UNIVERSITY OF CALIFORNIA, IRVINE. Ecient Structures for Digital Communication Systems THESIS

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1 UNIVERSITY OF CALIFORNIA, IRVINE Ecient Structures for Digital Communication Systems THESIS submitted in partial satisfaction of the requirements for the degree of MASTER OF SCIENCE in Electrical and Computer Engineering by Hung-Kang Liu Thesis Committee: Professor Nader Bagherzadeh, Chair Professor Fadi Kurdahi Professor Nikil Dutt 1997

2 c 1997 Hung-Kang Liu

3 The thesis of Hung-Kang Liu is approved: Committee Chair University of California, Irvine 1997 ii

4 Dedication To my parents Pei-Kuang and Jin-Lien, my sister Shi-Ru and my brother Patrick. It has been said that life is but a series of obstacles, one challenge after another. The support they have provided me through the years has made overcoming these challenges much easier. iii

5 Table of Contents List of Figures : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : vi List of Tables : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : Acknowledgments : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : Abstract : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : viii ix xi Chapter 1 Introduction : : : : : : : : : : : : : : : : : : : : : : : : : : : Motivation For This Thesis : : : : : : : : : : : : : : : : : : : : : : : Scope of The Thesis : : : : : : : : : : : : : : : : : : : : : : : : : : : 3 Chapter Mbps Transceiver Overview : : : : : : : : : : : : : Modulator : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : Modulator Structure : : : : : : : : : : : : : : : : : : : : : : : Modulator Implementation : : : : : : : : : : : : : : : : : : : : Demodulator : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : Demodulator Structure : : : : : : : : : : : : : : : : : : : : : : Demodulator Implementation : : : : : : : : : : : : : : : : : : 17 Chapter 3 Equalizer for Mbps Transceiver : : : : : : : : : : : Equalizer and NEXT Canceller Overview : : : : : : : : : : : : : : : : LMS Algorithms : : : : : : : : : : : : : : : : : : : : : : : : : : : : : Startup Sequence : : : : : : : : : : : : : : : : : : : : : : : : : : : : : Challenges of Implementing the Equalizer : : : : : : : : : : : : : : : First Improvements : : : : : : : : : : : : : : : : : : : : : : : : : : : : Improvements to the DFE and NEXT Canceller : : : : : : : : : : : : Improvements to the FFE : : : : : : : : : : : : : : : : : : : : : : : : Using a MAU : : : : : : : : : : : : : : : : : : : : : : : : : : : Modied Complex Multiply : : : : : : : : : : : : : : : : : : : Conservation of QMSR Blocks : : : : : : : : : : : : : : : : : : : : : : Final Results For The Equalizer : : : : : : : : : : : : : : : : : : : : : 41 iv

6 Chapter Mbps Modulator and Demodulator : : : : : : : : Shaping Filters : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : Multi-rate Design : : : : : : : : : : : : : : : : : : : : : : : : : : : : : Modulator Implementation : : : : : : : : : : : : : : : : : : : : : : : : Demodulator Implementation : : : : : : : : : : : : : : : : : : : : : : The Overall Chip Architecture : : : : : : : : : : : : : : : : : : : : : : Simulation Results and Final Layout : : : : : : : : : : : : : : : : : : 58 Chapter 5 Design Methodology and Tools : : : : : : : : : : : : : : : Design Methodology : : : : : : : : : : : : : : : : : : : : : : : : : : : Tools : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 63 Chapter 6 Conclusion : : : : : : : : : : : : : : : : : : : : : : : : : : : : 66 Bibliography : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 68 v

7 List of Figures 2.1 Block diagram of the Mbps transceiver. : : : : : : : : : : : : : CAP Constellation. : : : : : : : : : : : : : : : : : : : : : : : : : : Frequency and impulse response of the propagation loss model. : : : : Frequency response of the NEXT loss model. : : : : : : : : : : : : : : Impulse response of the NEXT loss model. : : : : : : : : : : : : : : : Modulator structures. : : : : : : : : : : : : : : : : : : : : : : : : : : : Block diagram of the modulator and demodulator. : : : : : : : : : : : Impulse responses of modulator lters. : : : : : : : : : : : : : : : : : FIR using ROMs. : : : : : : : : : : : : : : : : : : : : : : : : : : : : : Modulator sub-lters replaced with ROMs. : : : : : : : : : : : : : : : Demodulator structures. : : : : : : : : : : : : : : : : : : : : : : : : : Impulse responses of demodulator lers. : : : : : : : : : : : : : : : : Main tap location in the FIR lter in the FFE. : : : : : : : : : : : : MRU in the overall scheme of the DFE and NEXT canceller. : : : : : Multiplier Replacement Unit (MRU). : : : : : : : : : : : : : : : : : : Pie chart of preliminary gate count. : : : : : : : : : : : : : : : : : : : MAU within an the FFE : : : : : : : : : : : : : : : : : : : : : : : : : Function of the rst half of the MAU. : : : : : : : : : : : : : : : : : : Function of the second half of the MAU. : : : : : : : : : : : : : : : : Partial product generator for the most signicant TBR. : : : : : : : : Traditional complex multiply circuit. : : : : : : : : : : : : : : : : : : Modied complex multiply circuit. : : : : : : : : : : : : : : : : : : : Proposed structure with the QMSR moved closer to input. : : : : : : XY plots : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : Structure for a CAP modulator and demodulator : : : : : : : : : : : Poly-phase decomposition for interpolation. : : : : : : : : : : : : : : Poly-phase decomposition for decimation. : : : : : : : : : : : : : : : Merging the I and Q sub-lters. : : : : : : : : : : : : : : : : : : : : FIR non-grouped structure vs grouped structure. : : : : : : : : : : : General grouped structure. : : : : : : : : : : : : : : : : : : : : : : : Grouping for symmetric lter. : : : : : : : : : : : : : : : : : : : : : Detailed structure for the modulator. : : : : : : : : : : : : : : : : : Modulator timing diagram. : : : : : : : : : : : : : : : : : : : : : : : 51 vi

8 4.10 Original demodulator timing diagram. : : : : : : : : : : : : : : : : : A simple demodulator structure. : : : : : : : : : : : : : : : : : : : : The modied demodulator structure. : : : : : : : : : : : : : : : : : : The nal demodulator structure. : : : : : : : : : : : : : : : : : : : : The overall chip structure. : : : : : : : : : : : : : : : : : : : : : : : Demodulator output. : : : : : : : : : : : : : : : : : : : : : : : : : : Chip layout : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : Design ow. : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 64 vii

9 List of Tables 2.1 Summary of the Mbps transceiver specications. : : : : : : : : Function table for the MRU. : : : : : : : : : : : : : : : : : : : : : : : Comparison of MRU with a conventional multiplier. : : : : : : : : : : Preliminary gate count before any enhancements. : : : : : : : : : : : Comparison of two 16x15 multipliers. : : : : : : : : : : : : : : : : : : Gate count and critical path delay of various multiply structures. : : Gate count of the two parts to the MAU. : : : : : : : : : : : : : : : : Summary of the nal structure. : : : : : : : : : : : : : : : : : : : : : ATM Forum specications for Mbps transceiver. : : : : : : : : The dierent operational modes of the chip. : : : : : : : : : : : : : : Operating conditions under which the circuit was simulated. : : : : : Chip summary. : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 61 viii

10 Acknowledgments First and foremost I would like to thank my two advisors, Dr. Nader Bagherzadeh and Dr. Fadi Kurdahi. Their faith and condence in me, from my days as an undergraduate, to the nale of my graduate school experience, has been remarkable. Their experience and knowledge has guided this project from its inception to its conclusion. To both of them I am grateful for the vast opportunities to learn, to explore and more importantly to mature in all aspects of being a researcher, a professional, and an engineer. Also, I would like to thank Dr. Nikil Dutt for serving in my thesis committee. In addition, I would like to extend my gratitude to Farzad Etemadi and Guangming Lu, my colleagues throughout the course of this work. Their expertise injected fresh ideas to our projects, and their relaxed demeanor and enthusiasm made them a pleasure to work with. I would also like to thank Je Putnam for patiently answering questions regarding his work. In addition, I would also like to thank the rest of the members of the Advanced Computer Architecture Laboratory and the Fault Tolerant Multicomputing Laboratory: Brian, Hiro, Honge, Koji, Lingling, Mark, Marcelo, Minghau, Omar, Simin, Steve and Xingming. They made the environment in the lab, as unbelievable as it may seem... FUN! From lively discussion regarding dierent cultures, religion, sports, world events or any other trivia, to pizza parties, and occasional lunches, the last couple of years ix

11 have been great. In retrospective, I think I am a much richer person for having had the opportunity to know, even to a small extent, each and everyone of them. I would also like to thank Robert Heaton for his eorts, especially in the beginning of this project. Finally, I would like to thank Standard Microsystems Corporation and Kelly McClellan for their support in this project, and for providing us an opportunity to fabricate one of our designs. x

12 Abstract of the Thesis Ecient Structures for Digital Communication Systems by Hung-Kang Liu Master of Science in Electrical and Computer Engineering University of California, Irvine, 1997 Professor Nader Bagherzadeh, Chair The commercial growth of the Internet has triggered a demand for higher bandwidth in both local area networks (LAN) and wide area networks (WAN). In the LAN community, the ATM standard for Mbps and Mbps transmission over copper wires was adopted to meet this demand. Unfortunately, the challenge in using a copper wire is the large amounts of distortion it introduces. The two main distortions that destroy the signal in the case of the Mbps transceiver are propagation loss and Near End Cross Talk (NEXT). Propagation loss is caused by the parasitic capacitance and resistance in a copper wire. NEXT at a receiver is caused by a nearby transmitter which sends a signal using the same frequency bandwidth as the signal that is being received. Interests in using DSP techniques to counteract the eects of noise is growing. An ecient all-digital equalizer structure sucient to counteract the eects of propagation loss and NEXT will be the focus of the thesis. xi

13 In addition, an all-digital modulator and demodulator structure for the Mbps ATM transceiver will also be discussed. xii

14 Chapter 1 Introduction The amount of noise introduced to a signal is the most inuential parameter in determining the rate at which information can be delivered from one computer to another. Fiber optics cables, known for the little noise they introduce, can transfer data at much higher speed and over longer distances than conventional copper wires. The problem with ber optics is that the infrastructure to support it is not present and may not be present in the next few years. For now, copper wires is the popular choice since it is already present in the infrastructures of most buildings. The ATM Forum has created a standard for an ATM LAN transceiver for CAT-3 copper wires [1] [2] [3]. The transceiver is to operate at a bit rate of Mbps, with a baud rate of MBaud. It is expected that as a result of noise, the transmission of a signal through copper wire will signicantly degrade the quality of the signal. The two primary sources for noise in this transceiver are: Propagation Loss: Which is caused by the resistive loss of copper wires. Near end cross talk (NEXT): Which is caused by electro-magnetic emanations from a nearby transmitter. 1

15 In addition, the ATM forum has also approved a similar standard for transmission over copper wire at Mbps [4] also for transmission over copper wires Motivation For This Thesis Minimizing the eects of both propagation loss and NEXT is imperative for the reliable operation of the transceiver. Adaptive lters have traditionally been used to lter out these distortions [5] [6] [8]. The advantage of an adaptive lter is the ability of the lter to change its transfer function based on the quality of the signal it has received. The transfer function is changed until the signal quality improves to the point where the lter can no longer make any further improvements to enhance the quality of the received signal. This adjustment to the lter taps is made as the signal is being transmitted, in other words in real time. The disadvantage of an adaptive lter is the large chip area required to implement such a lter. The adaptive lter is basically a complex FIR lter with an extra circuit for an algorithm to adapt the taps of the lter. A typical complex FIR lter is almost the equivalent of four regular FIR lters because of the complex arithmetic involved. In addition to minimizing the eects of noise, eciency in the implementation of various components used in communication systems is also investigated in this thesis. Components such as the modulator and demodulator can consume large areas of silicon. Improved structures are presented in this thesis to minimize the size of these circuits, hence reducing the cost of building such a system.

16 1.2 Scope of The Thesis 3 This thesis is separated into three major sections. The rst section involves discussion of the basic blocks of the Mbps transceiver with an extra focus on the modulator and demodulator. This includes the transfer function of the modulator and demodulator lters, the structure of the modulator and demodulator, and nally some implementation issues. In addition, a discussion on the overall picture of the physical layer of ATM will be presented. The second section will focus on the equalizer and NEXT canceller of the transceiver. Specically, it will look at dierent methods to construct a more ecient equalizer and NEXT canceller without having to sacrice too much signal quality. The third section of this thesis will cover the design and implementation of a modulator and demodulator for a Mbps ATM transceiver [4]. The section will cover the design of the modulator and demodulator from the initial lter design, to the various optimization methods, to the nal layout.

17 Chapter Mbps Transceiver Overview The target specication for the Mbps transceiver, specied by the ATM Forum, is discussed in [1]. A summary of the transceiver specications is shown in Table 2.1. The system level design issues are presented in [2] [3] [5] [7]. The transceiver will send data at Mbps with a symbol rate of MBaud. In addition, the transceiver will have a scrambler and descrambler, an encoder and decoder, a modulator and demodulator, an analog to digital converter, a digital to analog converter, a PLL, equalizer and NEXT canceller. The block diagram of the transceiver is shown in Figure 2.1. In Figure 2.1a, incoming bits enter the transceiver serially and are \randomized" by the scrambler. Among some of the benets of \randomizing" a signal are [3]: To facilitate the operation of the receiver functions. Specically, timing recovery and adaptive equalization. Reduce the amount of electro-magnetic radiations that emanate from UTP wiring. After the bits have been \randomized", the bits are sent to the encoder where they are mapped to a point in the 16-CAP constellation. As shown in Figure 2.2a, 4

18 5 Input Bits Scrambler I Q Modulator D/A To Channel Model Encoder (a) Transmitter From Channel A/D Demodulator Equalizer Descrambler Output Bits Clock Generation Timing Recovery Decoder (b) Receiver From Demodulator FFE Error DFE NEXT Canceller Quantizer Error Output From Another Transmitter To Decoder Error (c) Equalizer with FFE, DFE, and NEXT Canceller Transmitter Channel Model + Receiver NEXT Model Transmitter (d) Position of the Models Figure 2.1: Block diagram of the Mbps transceiver.

19 6 the rst two bits that enter the encoder, b1 and b2, determine which quadrant in the 16-CAP constellation shown in Figure 2.2b to map to. The next two bits to enter the encoder, b3 and b4, determine which point in the quadrant to map to. The output of the encoder is a complex value whose real component will be referred to as the I value and whose imaginary component will be referred to as the Q value. The I and Q values will take on one of four signal levels, 1 and 3, based on which point and which quadrant in the constellation the bits map to. In the constellation shown in Figure 2.2b, the Q value corresponds to the Y-axis and the I value corresponds to the X-axis. As an example, if b1, b2, b3 and b4 had the values 0, 1, 1 and 0 respectively, then the Q value would take on the signal level +1 and the I value would take on the signal level?3. These two values are sent from the encoder to the CAP (Carrierless Amplitude and Phase modulation) modulator. The modulator reshapes the signal and creates a passband signal from the I and Q signals. After modulation, the digital signal is converted to an analog form by an Digital to Analog Converter. After the conversion to an analog form, the signal is low pass ltered to remove out of band images, and sent over the CAT-3 wire to the receiver. In Figure 2.1b, the distorted signal from the channel arrives at the receiver. The analog signal is rst low pass ltered to remove any aliasing eects. It is then converted into its digital form and sent to the demodulator. The demodulator takes the passband signal and eliminates the outer band noise. At this point, the sampling of the A/D may not be at the ideal sampling point of the signal. To remedy this problem, the timing recovery unit will take the demodulated output and will recover the correct timing phase so the A/D will sample at the right phase. The signal then goes through equalization to remove any noise introduced by the propagation loss

20 7 Symbol n Symbol n+1 First Bit b1 b2 b3 b4 b1 b2 b3 b4 Quadrant Point in Quadrant (a) Q I (b) Figure 2.2: 16-CAP Constellation. and NEXT. The slicer will take the output of the equalizer and produce two results. The rst is the approximated value of the symbol value (i.e. the value would be approximated to +3, the value -1.1 will be approximated to -1). The second is the dierence between the approximated value and the actual value at the output of the equalizer. This value is the error term that is used to update the lter taps in the equalizer. After approximation by the slicer, the signal is decoded back into a bit stream and de-scrambled back to its original bits. Figure 2.1c shows the equalizer unit. It consists of an FFE (Feed Forward Equalizer), a DFE (Decision Feedback Equalizer), and a NEXT (Near End X-Talk)

21 8 Parameter Bit Rate Baud Rate Carrier Frequency Specication Mbps MBaud MHz Excess Bandwidth 100% Channel 100m UTP-3 Bit Error Rate 10?10 SNR db Table 2.1: Summary of the Mbps transceiver specications. Canceller. The signal arriving at the receiver is usually distorted by the propagation loss and NEXT loss. It is the role of the equalizer blocks to adapt their transfer functions to counteract the eects of propagation loss and NEXT. Finally, Figure 2.1d shows the method used to simulate NEXT disturbance [7] [9]. A transmitter near a receiver sends a signal which interferes with another signal arriving at the receiver. The encoder outputs of the primary NEXT interferer will be sent to the receiver as input to the NEXT canceller. In order to verify the functionality of the the equalizer and NEXT canceller, the propagation loss and NEXT loss models were created. The analog channels were modeled as FIR lters with a sampling rate of sixteen times that of the sampling frequency in the digital portion of the circuit. The D/A was modeled as a repeat block followed by a reconstruction lter. The A/D was modeled as an anti-aliasing lter with a sampler.

22 Magnitude in db Tap value Frequency in MHz FIR filter taps Figure 2.3: Frequency and impulse response of the propagation loss model. The propagation loss model is specied in EIA/TIA standard for category 3 cables. The frequency response of the channel is given by Equation 2.1 [3]. The plot for the frequency response and impulse response of the channel is shown in Figure 2.3. q L(f) = 2:320 f + 0:238f (2.1) A realistic NEXT model was used for our simulations. The Frequency of the NEXT model is shown in Figure 2.4. The impulse response of the lter is shown in Modulator The modulator has the responsibility of shaping the symbols to make sure they t in the allocated bandwidth. The modulator takes the input signal and converts it into a passband signal using the allocated bandwidth.

23 10 20 Magnitude Response Magnitude in db Phase Response Phase in Radians Frequency in MHz Figure 2.4: Frequency response of the NEXT loss model Tap value FIR tap Figure 2.5: Impulse response of the NEXT loss model.

24 11 I g(t) Fc Cos(2* * *t) Fs To D/A I In-Phase Fc g(t)* Cos(2* * Fs *t) Quadrature To D/A Q g(t) Q g(t)* Sin(2* * Fc Fs *t) Fc Sin(2* * Fs *t) QAM CAP Figure 2.6: Modulator structures. In a QAM modulator shown in Figure 2.6a, the modulator is composed of two shaping lters with the transfer function g(t), two mixers (the multiply by sine and cosine), and one adder. The output of the shaping lter is sent to two mixers which modulate the signal to t in its allocated bandwidth. Since the two signals in the mixers are orthogonal to one another, the two values can be added and sent in the same channel as one signal. In the CAP modulator shown in Figure 2.6b, the mixers are embedded in the shaping lters, saving the need for two multipliers in the design. As specied in [1], the term g(t) refers to a square root raised cosine lter with the response: g(t) = 8 >< >: 4cos[2 t T ] [1?(4 t T )2 ] ; t 6= T 4 1; t = T 4 9 >= >; (2.2) The lter taps were generated using the Matlab routine presented in [10]. The discrete-time lter lter was generated by oversampling the analog lter four times the baud rate which helps avoid aliasing. The Nyquist Theorem states that in order to avoid aliasing, the discrete time signal must be sampled at twice the highest frequency term of the analog signal. The highest frequency term in the analog signal is MHz. Thefore to avoid aliasing, the signal must be sampled at MHz which also

25 happens to be four times the baud rate. This has a drawback in that the modulator 12 has to operate at 4x the baud rate. The In-Phase and Quadrature lters in the modulator consist of 12 tap FIR lters Modulator Structure Poly-phase decomposition was applied to the modulator. The modulator is composed of two 12 tap FIR lters which have undergone poly-phase decomposition [18]. The benet of a poly-phase decomposition comes about since most of the lter can be operating at the baud rate as opposed to the sampling frequency. The decomposition of two FIR lters from the modulator, to the structure shown in Figure 2.7, is presented in detail in [5]. This decomposed modulator has the advantage that most of the modulator is operating at the slow frequency of MHz instead of the MHz that would be required if no poly-phase decomposition has been performed. Figure 2.8 shows the impulse response of the In-Phase and Quadrature lters. Further savings in hardware can be attained in the digital circuit as a result of oversampling the analog lter four times every baud period. Since the carrier frequency(f c ) is the same as the baud frequency(f Baud ), and the sampling frequency(f s ) is four times the baud frequency, this reduces the multiplication of sine and cosine to the trivial values of 1; 0;?1. Since half the tap values will be multiplied by 0, the required lter size has essentially been reduced in half. The nal structure for the modulator is shown in Figure 2.7.

26 13 Modulator Demodulator Figure 2.7: Block diagram of the modulator and demodulator.

27 14 I Channel Impulse Response Q Channel Impulse Response Tap Coefficients Filter Taps Tap Coefficients Filter Taps In-Phase Filter Quadrature Filter Figure 2.8: Impulse responses of modulator lters Modulator Implementation Since the modulator input arrives from the encoder, it has the trivial values of 3, 1. This simple input set can be exploited to generate a more ecient modulator structure. Since the set of inputs is small, pre-multiplication of the inputs with the lter taps can be performed. In pre-multiplication, all the possible sets of inputs to a lter tap are multiplied and the results are stored in a look-up table. At run time, the inputs are used to access the look-up table therefore retrieving the multiplied output. Pre-multiplied values can be stored in a ROM or any other form of a look up table. An FIR using the pre-multiplication is shown in Figure 2.9. The input to the FIR is used as selection lines to the ROM. The benets gained with this approach is the elimination of every multiplication required in the modulator. This method replaces a multiplier with a simple ROM. Since the modulator structure, shown in Figure 2.7a, is composed of four sub- lter of three taps in length, a further optimization can be performed if the results of

28 15 Input Z -1 Z -1 ROM ROM ROM Output Figure 2.9: FIR using ROMs. each sub-lter is stored into a ROM. Since each sub-lter is composed of three taps, and each tap has only four possible values, a 64 entry ROM would be needed to store the values of the 64 possible outputs of the FIR. Figure 2.10 shows structure of the modulator with each sub-lter replaced by a ROM. By consolidating the sub-lters into a ROM, the adder that would otherwise be needed to add the tap values after multiplication are eliminated. 2.2 Demodulator The demodulator has the responsibility of taking the passband signal and recovering the I and Q components. In a QAM demodulator, Figure 2.11a, the passband signal is converted to baseband form by the mixers. The ~g(t) lters then recover the original signals. Note that for a QAM, the ~g(t) of the demodulator and g(t) for the

29 16 ROM I_Input Z -1 Z -1 ROM MUX To A/D ROM Q_Input Z -1 Z -1 ROM Figure 2.10: Modulator sub-lters replaced with ROMs. modulator must be matched lters. The ~g(t) from the demodulator and g(t) lter from the modulator are matched lters. Like the CAP modulator, the CAP demodulator, Figure 2.11b, also has the mixers embedded within the lters. In a CAP demodulator, the passband signal is sent to a passband lter which recovers the I and Q components. The impulse response of the CAP demodulator is shown in Figure Demodulator Structure Like the modulator, the demodulator also enjoys the benet of every other tap being 0. Poly-phase decomposition was also applied to the demodulator and is shown in detail in [5]. The nal demodulator structure is shown in Figure 2.7. Note that

30 17 Fc Cos(2*PI* Fs *t) From A./D ~ g(t) ~ g(t) I Q From A./D Fc g(t)* Cos(2*PI* Fs *t) g(t)* Sin(2*PI* Fc Fs *t) I Q Fc Sin(2*PI* Fs *t) QAM CAP Figure 2.11: Demodulator structures. the nal demodulator structure has most of the circuit operating at 25.92MHz as opposed to the baud rate of 12.96MHz. This was done in anticipation for an alldigital timing recovery unit similar to the one presented in [5] [11]. In the anticipated timing recovery scheme, the timing recovery unit works on every half-baud sample, hence it is necessary to have the demodulator output results at 25.92MHz Demodulator Implementation The input to the demodulator arrives from the A/D converter. An 8 bit A/D converter was deemed suciently accurate for the purposes of the Mbps transceiver [5]. Unfortunately, given the demodulator structure shown in 2.7, that means that if the demodulator would have been constructed using a ROM, the ROM would require [2 8 ] 6 entries, which is clearly not practical. Instead, the approach of approximating lter taps using CSD representation, such as the one used in [12] was adopted. The coecients of the demodulator lters were converted from 2's complement, to CSD. The conversion algorithm for recoding an M-bit 2's-complement number x to its CSD representation y is as follows [13]:

31 I Channel Impulse Response 0.4 Q Channel Impulse Response Tap Coefficients Tap Coefficients Filter Taps Filter Taps I channel lter Q channel lter Figure 2.12: Impulse responses of demodulator lers. 1. Let x M = x M?1 and C 0 = For i = 0; : : : ; M? 1 Let C i+1 = x i x i+1 + x i C i + x i+1 C i. 3. For i = 0; : : : ; M? 1 Let y i = x i + C i? 2C i+1. Notice that the \+" in step 2 is a logical OR, while the \+" in step 3 is an arithmetic sum. As an example, consider? 3 8 = (1:101) 2 0 s?complement = (0:101) CSD. Every binary number can be exactly represented by a unique CSD number. A fractional decimal number, however, may not have an exact CSD equivalent, since, it may not has a nite binary representation. Therefore, the number of bits of the CSD representation of a fractional decimal number depends on the tolerable truncation error. For even further savings, the maximum number of CSD that were used to represent a number was four. In other words, at most four CSDs were used to represent a single number.

32 19 The advantages of CSD representation is in the ecient hardware structure that can be used to implement multiplication of CSD. As an example, suppose a coecient in 2's complement notation was approximated to? The resulting circuit to implement a multiply by this number would require two hardwired shifts, and a subtractor which is by far more ecient than a full multiplier.

33 Chapter 3 Equalizer for Mbps Transceiver 3.1 Equalizer and NEXT Canceller Overview The FFE (Feed Foward Equalizer), DFE (Decision Feedback Equalizer), and NEXT canceller are used to remove distortion introduced by the channel and NEXT. In the ideal sampling point at the receiver, under ideal conditions, there should be no ISI (Intersymbol Interference). This is due to the fact that the cascade of the transmit and receive lter is a Nyquist lter where the sampling point at a symbol has no oset due to the inuence of the other symbols since Nyquist lters cross 0 at every symbol period with the exception of the center point. Unfortunately, the channel can change the phase of each symbol with respect to one another. Therefore at the sampling point of a symbol, an oset from the past and future symbols will be added to the current symbol, hence ISI. In addition, NEXT is introduced on a receiver when a nearby transmitter sends information across a wire near the wire that is receiving data. 20

34 21 Th FFE is designed to remove the inuence of the future symbol on the current symbol and the DFE is designed to remove the inuence of past symbols on the current symbol. The NEXT canceller is designed to remove the eects of the NEXT distortion. The three circuits are essentially complex adaptive FIR lters using the LMS algorithm to update the lter tap values. Each lter takes a complex number as an input and uses the complex error to update the lter taps. The error is generated as the dierence between the equalized value subtracted by the value predicted by the 16-CAP slicer. The FFE is composed of a six tap complex FIR. The DFE and NEXT canceller are composed of four taps, complex, FIR lters. As shown in Figure 2.1c, the FFE input is taken from the output of the demodulator, the DFE input is taken from the 16-CAP slicer, and the NEXT canceller input comes from the output of a 16-CAP encoder of a neighboring transceiver which is also the primary NEXT interferer [7]. 3.2 LMS Algorithms The LMS equations used for each block are as follows: h k;f F E (n + 1) = h k;f F E (n)? F F E e(n)x F F E(n? k) (3.1) h k;df E (n + 1) = h k;df E (n) + DF E e(n)x DF E(n? k) (3.2) h k;ec (n + 1) = h k;n C (n) + N C e(n)x N C (n? k) (3.3) The term e(n) refers to the error of the signal after the slicer, is the stepsize, x xxx is the complex conjugate of the input to the respective lter. The stepsizes used for the FFE, DFE, and NEXT canceller were 2?6, 2?10, 2?14 respectively. Since the stepsizes

35 were chosen to be powers-of-two, the multiplication that would have been required can be replaced with a hardwired shift [5] [8]. 22 In other works [5] [6], two dierent stepsizes were used, one for initialization, and the other for steady state operations. The larger stepsize was used for quick convergence during initialization when the lter taps are starting from their initial values. A larger stepsize allows the lter to arrive at its steady state value much more quickly. The smaller stepsize was used for steady state operations since during steady state operations, there is no need to have to quickly adjust the lter taps. By using a smaller stepsize during steady state operation, the ner granularity allows the lter taps to approach the ideal tap values needed to remove the noise. Since the ATM specication [1] allocates 500ms (relatively large, especially when comparing to the ethernet transceivers) for the circuit to arrive at a stable point, quick acquisition at the initialization was not necessary. As a result, to simplify the circuit, only one stepsize was chosen. 3.3 Startup Sequence Blind equalization was used to initialize the equalizer. Blind equalization means there is no pre-determined training sequence that is sent by the transmitter nor is any training sequence expected at the receiver. Blind equalization has its benet in that there is no need for any more additional circuit to locate this training sequence, and to train the FFE, DFE, and NEXT canceller [5] [6]. With blind equalization, the FFE, DFE, and NEXT can basically behave as they would normally do in steady state operation. Blind equalization is performed by rst transmitting random, 4-CAP

36 23 Main Tap Complex Input Z Z... Z LMS LMS LMS X X X Complex Output Figure 3.1: Main tap location in the FIR lter in the FFE. symbols. After initial convergence by the equalizer, 16-CAP symbols were sent. A period of time is then allocated to allow the lter taps to settle, after which, any valid data can be sent. In addition, the FFE contains a tap known as the main tap which is initialized to 1+j0 where as all the other taps are initialized to 0+j0. In the case of this FFE, the main tap was chosen to be the tap furthest from the input, as shown in Figure 3.1. In addition to the above, a specied startup sequence shown in more detail in [5] [6] was used to ensure proper convergence. The following is the startup sequence used: 1. Set main equalizer tap to 1+j0 and all other taps to 0+j0. 2. Enable main tap with decision slicer in 4-CAP mode. 3. Enable all equalizer taps with decision slicer in 16-CAP mode. Note that the startup sequence does not take into account the time for timing recovery. It was assumed that timing recovery has already been performed and the A/D is sampling the data at its ideal sampling point.

37 3.4 Challenges of Implementing the Equalizer 24 Since the equalizer in the Mbps transceiver design has to operate with a clock frequency of MHz, minimizing the critical path delay was not an issue, especially when the performance evaluation was performed using 0:35m technology. The challenge of constructing this FFE, DFE, and NEXT canceller is to design them using as little silicon as possible, while not sacricing the required 23.30dB SNR. In the scope of this thesis, the reduction in area is performed at the algorithmic level. In other words, dierent algorithms are tried to minimize the area of the chip. An example of a non-algorithmic approach is if custom layout was used for creating the chip area. In that case, reduction of area would be achieved at the chip level. Since a complex, adaptive, FIR lter can take up quite a bit of chip area, the total area required by the combined FFE, DFE, and NEXT canceller can be quite large. Adding a tap to a complex, FIR lter is the equivalent to adding four taps in a real FIR. In addition, there is the extra circuit required to implement the adaptation algorithm, in this case, the LMS algorithm. Fortunately, the equalizer and NEXT canceller can aord to approximate values. With the case of the equalizer and NEXT canceller, it is not as important to preserve an accurate a value of the lter tap as it is to preserve the monotonic behavior of the lter tap. The monotonic behavior can usually assure that the lter tap will arrive at its stable value [14]. Though quite a bit of approximation can be tolerated in the equalizer and NEXT canceller, too much approximation can hamper the steady state performance of the lter in terms of signal quality. A careful balance is needed to ensure that the system can deliver signal quality that conforms to the minimum specied requirement (23.30dB) and that the system is as hardware ecient as possible. In this section, an analysis of

38 the improvements in the equalizer and NEXT canceller is presented. In addition, an analysis of the cost, in terms of the loss of signal quality, is discussed First Improvements The rst improvement performed in the equalizer and NEXT canceller structure was to move from a full precision LMS algorithm to a sign LMS algorithm. This means for the LMS algorithm for the FFE, equation h k;f F E (n + 1) = h k;f F E (n)? F F E e(n)x F F E(n? k) (3.4) became h k;f F E (n + 1) = h k;f F E (n)? F F E sign(e(n))x F F E (n? k) (3.5) where e(n) was replaced with its signed version (sign(e(n))). The same applies to the LMS algorithms for the DFE and NEXT canceller. In addition, the stepsize is chosen to be a power of 2 so that a simple hardwired shift can be used instead of a multiply by a constant. These techniques have already been used by [5] [8] and are considered the default for this work. After this initial improvement, the SNR at the output of the slicer was 27.1dB, giving approximately a little over 4dB to sacrice to reduce additional area. 3.6 Improvements to the DFE and NEXT Canceller The DFE and NEXT canceller are very similar circuits. Both are four taps, complex, FIRs with the same adaptation algorithm (refer to Equation 3.2 and 3.3).

39 26 Complex Input Z Z... Z LMS LMS LMS MRU VS X MRU VS X MRU VS X Complex Output Figure 3.2: MRU in the overall scheme of the DFE and NEXT canceller. The only dierence between these two circuits is the stepsize. The NEXT canceller uses a stepsize of 2?14 as opposed to 2?10 for the DFE. The main improvement in the DFE and NEXT has already been made with the conversion from LMS to sign LMS, and choosing the stepsize as a power of two. Since the LMS circuit has already been reduced, the focus is shifted to the FIR portion of the DFE and NEXT canceller. The extra improvement that can be made is to exploit the trivial inputs to the DFE and NEXT canceller to simplify multiplication. The input to the DFE is the approximated value from a 16-CAP slicer (or 4-CAP in the case of the initialization). The input of the NEXT canceller is the output of an encoder from the transmitter that is the main NEXT interferer. Both of these inputs have the trivial values of 3; 1. Since the DFE and the NEXT canceller are adaptive lters, using a ROM to hold all the potential value similar to the modulator is out of the question. A simpler circuit can be built to emulate the multiplication without sacricing too much accuracy. For simplication, the circuit will be called a MRU (Multiply Replacement Unit). Figure 3.2 shows how the complex FIR will be changed by using a MRU block instead of a multiplier block.

40 27 Multiplicand Function 001 = +1 Output = Multiplier 011 = +3 Output = shift Multiplier by one, add to Multiplier 111 = -1 Output = invert Multiplier 101 = -3 Output = invert (shift Multiplier by one, add to Multiplier) Table 3.1: Function table for the MRU. Table 3.1 describes the functionality of this block. There are two inputs to a multiply unit, a multiplicand, and a multiplier. The possible sets of inputs to the multiplicand are 3 and 1. The multiplier is the output of the LMS unit, and is assumed to change every clock cycle. Basically, if the multiplicand is +1, then the circuit passes the multiplier to the output. If the multiplicand is?1, then the multiplier bits are inverted and passed to the output. If the multiplicand is +3, then multiplier is shifted by one to the left, and added to the original multiplier. If the multiplicand is?3, then the result of the multiply by +3 is inverted. A proposed block which implements the functions outlined in Table 3.1 is shown in Figure 3.3. The block consists of two sets of inverters, a 4x1 MUX, and an adder. As can be seen from the result in Table 3.2, the gate count of this MRU is essentially half the gate count of a regular multiplier. The issue now is the loss in signal quality incurred with this new circuit. A multiplication by +1 introduces no additional error since passing the signal to the output is exactly the same as a multiplying. Multiplication by +3 also introduces no errors. Nothing is lost in the shift, nor is anything lost when adding the original

41 28 Coefficient Shift Left 1 + MUX Output Figure 3.3: Multiplier Replacement Unit (MRU). value to the shifted value. Multiplication by?3 and?1 introduces an error in the lsb (least signicant bit). Normally, taking a two's complement of a number requires two steps: inverting all the bits, and adding a one to the least signicant bit. In this case, for interest of saving size, the second step is not performed. Therefore the total error introduced in this step is the equivalent of 1lsb. 2 The 1 2 comes about because if there is a random signal, then half the time the signal will be positive and half the time negative. The error only comes when there is a negative signal. Therefore half the time, there is a lsb error. So the total error of all values is 1 2 lsb. Type Multiplier MRU Gate count gates gates Table 3.2: Comparison of MRU with a conventional multiplier.

42 29 Name Gate Count % of total area FFE :9% DFE :9% NC :8% Others 886 0:1% Total % Table 3.3: Preliminary gate count before any enhancements. 3.7 Improvements to the FFE In the transceiver, the FFE dominates the area accounting for 65% of the total area (See Table 3.3 and Figure 3.4). The extra size of the FFE is due to the extra 2 taps the FFE requires, and to the large bitwidth of the input. Whereas the inputs to the DFE and NEXT canceller were trivial 3 bits wide, the input to the FFE is 16 bits wide. That translates to wider tap delay lines, and larger multiplication blocks. Therefore, reducing the FFE area is critical for an ecient equalizer design. Two dierent approaches were used to reduce the area of the FFE. The rst approach involved replacing the multiply block in the FIR portion of the FFE with a smaller circuit which would produce an approximation of a multiply operation. We call this circuit the MAU (Multiplier Approximation Unit). The second approach restructures the traditional way complex multiplication is performed to produce a more hardware ecient method for performing complex multiply.

43 Using a MAU Figure 3.4: Pie chart of preliminary gate count. Since the LMS portion of the FFE has already been simplied by choosing a powers-of-two term for the stepsize and using the signed LMS algorithm, the multiplier in the FIR portion of the FFE consumes most of the FFE area. In the Mbps transceiver, this complex multiplier was constructed out of four 16 bit by 15 bit real multiplier and some additional adders and subtractors. Considering this is a complex six tap FIR, this means the FFE will require 24 real multipliers. Unlike the DFE and the NEXT canceller, the inputs to this multiplication is not by any means trivial. What can be done, however, is to use the approximation method specied in [14]. In this method, an additional circuit, which will be referred to as the MAU, converts the 2's complement numbers into signed powers-of-two terms on the y. When multiplying with signed powers-of-two terms multiplication is reduced to hardwired shifts, adders and subtractors. Figure 3.5 shows where the MAU will the placed within the FFE.

44 31 Complex Input Z Z Z LMS LMS LMS QMSR QMSR QMSR PP_SUM MAU PP_SUM MAU PP_SUM MAU Complex Output Figure 3.5: MAU within an the FFE The MAU is a basic multiply approximate block based on the signed powersof-two conversion algorithm. There are two steps to this approximation, the rst is a conversion of the 2's complement numbers into a signed powers-of-two representation where each bit pair has at most one non-zero number. The general idea of this function is shown in Figure 3.6A. A bit pair i + 1; i is converted to a three bits representation sign; i + 1; i where either i or i + 1 is non-zero. The sign determines whether the bit pair represents a positive or negative number. If both i and i + 1 are zero, then sign is meaningless. As an example, suppose sign is 0, and i + 1 is a positive integer, then the number the bit pair represents is 2 i+1. If the sign is a one, then the number is?2 i+1. With the Mbps transceiver, the 16 bit number that is the input to the FFE is converted to a three bit representation (TBR). This 16 bit number is grouped into 8 bit pairs. Those 8 bit pairs produce 8 TBR values. Therefore, since within a TBR, at most there can only be one non-zero term, there is a maximum total of 8 non-zero bit after the conversion. After these 8 TBR terms have been generated, they are grouped into a most signicant section and a least signicant section as shown in Figure 3.6B. A block that accomplishes the function of converting a 2's complement number into a TBR and grouping the TBR into a most signicant half

45 32 A Bit Pair Multiplier i+1 i sign i+1 i B Most Significant half Least Significant half These are 3 bit approximations of the orignal value Figure 3.6: Function of the rst half of the MAU. and least signicant half will be referred to as a QMSR (Quasi Minimal Signed-digit Representation). The second step to the MAU approximation is to generate the partial products based on the TBR generated in step 1. If all 8 TBRs were used, 8 partial products would be generated and seven adders would be needed to sum the results. Since most of the time, the eight partial products terms are not all non-zero, a further approximation that can be made is to try to use only four partial products, therefore requiring only three adders to produce the results. To accomplish this, rst the 8 TBRs are separated into two groups. One group contains the most signicant TBRs. The second group contains the least signicant TBRs. The most signicant TBRs in both groups are joined into one group to generate one partial product. Then the second most signicant TBRs in both groups are joined to generate another partial product and so on. Figure 3.7 shows the block diagram of the circuit to calculate the four partial products terms from the 8 TBRs. In addition, the circuit also adds

46 33 C Most Significant half Least Significant half shifted versions of multiplicand Multiplicand... Partial Product Calculator Partial Product Calculator Partial Product Calculator Partial Product Calculator Multiply Output Figure 3.7: Function of the second half of the MAU. the four partial product terms to produce a nal multiply result. This circuit will be referred to as the PP SUM. Calculation of the partial product out of two TBRs is simple. If either the i + 1 or i term in the more signicant TBR is non-zero, then that TBR is used, otherwise the more signicant TBR contains one non-zero bit, then that TBR is used, otherwise, the least signicant one is used. The TBR that is chosen will perform a shift and a negate if necessary on the incoming 2's complement number (in this case, the output

47 34 X 0 X 1 S15 S 7 d15 d14 d 7 d 6 X 7 X 8 MUX MUX MUX MUX Partial Product Figure 3.8: Partial product generator for the most signicant TBR. of the LMS unit), which will produce one partial product. Figure 3.8 shows a circuit that will perform this task for the most signicant TBRs in both halves. The benet of using a MAU is to replace a multiply operation with three adders and additional logic such as the logic used to extract the signed powers-of-two terms. It is hoped that the three adders and additional logic required for TBR extraction and partial product generation will be smaller than the multiplier. A comparison was made between two 16x15 bit multiplier. One was a conventional 2's complement multiplier, where as the second used the MAU method. The results, which are summarized in Table 3.4, clearly indicated the savings gained by using a MAU. This type of implementation suers from errors introduced during the approximation. Assuming that all 8 TBRs of this number contains a non-zero bit, then since only four partial products are used to calculate the nal result, the least signicant TBRs will be essentially thrown away. This would produce the worst case error for this circuit.

48 35 Type Gate Count MAU Multiplier Table 3.4: Comparison of two 16x15 multipliers Modied Complex Multiply The conventional method to multiply two complex numbers is shown in Equation 3.6. (a + jb) (c + jd) = (ac? bd) + j(ad + bc) (3.6) A proposed modied version of a complex multiply is the following [15]: (a? b)d + a(c? d) = ac? bd (3.7) (a? b)d + b(c + d) = ad + bc (3.8) The benet of the modied version of a complex multiply is that one multiply step is exchanged for three adders. Since adders are much smaller than multiply blocks, there is an automatic savings in area just by applying this transformation with absolutely no loss in signal quality. In other words, this modied version of complex multiply should yield the same result as the conventional method for complex multiply. There is one drawback to this modication, and that is the critical path. As shown in Figure 3.9, the critical path for a traditional complex multiply requires only a multiply step and an adder. Figure 3.10 shows the structure and critical path for the modied complex multiply. The critical path in this case encompasses two adders and one multiply. Since critical path is not an issue in the FFE, the extra delay of using the modied complex multiply was not an issue. For higher speed systems, this

49 36 A B C D Real Imaginary Critical Path Figure 3.9: Traditional complex multiply circuit. method may pose to be a potential problem as it can signicantly increase the critical path. Keeping in mind the modication presented earlier, there is no multiply components in the FFE. The multiply blocks, in the FIR portion of the FFE, have been replaced with MAUs. Gate Count Critical Path Delay Conventional Complex Multiplier ns Conventional Complex Multiplier w/ MAU block ns Modied Complex Multiplier w/ MAU block ns Table 3.5: Gate count and critical path delay of various multiply structures.

50 37 A B C D Real Imaginary Critical Path Figure 3.10: Modied complex multiply circuit. Table 3.5 gives a summary of the dierent complex multiply structures. The rst item in the table is a conventional complex multiplier using full multiply blocks. The second item in the table is a conventional complex multiplier using the MAU block instead of the multipliers. The nal item in the table is the complex multiply block using the modied algorithm and the MAU block. As expected, a conventional complex multiply with regular multipliers required the largest area. The conventional complex multiply using the MAU required more gates than the modied version. However, the modied version has a worst critical path, as expected since the modied version's critical path has to go through an extra adder.

51 38 Name Gate Count % of total area in MAU QMSR % PP SUM % MAU % Table 3.6: Gate count of the two parts to the MAU. 3.8 Conservation of QMSR Blocks Another possible optimization in the FFE is to restructure it by using as little QMSR blocks in the MAU in hopes of minimizing size. As can be seen from Figure 3.5, the MAU is separated into two parts named QMSR and PP SUM. Two facts that need to be established rst before this discussion continues: The input to the QMSR portion of the MAU is the value in the tap delay line. The PP SUM portion in the MAU is much larger than the QMSR portion as can be seen in Table 3.6. Since the input to the QMSR comes from the tap delay line, it may seem logical to use one QMSR block to convert a value, and propagate that converted value across the tap delay line. That would mean, for each input to the FFE, the conversion to TBR is performed only once, whereas in the current state it has to be performed at every tap. Figure 3.11 shows this new proposed structure. Obviously from this structure, a new tap delay line is needed to hold the values of the converted value. This means the new system will need 2 tap delay lines, one to hold the converted value,

52 39 Complex Input Z -1-1 Z... Z -1 QMSR Z -1 Z Z -1 LMS LMS LMS PP_SUM PP_SUM PP_SUM Complex Output Figure 3.11: Proposed structure with the QMSR moved closer to input. the other to hold the original 2's complement values. The original 2's complement version must be maintained since the LMS needs this value to update the taps. A second question that arises from this modied structure is which complex multiply algorithm to use. In the previous section it was determined that the modi- ed complex multiply algorithm yielded some savings in size over the original complex multiply algorithm. The size saving was attributed to using only three regular multipliers (as opposed to four multiplier in the regular complex multiply) per complex multiply operation. The nal multiplier was replaced with three adders. The savings come since the area of three adders is smaller than the area of a multiplier. In this FFE, however, each regular multiply has been replaced with the MAU block. Hence the savings is not really a multiply block but a MAU block. In addition, the result from Table 3.6 shows the size of the PP SUM block to be much more signicant to the size of the QMSR, most of the savings comes from the lack of need to use the extra PP SUM block. There is one drawback in using the modied complex multiply in this new structure. Referring back to the Equation 3.7, in the context of this new structure, the terms A and B pass through the QMSR. However, the 2's complement values of A

53 40 and B need to be subtracted to produce the A? B term. This means that in order to produce the result of (A? B)D, a QMSR block must be added to convert the A? B term. This problem does not exist in the traditional complex multiply structure. Using a traditional complex multiply would, however, require use of four PP SUM blocks, where as the modied complex multiply requires only three PP SUM. Previously, it was been established that a PP SUM block is much than the QMSR. This means that choosing a traditional complex multiply structure over a modied complex multiply results in an extra PP SUM block. If a modied complex multiply is used, this results in a extra QMSR block. Since PP SUM is larger than a QMSR, the modied complex multiply was selected. The questions now remains, how much gain was achieved with this new structure? In order to justify the use of this new structure, essentially, 18 QMSR blocks (3 per each tap) that were saved by moving the QMSR blocks must be larger than the second complex tap delay line introduced by the new structure, two QMSR blocks required for conversion of the I and Q channel and one QMSR for each additional tap because of the modied complex multiply algorithm. To put it succinctly, 10 QMSR blocks must be smaller than a tap delay line which contains ve complex registers. The tap delay line, which is 24 bits wide (24 because of the 2's complement to TBR conversion in QMSR) requires about 1800 gates, considering 7.5 gates per each DFF. 10 QMSR blocks would require about 1077 gates. As can be seen from the result, this \improvement" really didn't yield any signicant amount of reduction at all. As a matter of fact the resulting area was even worse. Hence, this \improvement" was not include in the nal design.

54 41 Gate Count Chart Block tap Stepsize Bit Width Gate Count Percent of Total FFE 6 2? :7% DFE 4 2? :7% NEXT Canceller 4 2? :7% Others N/A N/A N/A 886 2:5% Total N/A N/A N/A % Table 3.7: Summary of the nal structure. 3.9 Final Results For The Equalizer area: The nal equalizer structure contains the following optimizations to conserve Signed LMS algorithm Stepsizes that are powers-of-two terms MRU unit in the DFE and NEXT Canceller MAU unit in the FFE Modied complex multiply algorithm in the FFE The results of the implementation of the equalizer and NEXT canceller is shown in Table 3.7. To make a point stated earlier, in spite of progress made to optimize the FFE, the FFE still accounts for 66.7% of the total gates. The simulation results are shown in Figure A noisy signal with propagation loss and NEXT distortion is

55 Demodulator Output 4 Demodulator Output Distorted input Undistorted output Figure 3.12: XY plots sent to the equalizer and NEXT canceller. As can be seen from the output, the signals t nicely into the 16-CAP constellation and the slicer and decoder should have no problems recovering the original bit-stream from the output. The nal SNR in the system was 24.3 db which is well within the required db.

56 Chapter Mbps Modulator and Demodulator Up to this point, most of the analysis has been focused on reducing area since the timing constraint in the Mbps transceiver was not a very large issue. In this chapter, the modulator and demodulator for the Mbps ATM transceiver is presented. Table 4.1 shows the specication for the Mbps adopted by the ATM Forum [4]. This chapter shows the design of the modulator and demodulator from its concept, to silicon. 4.1 Shaping Filters The modulator and demodulator each consist of two I and Q channel passband shaping lters, as shown in Figure 4.1. The impulse responses of the passband lters p(t) and ~p(t) are given by: p(t) = g(t)cos(2f c t) (4.1) ~p(t) = g(t)sin(2f c t) where g(t) is a low-pass lter, and f c is the carrier frequency. 43

57 44 Parameter Bit Rate Baud Rate Carrier Frequency Specication Mbps MBaud 15 MHz Excess Bandwidth 15% Passband ripple Stopband Attenuation SNR 0.4 db 30 db db Table 4.1: ATM Forum specications for Mbps transceiver. I p(t) p(t) I Q ~ p(t) ~ p(t) Q (a) (b) Figure 4.1: Structure for a CAP modulator and demodulator

58 45 The ATM specication states that g(t) is to be square root raised cosine pulse with an excess bandwidth of 15%. This nearly ideal lter has a very sharp transition band, which calls for high order FIR lters. In order to satisfy the ATM Forum square-root Nyquist specication while keeping the lter length in a reasonable range, an approximation approach was developed. The key point in this scheme is the allowable tolerance of the lter specications. A MATLAB function was used to approximate an ideal square-root Nyquist lter. By proper selection of the weights in the passband and the stopband, a linear-phase lter was designed with 61 taps which satises the frequency domain constraints while introducing negligible ISI. The multiplier-less implementation of the FIR lters is achieved by using the CSD representation of the taps [26], which allows multiplications to be replaced by hardwired shifts and additions. After the CSD representations have been found, the next step is to nd the proper bit width of the system. All taps were rst converted to the CSD representation with a maximum of 0.1% error. The bit width was then decreased to nd the minimum bit width satisfying the frequency response. This minimal bit width, however, can increase the ISI. Therefore, an index was needed to compare the introduced ISI, and then increase the bit width based on that index. Ideally, each fourth tap should be zero in the impulse response of the transmitter/receiver cascaded (assuming an up-sample factor of 4). Therefore, the quantity X ISI = jh(4k)j (4.2) can be considered as an index for the ISI. The bit width was then incremented until the dierence in the ISI of the original oating-point lter and the quantized lter

59 46 x(n) MHz MHz H(z) y(n) x(n) MHz H0(z) H1(z) H2(z) H3(z) MHz y(n) Figure 4.2: Poly-phase decomposition for interpolation. became negligible. The average number of CSD digits per tap was found to be 2 (maximum 4), with a maximum number of shifts equal to 12. The results of this simple quantization scheme are consistent with the local search algorithm of [16], which optimizes the CSD taps to minimize ISI and the lter stopband attenuation at the lter design level. 4.2 Multi-rate Design The all-digital structure of the transceiver requires the shaping lters to operate at a frequency at least twice the symbol rate. Lower operation rates are attractive in terms of the critical path and power consumption, while higher sampling rates make the design of the D/A image suppression lters easier. A good compromise can be achieved by using a sampling rate equal to four times the symbol rate. The lters need not to operate at this sampling frequency, however. By using the poly-phase decomposition [18], each lter can be replaced by four sub-lters, each operating at the symbol rate (see Figures 4.2 and 4.3). The relationship between the sub-lters and the original lter is given by: h 0 = h(4k) h 1 = h(4k + 1) h 2 = h(4k + 2) h 3 = h(4k + 3) (4.3)

60 MHz x(n) MHz H(z) MHz y(n) MHz x(n) H0(z) H3(z) H2(z) H1(z) y(n) Figure 4.3: Poly-phase decomposition for decimation. 4.3 Modulator Implementation The rst step toward an ecient implementation of the modulator is to merge the I and Q sub-lters. This approach is shown in Figure 4.4 which has the advantage of the output adders being clocked at low frequency. FIR shaping lters can be implemented as direct or transposed direct forms [17]. Transposed direct forms have a very short critical path which makes them suitable for high-speed applications. However, this structure has two main disadvantages. First, the input should feed all the taps, which results in a big capacitive load on the driving circuit. Second, the registers should provide guard bits to accommodate the outputs of the arithmetic units, which is not necessary in the direct form where each register keeps a 4-bit symbol. The direct form structure has no such problems, but its main disadvantage is the long adder chain. In the modulator, this long critical path introduces no problem, mainly because the inputs to the adders are the 4-bit I channel I0(z) I channel I0(z) Q channel I1(z) I2(z) I3(z) Q0(z) Q1(z) Q2(z) + - y(n) Q channel I1(z) I2(z) I3(z) Q0(z) Q1(z) Q2(z) y(n) Q3(z) Q3(z) Figure 4.4: Merging the I and Q sub-lters.

61 symbols. The reason the input to the adders are four bits is due to the grouping method which will be presented in more detail later. 48 The direct form of the modulator sub-lters can be further optimized by tappeddelay line sharing. As can be seen from Figure 4.4, only one register chain can be used for each channel since the inputs to all sub-lters of the same channel are the same. This structure signicantly reduces the load on the clock signal and thus avoiding the clock skew problems. Multiplierless lters can be eciently implemented by grouping the CSD digits with the same number of shifts. In other words, all taps with the same shift will be added rst, and then will be shifted. For instance, assuming there are two arbitrary taps. The rst tap with the CSD representation 2?5? 2?7. The second with the CSD representation 2?7? 2?9. Figure 4.5 shows how a conventional FIR would be built and how a FIR using this grouping method would be built. The overall picture of the grouped FIR is shown in Figure 4.6. This grouping methodology has several advantages. First, the rst-level adders have a small bit width, since they don't need to accommodate the guard bits of the shifting operation. Second, the number of inputs of the wide output adder is all possible shift values, which is less than the lter length as used in the conventional direct form structure. This reduction in the number of inputs will reduce the routing complexity. Finally, this approach makes the I-Q sub-lter merging easier, since there are so many common CSD digits in these sub-lter taps which can be grouped eciently. The nal possible optimization in the modulator is the well-known folded structure of the symmetric FIR lters [17]. It is known that the linear-phase symmetry

62 49 Non-Grouped FIR Grouped FIR In Z -1 In Z Out Out Figure 4.5: FIR non-grouped structure vs grouped structure. x(n) Tapped-Delay Line y(n) Figure 4.6: General grouped structure.

63 50 x(n) Z -1 Z -1 Z -1 Z -1 Z -1 Z -1 Z -1 Z -1 Z -1 Z -1 Z -1 Z -1 Z -1 Grouping... y(n) Figure 4.7: Grouping for symmetric lter. of an FIR lter will always be reected into its poly-phase decomposition [18]. More specically, each sub-lter is either symmetric or pairwise mirror-symmetric. Ecient implementations of such lters are discussed in [19]. It should be noted that the direct folded form of the mirror-symmetric lters introduces some additional cost for the wide registers used between the adders. Moreover, sophisticated routing between the mirror-symmetric sub-lters will increase the routing delays. Based on these observations, we decided to apply the linear-phase symmetry to the symmetric lters only, and not the mirror-symmetric lters. The grouping of the CSD taps is shown in Figure 4.7 for a symmetric sub-lter. The overall structure of the modulator including all the above techniques is shown in Figure 4.8. Each tapped delay line has two outputs. The all-taps output comes directly from all the taps, and is used in non-symmetric groups 1 and 3. The folded output is the output of the adders of Figure 4.7, and is used in the symmetric groups 0 and 2. The output registers synchronize the slow and fast parts of the circuit. The timing diagram for the modulator is shown in Figure 4.9.

64 51 I Tapped Delay Line All Taps CLK Folded Group Adders 0 D A 1 2 D D MUX D Output 3 D Q All Taps Tapped Delay Line CLK Folded Counter f = MHz = B 4f MHz B Figure 4.8: Detailed structure for the modulator. h0 h4 h8 Group 0 Output h1 h5 h9 Group 1 Output h2 h6 h10 Group 2 Output h3 h7 h11 Group 3 Output h0 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 Modulator Output Figure 4.9: Modulator timing diagram.

65 4.4 Demodulator Implementation 52 The main dierence between the demodulator and the modulator is that the direct form implementation of the sub-lters is not feasible in the demodulator. The reason is that the input to the demodulator is 14-bits wide, so the delay in the adder chain of the sub-lters is much bigger than the available delay budget. Another problem in the demodulator, as a result of using a transposed form FIR, involved the sign bit of the input word. The common input of all taps together with the sign extension required for the shifts of the CSD taps overloads the sign bit of the input. This problem has been addressed in [12] and a solution called MSB-x has been presented. This solution will replace a shift with an addition to a constant, and therefore will sacrice the area for speed. The nal layout for the demodulator is approximately three times as large as the modulator, even though both lters are of the same order. The large bit width of the input to the demodulator is one reason for this dierence in area. Lack of tapped delay line sharing and grouping/merging techniques is the other reason for this dierence in the area which also highlights the eectiveness of these algorithms. In addition, clock skew became a problem in both the modulator and demodulator design. The slow clock on the demodulator side should supply eight sub-lters of length 15/16 taps with 17-bit registers, together with some other synchronizing registers. This makes the use of clock buer tree inevitable in the demodulator. Since the input to the I and Q channels is the same, the multiplexer, intermediate registers, and the sub-lter input buers can be shared. Besides, the common input to each sub-lter pair was rst shifted (or equivalently added to a constant to avoid

66 53 h0 h4 h8 Impulse at time 0 h0 h3 h7 Impulse at time 1 h0 h2 h6 Impulse at time 2 h0 h1 h5 Impulse at time 3 h0 h1+h2+h3+h4 h5+h6+h7+h8 Demodulator output Input H(z) 4 Output Figure 4.10: Original demodulator timing diagram. MSB overloading), and then these shifted terms were shared between the two sub- lter. As in the modulator, the symmetric sub-lters 0 and 2 were implemented in the folded form for additional hardware eciency. Timing diagram for the demodulator can be explained with reference to Figure In this gure the output of the original lter, before poly-phase decomposition, is shown for the input (n)+(n?1)+(n?2)+(n?3). The equivalent poly-phase implementation should produce an identical output. A simple poly-phase implementation and its output is shown in Figure This circuit is not practical for two reasons. First, even though each sub-lter operates at the baud frequency, we need a four-phase baud rate clock since the sub-lter inputs are not aligned. The second problem is that there is only a short period of 1 4f B available where all the sub-lter outputs are valid and can be added to generate the correct sequence. This addition is impractical with a clock frequency of MHz and four 17-bit inputs. The demodulator circuit was then modied as shown in Figure The fast registers were used to align the outputs and increase the addition time and also

67 54 h0 h4 h8 y0 H0 y0 + Output h3 h2 h7 h6 h11 h10 y3 y2 Input DEMUX H3 H2 y3 y2 + + h1 h5 h9 y1 H1 y1 valid valid valid Counter 4f B f B Figure 4.11: A simple demodulator structure. eliminate the need for a four-phase clock. Slow registers are used to latch the sub- lter input to make it stable during the baud period in which sub-lters are supposed to operate. The nal modication in the demodulator was the result of the dependency between the slow and fast clocks. From Figure 4.12 it can be seen that the data at point A is stable for one fast clock period. The validity period for data at point B depends on the phase of the demultiplexer input data and also the demultiplexer delay. This will make the slow register of channel 0 very sensitive to the relative phases of the fast and slow clocks, which can easily result in setup/hold violations. h0 h4 h8 y0 B D H0 y0 + Output h3 h2 h7 h6 y3 y2 Input DEMUX D 3 D 2 A D D H3 H2 y3 y2 + + h1 h5 y1 D D H1 y1 valid valid valid Counter 4f B f B Figure 4.12: The modied demodulator structure.

68 55 Fast Slow D B D C I0 + D I Q0 D 3 D D I3 + Input DEMUX Q3 + D 2 D D I2 + Q2 + D D D I1 Counter Q1 + D Q 4f B Alignment Setup Synchronization f B Figure 4.13: The nal demodulator structure. An obvious solution is to latch data at point B, but this will aect the data alignment unless we add latches to all the other sub-lters as well. Therefore, one additional level of fast latches were added in the nal version of the demodulator shown in Figure The Overall Chip Architecture The complete chip including the modulator, demodulator, and control unit is shown in Figure The control unit selects the chip's dierent operational modes shown in Table 4.2. These modes include modulator, modulator/demodulator, and demodulator modes. The modulator modes (0-1) are used for testing the modulator alone. In these modes, the group outputs (point A in Figure 4.8) together with the modulator output are accessible and the input to the demodulator is zero. Modulator/demodulator modes (2-10) make it possible to test both modulator and demodulator of the same chip. In these modes, the modulator output is connected to the demodulator input, and the access points are modulator output, demodulator output, demodulator sub-lter outputs, and the fast and slow latch outputs of

69 56 CLK CLK4 Top-Level System I Q Reset CLK 3 3 Modulator 5x I Q CLK4 8x14 Reset MIISel Demodulator 10x17 14 Controller 14 I/O mod3 mod2 MDIO/mod1 MDC /mod0 MII MUX 4 Figure 4.14: The overall chip structure. the demodulator (points B and C in Figure 4.13). Demodulator mode (15) is used for testing two dierent chips. In this case, the IO bus acts as an input to the demodulator so the output of one chip's modulator can be connected to another chip's demodulator input. To control the dierent modes built into the modulator and demodulator chip, the MII (Media Independent Interface), which is dened the IEEE standard for Ethernet [20], was included in the chip. The modulator and demodulator chip did not need the MII for the functions dened in the Ethernet standard. What it did need was a convenient way to read and write the state of buses within the chip (in the case of this chip, to write the mode bits). Obviously, after a chip has been fabricated,

70 57 Mode I/O iout qout DemIn 0 mod mod0 mod1 0 1 mod mod2 mod3 0 2 mod I Q mod 3 mod I0 Q0 mod 4 mod I1 Q1 mod 5 mod I2 Q2 mod 6 mod I3 Q3 mod 7 mod slow0 slow1 mod 8 mod slow2 slow3 mod 9 mod fast0 fast1 mod 10 mod fast2 fast3 mod 15 external I Q external other Table 4.2: The dierent operational modes of the chip.

71 58 the internal buses of the chip cannot be easily observed like they can be through a simulator. Debugging the chip can be an arduous task since the engineer must derive the events inside the chip solely from the output signals. The MII has been dened to include a mechanism where the engineer, using a computer, can read and write to registers within a chip from a computer. Using this feature, it is possible to read and write the state of certain buses inside the chip. The cost for the MII are some extra gates for the controller portion of the MII, the registers which hold the values of the bus being observed and two I/O pins. The VHDL for the MII was synthesized into a netlist and placed as a component in logic assistant. The netlist was attened therefore integrating the MII with our modulator and demodulator. A layout was created using this attened netlist with the MII. The simulation les were modied so the structure of the inputs were that of MII frames specied in the Ethernet standard. MII is basically a serial port which uses the MDC pin for clock and the MDIO pin for reading and writing data. Besides the MII support, a simple 4-bit parallel control signal was also provided for the chip. The control mode is user-selectable via the MIISel signal. 4.6 Simulation Results and Final Layout The nal layout was simulated under the conditions showed in Table 4.3, and it's functionality was veried for 5000 random symbols and the output SNR found to be 36dB. The signal constellation of the demodulator output is shown in Figure 4.15.

72 59 Process VDD (V) Temperature ( C) Best Typical Worst Table 4.3: Operating conditions under which the circuit was simulated. 8 Demodulator Output Figure 4.15: Demodulator output.

73 60 Figure 4.16: Chip layout The Design Rule Checker (DRC) was then run on the chip to nd the possible violations. There were some spacing and mis-alignment errors which were xed manually. Figure 4.16 and the chip dimensions in Table 4.4.