Switching Regulator IC for Buck Converter. w/ 40V/1A or 40V/600mA MOSFET. NJW4152R-B (MSOP8 (VSP8)) Wide Operating Voltage Range 4.

Transcription

1 NJW45 Switching Regulator IC for Buck Converter w/ 4/A or 4/6mA MOSFET GENERAL DESCRIPTION The NJW45 is a buck converter with 4/A or 4/6mA MOSFET. It corresponds to high oscillating frequency, and Low ESR Output Capacitor (MLCC) within wide input range from 4.6 to 4. Therefore, the NJW45 can realize downsizing of an application with a few external parts. Also, it has a soft start function, an over current protection and a thermal shutdown circuit. Moreover there is an automotive for extended operating temperature range version. It is suitable for logic voltage generation from high voltage that Car Accessory, Office Automation Equipment, Industrial Instrument and so on. PACKAGE OUTLE NJW45GM-A (HSOP8) FEATURES Maximum Rating Input oltage 45 NJW45R-B (MSOP8 (SP8)) Wide Operating oltage Range 4.6 to 4 Switching version PWM Control Wide Oscillating Frequency 3kHz to MHz Soft Start Function 4ms typ. ULO (Under oltage Lockout) Over Current Protection / Thermal Shutdown Protection Standby Function Package Outline NJW45GM: HSOP8 NJW45R: MSOP8(SP8)* *MEET JEDEC MO-87-DA AEC-Q (HSOP8 package) This product meets the reliability level required by AEC-Q. PRODUCT CLASSIFICATION Part Number ersion Output Current Switching Current Limit (M.) Operating oltage Package NJW45GM-A A.A.4A 4.6 to 4 HSOP8 NJW45GM-A-T A.A.4A 4.6 to 4 HSOP8 NJW45GM-A-T A.A.4A 4.6 to 4 HSOP8 NJW45GM-AB AB.A.4A 3.6 to 4 HSOP8 NJW45GM-AB-T AB.A.4A 3.6 to 4 HSOP8 NJW45R-B B 6mA.8A 4.6 to 4 NJW45R-BA-Z BA 6mA.8A 4.4 to 4 This data sheet is applied to "NJW45GM-A, NJW45R-B". Please refer to each data sheet for other versions. MSOP8 (SP8) MSOP8 (SP8) Operating Temperature Range General Spec. -4 to +85 C Automotive T Spec. -4 to +5 C Automotive T Spec. -4 to +5 C General Spec. -4 to +85 C Automotive T Spec. -4 to +5 C General Spec. -4 to +85 C Automotive Z Spec. -4 to +5 C er

2 NJW45 P CONFIGURATION 3 4 Exposed PAD on backside connect to GND P FUNCTION. P ON/OFF 4. RT FB 7. GND 8. SW NJW45GM-A NJW45R-B BLOCK DIAGRAM + P + ON/OFF High: ON Low : OFF (Standby) 48k Regulator Standby ON/OFF ULO Low Frequency Control OCP Pulse by Pulse FB - ER AMP OSC PWM Buffer SW ref Soft Start TSD.8 RT GND - - er.5--

3 NJW45 ABSOLUTE MAXIMUM RATGS (Ta=5 C) PARAMETER SYMBOL MAXIMUM RATGS UNIT Supply oltage ( + pin, P + pin) P + - SW pin oltage P-SW pin oltage to +6 ON/OFF pin oltage ON/OFF +45 HSOP8 79 (*),5 (*) Power Dissipation P D mw MSOP8(SP8) 595 (*3) 85 (*4) Junction Temperature Range Tj -4 to +5 C Operating Temperature Range T opr -4 to +85 C Storage Temperature Range T stg -4 to +5 C (*): Mounted on glass epoxy board. ( mm:based on EIA/JDEC standard, Layers) (*): Mounted on glass epoxy board. ( mm:based on EIA/JDEC standard, 4Layers) (For 4Layers: Applying mm inner Cu area and a thermal via hole to a board based on JEDEC standard JESD5-5) (*3): Mounted on glass epoxy board. ( mm:based on EIA/JDEC standard, Layers) (*4): Mounted on glass epoxy board. ( mm:based on EIA/JDEC standard, 4Layers), internal Cu area: mm RECOMMENDED OPERATG CONDITIONS PARAMETER SYMBOL M. TYP. MAX. UNIT Supply oltage Output Current (*5) A version. A I B version OUT.6 A Timing Resistor R T k Oscillating Frequency fosc 3 7, khz (*5): At Static Status er

4 NJW45 ELECTRICAL CHARACTERISTICS (Unless otherwise noted, + = ON/OFF =, R T =7k, Ta=5 C) PARAMETER SYMBOL TEST CONDITION M. TYP. MAX. UNIT Under oltage Lockout Block ON Threshold oltage T_ON + = L H OFF Threshold oltage T_OFF + = H L Hysteresis oltage HYS 6 m Soft Start Block Soft Start Time T SS B = ms Oscillator Block Oscillation Frequency f OSC khz Oscillation Frequency (Low Frequency Control) f OSC_LOW - =.4, FB =.55 7 khz RT pin oltage RT Oscillation Frequency deviation (Supply voltage) f D + =4.6 to 4 % Oscillation Frequency deviation (Temperature) f DT Ta=-4 C to +85 C % Error Amplifier Block Reference oltage B -.%.8 +.% Input Bias Current I B A Open Loop Gain A 8 db Gain Bandwidth G B.6 MHz Output Source Current I OM+ FB =, - = A Output Sink Current I OM- FB =, - =.9 4 ma PWM Comparate Block Maximum Duty Cycle M AX D UTY - =.7 % Output Block Output ON Resistance R ON A version, I SW =A.3.5 B version, I SW =.6A.8.48 Switching Current Limit I LIM A version.4.7. A B version.8..3 A Switching Leak Current I LEAK ON/OFF =, + =45, SW = A ON/OFF Block ON Control oltage ON ON/OFF = L H.6 + OFF Control oltage OFF ON/OFF = H L.5 Pull-down Resistance R PD 48 k General Characteristics Quiescent Current I DD R L =no load, - =.7, FB = ma Standby Current I DD_STB ON/OFF = A er.5--

5 NJW45 TYPICAL APPLICATIONS C C ON/OFF High: ON Low: OFF (Standby) R T 4 3 RT ON/OFF + P + NJW45 - FB GND SW L C OUT OUT SBD C FB R R NF C NF R FB R er

6 NJW45 CHARACTERISTICS Oscillation Frequency f OSC (khz) Timing Resistor vs.oscillation Frequency ( + =, Ta=5 o C) Timing Resistor R (k ) T Oscillation Frequency f OSC (khz) Oscillation Frequency vs. Supply oltage (R 7 T =7k, Ta=5 o C) Supply oltage + () Reference oltage B () Reference oltage vs. Supply oltage (Ta=5 o C) Supply oltage + () 4 Quiescent Current vs. Supply oltage (R =no load, L - =.5, Ta=5 o C) 6 Error Amplifier Block oltage Gain, Phase vs. Frequency ( + =, Gain=4dB, Ta=5 o C) 8 Quiescent Current I DD (ma) 3 oltage Gain Av (db) Gain Phase Phase (deg) 3 4 Supply oltage + (). Frequency f (khz) er.5--

7 NJW45 CHARACTERISTICS Oscillator Frequency f OSC (khz) Oscillator Frequency vs. Temperature ( + =, R T =7k ) Ambient Temperature Ta ( o C) Reference oltage B () Reference oltage vs. Temperature ( + =) Ambient Temperature Ta ( o C) Limited switching Current I LIM (A) Limited Switching Current vs. Temperature (A ver.) =4.5 + = + = Ambient Temperature Ta ( o C) Limited switching Current I LIM (A) Limited Switching Current vs. Temperature (B ver.) =4.5 + = + = Ambient Temperature Ta ( o C) Output ON Resistance R ON ( ) Output ON Resistance vs.temperature (A ver., I SW =A) + =4.5 + =, Ambient Temperature Ta ( o C) Output ON Resistance R ON ( ) Output ON Resistance vs.temperature (B ver., I SW =.6A) + =4.5 + =, Ambient Temperature Ta ( o C) er

8 NJW45 CHARACTERISTICS 4.6 Under oltage Lockout oltage vs. Temperature 8 Soft Start Time vs. Temperature ( + =, B =.75) Threshold oltage () T_ON T_OFF Soft Start Time Tss (ms) Ambient Temperature Ta ( o C) Ambient Temperature Ta ( o C) Quiescent Current I DD (ma) Quiescent Current vs. Temperature (R T =7k, R L =no load, - =.5) + =4 + =4.5 + = Ambient Temperature Ta ( o C) Standby Current I DD_STB ( A) Standby Current vs. Temperature ( ON/OFF =) + = + =4.5 + = Ambient Temperature Ta ( o C) Switching Leak Current I LEAK ( A) Switching Leak Current vs. Temperature ( + =45, ON/OFF =, SW =) Ambient Temperature Ta ( o C) er.5--

9 NJW45 Application NJW45 Manual P DESCRIPTIONS P NUMBER P NAME FUNCTION P + Power Supply pin for Power Line + Power Supply pin for IC Control 3 ON/OFF ON/OFF Control pin The ON/OFF pin internally pulls down with 48k. Normal Operation at the time of High Level. Standby Mode at the time of Low Level or OPEN. 4 RT Oscillating Frequency Setting pin by Timing Resistor. Oscillating Frequency should set between 3kHz and MHz. 5 - Output oltage Detecting pin Connects output voltage through the resistor divider tap to this pin in order to voltage of the - pin become.8. 6 FB Feedback Setting pin The feedback resistor and capacitor are connected between the FB pin and the - pin. 7 GND GND pin 8 SW Switch Output pin of Power MOSFET Exposed PAD Connect to GND (only HSOP8 PKG) Description of Block Features. Basic Functions / Features Error Amplifier Section (ER AMP).8±% precise reference voltage is connected to the non-inverted input of this section. To set the output voltage, connects converter's output to inverted input of this section (- pin). If requires output voltage over.8, inserts resistor divider. This AMP section has high gain and external feedback pin (FB pin). It is easy to insert a feedback resistor and a capacitor between the FB pin and the - pin, making possible to set optimum loop compensation for each type of application. Oscillation Circuit Section (OSC) Oscillation frequency can be set by inserting resistor between the RT pin and GND. Referring to the sample characteristics in "Timing Resistor and Oscillation Frequency", set oscillation between 3kHz and MHz. er

10 NJW45 Application Manual Description of Block Features (Continued) PWM Comparator Section (PWM) This section controls the switching duty ratio. PWM comparator receives the signal of the error amplifier and the triangular wave, and controls the duty ratio between % and %. The timing chart is shown in Fig.. FB pin oltage OSC Waveform (IC internal) Maximum duty: % SW pin ON OFF Fig.. Timing Chart PWM Comparator and SW pin Power MOSFET (SW Output Section) The power is stored in the inductor by the switch operation of built-in power MOSFET. The output current is limited to.4a(min.)@a version and.8a(min.)@b version by the overcurrent protection function. In case of step-down converter, the forward direction bias voltage is generated with inductance current that flows into the external regenerative diode when MOSFET is turned off. The SW pin allows voltage between the P + pin and the SW pin up to +45. However, you should use an Schottky diode that has low saturation voltage. Power Supply, GND pin ( +, P + and GND) In line with switching element drive, current flows into the IC according to frequency. If the power supply impedance provided to the power supply circuit is high, it will not be possible to take advantage of IC performance due to input voltage fluctuation. Therefore insert a bypass capacitor close to the + pin the GND pin connection in order to lower high frequency impedance. - - er.5--

11 NJW45 Application NJW45 Manual. Additional and Protection Functions / Features Under oltage Lockout (ULO) The ULO circuit operating is released above + =4.5(typ.) and IC operation starts. When power supply voltage is low, IC does not operate because the ULO circuit operates. There is m width hysteresis voltage at rise and decay of power supply voltage. Hysteresis prevents the malfunction at the time of ULO operating and releasing. Soft Start Function (Soft Start) The output voltage of the converter gradually rises to a set value by the soft start function. The soft start time is 4ms (typ). It is defined with the time of the error amplifier reference voltage becoming from to.75. The soft start circuit operates after the release ULO and/or recovery from thermal shutdown. The operating frequency is controlled with a low frequency, approximately 4% of the set value by the timing resistor, until voltage of the - pin becomes approximately.4..8 ref, - pin oltage FB pin oltage OSC Waveform SW pin ON OFF ULO(4.5 typ.) Release, Standby, Recover from Thermal Shutdow n Low Frequency Control - =approx.4 Soft Start time: Tss=4ms(typ.) to B =.75 Soft Start effective period to B =.8 Steady Operaton Fig.. Startup Timing Chart er

12 NJW45 Application Manual Description of Block Features (Continued) Over Current Protection Circuit (OCP) At when the switching current becomes I LIM or more, the overcurrent protection circuit is stopped the MOSFET output. The switching output holds low level down to next pulse output at OCP operating. The NJW45 output returns automatically along with release from the over current condition because the OCP is pulse-by-pulse type. Fig.3. shows the timing chart of the over current protection detection. If voltage of the - pin becomes less than.4, the oscillation frequency decreases to approximately 4% and the energy consumption is suppressed. FB pin oltage OSC Waveform SW pin ON OFF Sw itching Current I LIM Static Status Detect Overcurrent Static Status Fig. 3. Timing Chart at Over Current Detection Thermal Shutdown Function (TSD) When Junction temperature of the NJW45 exceeds the 75 C*, internal thermal shutdown circuit function stops SW function. When junction temperature decreases to 45 C* or less, SW operation returns with soft start operation. The purpose of this function is to prevent malfunctioning of IC at the high junction temperature. Therefore it is not something that urges positive use. You should make sure to operate within the junction temperature range rated (5 C). (* Design value) ON/OFF Function (Standby Control) The NJW45 stops the operating and becomes standby status when the ON/OFF pin becomes less than.5. The ON/OFF pin internally pulls down with 48k, therefore the NJW45 becomes standby mode when the ON/OFF pin is OPEN. You should connect this pin to + when you do not use ON/OFF function. - - er.5--

13 NJW45 Application NJW45 Manual Application Information Inductors Large currents flow into inductor, therefore you must Current Peak Current Ipk provide current capacity that does not saturate. Inductor () Continuous Reducing L, the size of the inductor can be smaller. Current I L Conduction Mode However, peak current increases and adversely affecting efficiency. () Critical Mode On the other hand, increasing L, peak current can (3) Continuous Conduction Mode be reduced at switching time. Therefore conversion Frequency t ON t OFF efficiency improves, and output ripple voltage reduces. f OSC Above a certain level, increasing inductance windings increases loss (copper loss) due to the resistor Fig. 4. Inductor Current State Transition element. Ideally, the value of L is set so that inductance current is in continuous conduction mode. However, as the load current decreases, the current waveform changes from () CCM: Continuous Conduction Mode () Critical Mode (3) DCM: Discontinuous Conduction Mode (Fig. 4.). In discontinuous mode, peak current increases with respect to output current, and conversion efficiency tend to decrease. Depending on the situation, increase L to widen the load current area to maintain continuous mode. If the application needs maximum output current, the inductor ripple current should be set less than % to prevent operating the over current protection circuit at the minimum switching limiting current. Catch Diode When the switch element is in OFF cycle, power stored in the inductor flows via the catch diode to the output capacitor. Therefore during each cycle current flows to the diode in response to load current. Because diode's forward saturation voltage and current accumulation cause power loss, a Schottky Barrier Diode (SBD), which has a low forward saturation voltage, is ideal. An SBD also has a short reverse recovery time. If the reverse recovery time is long, through current flows when the switching transistor transitions from OFF cycle to ON cycle. This current may lower efficiency and affect such factors as noise generation. Input Capacitor Transient current flows into the input section of a switching regulator responsive to frequency. If the power supply impedance provided to the power supply circuit is large, it will not be possible to take advantage of the NJW45 performance due to input voltage fluctuation. Therefore insert an input capacitor as close to the MOSFET as possible. Output Capacitor An output capacitor stores power from the inductor, and stabilizes voltage provided to the output. When selecting an output capacitor, you must consider Equivalent Series Resistance (ESR) characteristics, ripple current, and breakdown voltage. Also, the ambient temperature affects capacitors, decreasing capacitance and increasing ESR (at low temperature), and decreasing lifetime (at high temperature). Concerning capacitor rating, it is advisable to allow sufficient margin. Output capacitor ESR characteristics have a major influence on output ripple noise. A capacitor with low ESR can further reduce ripple voltage. Be sure to note the following points; when ceramic capacitor is used, the capacitance value decreases with DC voltage applied to the capacitor. er

14 NJW45 Application Manual Application Information (Continued) Board Layout In the switching regulator application, because the current flow corresponds to the oscillation frequency, the substrate (PCB) layout becomes an important. You should attempt the transition voltage decrease by making a current loop area minimize as much as possible. Therefore, you should make a current flowing line thick and short as much as possible. Fig.5. shows a current loop at step-down converter. Especially, should lay out high priority the loop of C -SW-SBD that occurs rapid current change in the switching. It is effective in reducing noise spikes caused by parasitic inductance. NJW45 Built-in SW L NJW45 Built-in SW L C SBD C OUT C SBD C OUT (a) Buck Converter SW ON (b) Buck Converter SW OFF Fig. 5. Current Loop at Buck Converter Concerning the GND line, it is preferred to separate the power system and the signal system, and use single ground point. The voltage sensing feedback line should be as far away as possible from the inductance. Because this line has high impedance, it is laid out to avoid the influence noise caused by flux leaked from the inductance. Fig. 6. shows example of wiring at buck converter. Fig. 7 shows the PCB layout example. P + SW L OUT C + SBD C OUT R L (Bypass Capacitor) NJW45 R FB C FB RT - R T GND R R To avoid the influence of the voltage drop, the output voltage should be detected near the load. Separate Digital(Signal) GND from Pow er GND Because - pin is high impedance, the voltage detection resistance: R/R is put as much as possible near IC(-). Fig. 6. Board Layout at Buck Converter er.5--

15 Application Information (Continued) NJW45 Application NJW45 Manual GND GND OUT Power GND Area C SBD C OUT L OUT ON/OFF C To Signal GND R FB C FB R T R NF Signal GND Area R R C NF Feed back signal Connect Signal GND line and Power GND line on backside pattern Fig. 7 Layout Example (upper view) er

16 NJW45 Application Manual Calculation of Package Power A lot of the power consumption of buck converter occurs from the internal switching element (Power MOSFET). Power consumption of NJW45 is roughly estimated as follows. Input Power: P = I [W] Output Power: P OUT = OUT I OUT [W] Diode Loss: P DIODE = F I L(avg) OFF duty [W] NJW45 Power Consumption: P LOSS = P P OUT P DIODE [W] Where: : Input oltage for Converter I : Input Current for Converter OUT : Output oltage of Converter I OUT : Output Current of Converter F : Diode's Forward Saturation oltage I L(avg) : Inductor Average Current OFF duty : Switch OFF Duty Efficiency ( ) is calculated as follows. = (P OUT P ) [%] You should consider temperature derating to the calculated power consumption: P D. You should design power consumption in rated range referring to the power dissipation vs. ambient temperature characteristics (Fig. 8). Power Dissipation P D (mw) NJW45GM-A (HSOP8 Package) Power Dissipation vs. Ambient Temperature (Tj=~5 C) At on 4 layer PC Board (*7) At on layer PC Board (*6) General Spec Extended T spec Extended T spec Power Dissipation P D (mw) NJW45R-B (SP8 Package) Power Dissipation vs. Ambient Temperature (Tj=~5 C) At on 4 layer PC Board (*9) At on layer PC Board (*8) Ambient Temperature Ta ( C) Ambient Temperature Ta ( C) (*6): Mounted on glass epoxy board. ( mm:based on EIA/JDEC standard, Layers) (*7): Mounted on glass epoxy board. ( mm:based on EIA/JDEC standard, 4Layers) (For 4Layers: Applying mm inner Cu area and a thermal via hole to a board based on JEDEC standard JESD5-5) (*8): Mounted on glass epoxy board. ( mm:based on EIA/JDEC standard, Layers) (*9): Mounted on glass epoxy board. ( mm:based on EIA/JDEC standard, 4Layers), internal Cu area: mm Fig. 8. Power Dissipation vs. Ambient Temperature Characteristics er.5--

17 Application Design Examples Step-Down Application Circuit IC : NJW45GM Input oltage : = Output oltage : OUT =5 Output Current : I OUT =A Oscillation frequency : fosc=7khz Output Ripple oltage : ripple(p-p) =less than m NJW45 Application NJW45 Manual ONOFF High: ON Low: OFF (Standby) R T C. F/ k RT ON/OFF + P + NJW45GM C F/5 = C open R NF 3.3k - 5 FB 6 C NF 4,7pF GND 7 SW 8 L H/.5A SBD C OUT 4.7 F/6.3 C FB pf R FB R 7k OUT =5 R 5.k Reference Qty. Part Number Description Manufacturer IC NJW45GM Internal A MOSFET SW.REG. IC New JRC L CDRH8D8HPNP-N Inductor H,.5A(Ta= C) /.9A (Ta= C) Sumida D CMS Schottky Diode 4, A Toshiba C UMK35BJ6MM Ceramic Capacitor 35 F, 5, X5R Taiyo Yuden C. F Ceramic Capacitor 68. F, 5, B Std. C OUT JMKABJ475KG Ceramic Capacitor 4.7 F, 6.3, X5R Taiyo Yuden C NF 4,7pF Ceramic Capacitor 68 4,7pF, 5, B Std. C FB pf Ceramic Capacitor 68 pf, 5, CH Std. C (Optional) Optional R 5.k Resistor 68 5.k, %,.W Std. R, R T 7k Resistor 68 7k, %,.W Std. R NF 3.3k Resistor k, 5%,.W Std. R FB (Short) Resistor 68,.W Std. er

18 NJW45 Application Manual Application Design Examples (Continued) Setting Oscillation Frequency From the Oscillation frequency vs. Timing Resistor Characteristic, R T =7 [k ], t=.43[ s] at fosc=7khz. Inductance Current: I L Peak Current: Ipk Step-down converter duty ratio is shown with the following equation. Output Current: I OUT Duty OUT F 5.4 Therefore, t ON =.64 [ s], t OFF =.79 [ s] 45 % Period: t Frequency: f OSC =/t t ON t OFF Fig. 9. Inductor Current Waveform Selecting Inductance To assume maximum output current: A, and the inductor ripple current should be set not to exceed the minimum switching limiting current: I LIM =.4A (min.). IL is Inductance ripple current. When to IL= output current %: I L =. I OUT =. =. [A] This obtains inductance L. DS_RON is drop voltage by MOSFET on resistance. L DS RON I L OUT t ON [ H ] [ H] Inductance L is a theoretical value. The optimum value varies according such factors as application specifications and components. Fine-tuning should be done on the actual device. This obtains the peak current Ipk at switching time. Ipk I OUT I L..[ A] The current that flows into the inductance provides sufficient margin for peak current at switching time. In the application circuit, use L= H,.5A(Ta= C) /.9A (Ta= C) er.5--

19 NJW45 Application NJW45 Manual Application Design Examples (Continued) Selecting the Input Capacitor The input capacitor corresponds to the input of the power supply. It is required to adequately reduce the impedance of the power supply. The input capacitor selection should be determined by the input ripple current and the maximum input voltage of the capacitor rather than its capacitance value. I The effective input current can be expressed by the following formula. RMS I OUT OUT OUT [A] In the above formula, the maximum current is obtained when = OUT, and the result in this case is I RMS = I OUT (MAX). When selecting the input capacitor, carry out an evaluation based on the application, and use a capacitor that has adequate margin. Selecting the Output Capacitor The output capacitor is an important component that determines output ripple noise. Equivalent Series Resistance (ESR), ripple current, and capacitor breakdown voltage are important in determining the output capacitor. The output ripple noise can be expressed by the following formula. ESR ripple( p p) I L When selecting output capacitance, select a capacitor that allows for sufficient ripple current. The effective ripple current that flows in a capacitor (I rms ) is obtained by the following equation. I rms I L [ marms] Consider sufficient margin, and use a capacitor that fulfills the above spec. In the application circuit, use C OUT =4.7 F/6.3. Setting Output oltage The output voltage OUT is determined by the relative resistances of R, R. The current that flows in R, R must be a value that can ignore the bias current that flows in ER AMP. OUT R R B 7k 5.k [ ] er

20 NJW45 Application Manual Compensation design example A switching regulator requires a feedback circuit for acquiring a stable output. Because the frequency characteristics of the application change according to the inductance, output capacitor, and so on, the compensation constant should ideally be determined in such a way that the maximum band is acquired while the necessary phase for stable operation is maintained. These compensation constants play an important role in the adjustment of the NJW45 when mounted in an actual unit. Finally, select the constants while performing measurement, in consideration of the application specifications. Feedback and Stability Basically, the feedback loop should be designed in such a way that the open loop phase shift at the point where the loop gain is db is less than -8. It is also important that the loop characteristics have margin in consideration of ringing and immunity to oscillation during load fluctuations. With the NJW45, the feedback circuit can be freely designed, enabling the arrangement of the poles and zeros which is important for loop compensation, to be optimized. The characteristics of the poles and zeros are shown in Fig.. Poles: The gain has a slope of - db/dec, and the phase shifts -9. Zeros: The gain has a slope of + db/dec, and the phase shift +9. If the number of factors constituting poles is defined as n, the change in the gain and phase will be n -fold. This also applies to zeros as well. The poles and zeros are in a reciprocal relationship, so if there is one factor for each pole and zero, they will cancel each other. Configuration of the compensation circuit Gain Phase Gain Phase f P / f Z / Pole f P f P Frequency Pole +db/dec Zero Fig.. Characteristics of Pole and Zero f Z Frequency Zero -db/dec f Z P + Buffer SW L LC Gain OUT RESR C OUT CFB R ER AMP ref =.8 CFB RFB PWM FB - R CNF RNF C(option) Fig.. Compensation Circuit Configuration - - er.5--

21 NJW45 Application NJW45 Manual Compensation Design (Continued) Poles and zeros due to the inductance and output capacitor Double poles f P(LC) are generated by the inductance and output capacitor. Simultaneously, single zeros f Z(ESR) are generated by the output capacitor and ESR. Each pole and zero is expressed by the following formula. f Z(ESR) C R OUT ESR f P(LC) If the ESR of the output capacitor is high, f Z(ESR) will be located in the vicinity of f P(LC). In an application such as this, the zero f Z(ESR) compensates the double poles f P(LC), resulting in a tendency for stability to be readily maintained. However, if the ESR of the output capacitor is low, f Z(ESR) shifts to the high region, and the phase is shifted -8 by f P(LC).The NJW45 compensation circuit enables compensation to be realized by using zeros f Z and f Z. LC OUT Poles and zeros due to error amplifier The single poles and zeros generated by the error amplifier are obtained using the following formula. Zero Pole fp f Z RR CNFRNF CNFA R R (Av: Amplifier Open Loop Gain=8dB) f Z C R FB f P f C P3 FB R FB CR (Option) RR R R NF LC Gain Loop Gain Compensation Gain Gain (db) Double pole -4dB/dec db frequency -db/dec * Gain increase due to Zero f Z and f Z are located on both sides of f P(LC). Because the inductance and output capacitor vary, they are each set using the following as a rough guide. f P(LC).5-fold.9-fold f P(LC).-fold.-fold f P f Z or f Z f P(LC) f P f P3 f Z(ESR) Fig. Loop Gain examples There is also a method in which f Z and f Z are located at positions lower than even f P(LC). Because there is a tendency for the phase shift to increase and the gain to rise, it can be expected that the response will improve. However, there is a tendency for the phase margin to become insufficient, so care is necessary. f P creates poles in the low frequency region due to the Miller effect of the error amplifier. The stability becomes better as f P becomes lower. On the other hand, the frequency characteristics do not improve, so the response is adversely affected. f P is set using a frequency gain of db for f P(LC) as a rough guide. If the open loop gain of the error amplifier is made 8 db, design is carried out using f P < f P(LC) 3 (= 6 db) as a rough guide. Above several khz, various poles are generated, so the upper limit of the frequency range where the loop gain is db is set to fifth (/5) to tenth (/) of oscillation frequency. The f Z(ESR) in the high frequency region sometimes causes a loop gain to be generated (See Fig. Loop Gain ). Using f P and f P3, perform adjustment with the NJW45 mounted in an actual unit, so as to adequately reduce the loop gain in the high frequency region. er

22 NJW45 Application Manual Application Characteristics :NJW45GM-A At OUT =5. setting (R=5.k, R=7k, C FB =pf, R FB = ) Efficiency (%) f=7khz L= H Efficiency vs. Output Current ( OUT =5., Ta=5 o C) =6 = =8 =4 Output Current I OUT (ma) Output oltage OUT () Output oltage vs. Output Current f=7khz L= H (Ta=5 o C) =6,, 8, Output Current I OUT (ma) At OUT =3.3 setting (R=5.k, R=6k, C FB =pf, R FB = ) Efficiency (%) f=7khz L= H Efficiency vs. Output Current ( OUT =3.3, Ta=5 o C) =5 = =8 =4 Output Current I OUT (ma) Output oltage OUT () Output oltage vs. Output Current f=7khz L= H (Ta=5 o C) =5,, 8, Output Current I OUT (ma) At OUT =.5 setting (R=3k, R=7k, C FB =pf, R FB =k ) Efficiency (%) f=7khz L= H Efficiency vs. Output Current ( OUT =.5, Ta=5 o C) =5 = =8 =4 Output Current I OUT (ma) Output oltage OUT () Output oltage vs. Output Current f=7khz L= H (Ta=5 o C) =5,, 8, 4.44 Output Current I OUT (ma) - - er.5--

23 NJW45 MEMO [CAUTION] The specifications on this databook are only given for information, without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. er