NJW4160. Switching Regulator IC for Buck Converter

Transcription

1 NJW46 Switching Regulator IC for Buck Converter External MOSFET driving GENERAL DESCRIPTION The NJW46 is a MOSFET Drive switching regulator IC for Buck Converter that operates wide input range from 3. to 35. It can provide large current application because of built-in highly effective Pch MOSFET drive circuit. Built-in pulse-by-pulse current detecting type over current protection limits the output current at over load. It is suitable for logic voltage generation from high voltage that Car Accessory, Office Automation Equipment, Industrial Instrument and so on. PACKAGE LINE NJW46R (MSOP8(SP8)) NJW46M (DMP8) FEATURES Pch MOSFET Driving Wide Operating oltage Range PWM Control Wide Oscillating Frequency Over Current Protection ULO (Under oltage Lockout) Standby Function Package Outline Driving oltage (typ.) 3 to 35 5kHz to MHz NJW46M: DMP8 NJW46R: MSOP8(SP8) *MEETJEDEC MO-87-DA PIN CONFIGURATION NJW46R NJW46M PIN FUNCTION.. SI EN 5. IN- 6. FB 7. CT 8. GND er

2 NJW46 BLOCK DIAGRAM + SI EN Enable Control ON/OFF IPK Low Frequency Control OSC Pulse by Pulse 5 Reg. Driver ref.8 Error AMP PWM Comparator IN- FB CT GND ABSOLUTE MAXIMUM RATINGS (Ta=5 C) PARAMETER SYMBOL MAXIMUM RATINGS UNIT Supply oltage + +4 pin oltage + -6 to + EN pin sink Current I EN 5 A IN- pin oltage IN- +6 CT pin oltage CT +6 (*) Power Dissipation P D MSOP8(SP8) : 595 (*) DMP8: 53 (*) mw Operating Temperature Range T opr -4 to +85 C Storage Temperature Range T stg -4 to +5 C (*): When Supply voltage is less than +6, the absolute maximum voltage is equal to the Supply voltage. (*): Mounted on glass epoxy board based on EIA/JEDEC. ( mm: -Layers) RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL MIN. TYP. MAX. UNIT Supply oltage Timing Capacitor C T 3,3 pf Oscillating Frequency f OSC 5, khz - - er.4-4-

3 NJW46 ELECTRICAL CHARACTERISTICS (Unless otherwise noted, + =, EN is connected to + via k pull-up, C T =47pF, Ta=5 C) PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT Oscillator Block Oscillation Frequency f OSC C T =47pF khz Charge Current I chg 8 A Discharge Current I dis 8 A oltage amplitude OSC.6 Frequency Supply oltage Deviation Frequency Temperature Deviation Oscillation Frequency (Low Frequency Control) f D + =3 to 35 % f DT Ta=-4 C to +85 C 5 % f OSC_LOW IN- =.3, FB =.7 khz Error Amplifier Block Reference oltage B -.%.8 +.% Input Bias Current I B A Open Loop Gain A 8 db Gain Bandwidth G B MHz Output Source Current I OM+ FB =, IN- = A Output Sink Current I OM- FB =, IN- = ma PWM Comparate Block Input Threshold oltage (FB pin) T_ Duty=%, IN- = T_5 Duty=5%, IN- = Maximum Duty Cycle M AX D UTY FB =. % Current Limit Detection Block Current Limit Detection oltage IPK m Delay Time T DELAY ns Output Block Output High Level ON Resistance R OH I O =-5mA Output Low Level ON Resistance R OL I O =+5mA 9 Output Sink Current I OL pin= ma Output pin Limiting oltage OLIM Under oltage Lockout Block ON Threshold oltage T_ON + = L H OFF Threshold oltage T_OFF + = H L er

4 NJW46 ELECTRICAL CHARACTERISTICS (Unless otherwise noted, + =, EN is connected to + via k pull-up, C T =47pF, Ta=5 C) PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT Enable Control Block ON Control oltage ON EN = L H.6 Z_EN OFF Control oltage OFF EN = H L.5 EN pin oltage at Open EN_OPEN.5.8. EN pin Zener oltage Z_EN I EN = 45 A EN pin Source Current I EN_SOURCE EN = A EN pin Sink Current I EN_SINK EN = A General Characteristics Quiescent Current I DD R L =no load, IN- =.7, FB =.7..5 ma Standby Current I DD_STB EN = A APPLICATION EXAMPLE Non-isolated Buck Converter IN R SENSE C IN R EN Pow er MOSFET C IN 4 3 EN + SI NJW46 SBD L C C FB R FB R IN- FB CT GND R R NF C NF C T er.4-4-

5 NJW46 CHARACTERISTICS Oscillation Frequency f OSC (khz) Oscillation Frequency vs. Supply oltage (C =47pF, Ta=5 o C) 3 T Supply oltage + () Reference oltage B () Reference oltage vs. Supply oltage (Ta=5 o C) Supply oltage + () Quiescent Current I DD (ma) Quiescent Current vs. Supply oltage (R =no load, =.6 L IN- FB =.7, Ta=5 o C) Supply oltage + () oltage Gain Av (db) Error Amplifier Block oltage Gain, Phase vs. Frequency ( + =, Gain=4dB, Ta=5 o C) Gain Phase Frequency f (khz) Phase (deg) EN pin Current I EN ( A) EN pin Current vs.en pin oltage ( + =, Ta=5 o C) Sink EN_OPEN Z_EN -5 Source EN pin olatage EN () er

6 NJW46 CHARACTERISTICS Oscillator Frequency f OSC (khz) Oscillator Frequency vs. Temperature ( + =, C T =47pF) Reference oltage B () Reference oltage vs. Temperature ( + =) Current Limit Detection oltage IPK (m) Current Limit Detection otage vs.temperature ( + =) pin Limited oltage OLIM () pin Limited oltage vs.temperature ( + =) Output High Level ON Resistance R ( ) OH Output High Level ON Resistance vs.temperature (I O =-5mA) =3 + =, Output Low Level ON Resistance R (W) OH Output Low Level ON Resistance vs.temperature (I 3 O =-5mA) =3 + =, er.4-4-

7 NJW46 CHARACTERISTICS Threshold oltage () Under oltage Lockout oltage vs. Temperature T_ON T_OFF ON/OFF oltage ON/OFF () Enable Control ON/OFF oltage vs.temperature ( + =) ON OFF Quiescent Current I DD (ma) Quiescent Current vs. Temperature (C T =47pF, R L =no load, IN- = FB =.7) + =35 + =3 + = Standby Current I DD_STB (ma) Standby Current vs. Temperature ( EN =) + =35 + = + = er

8 NJW46 Application Manual PIN DESCRIPTIONS PIN PIN NAME NUMBER SI 3 + Power Supply pin FUNCTION Output pin for Power MOSFET Driving The pin oltage is clamped with (typ.) at the time of Low level, in order to protect a gate of Pch MOSFET. Current Sensing pin When difference voltage between the + pin and the SI pin exceeds m(typ.), over current protection operates. 4 EN ON/OFF Control pin Normal Operation at the time of High Level. Standby Mode at the time of Low Level. 5 IN- Output oltage Detecting pin Connects output voltage through the resistor divider tap to this pin in order to voltage of the IN- pin become.8. 6 FB Feedback Setting pin The feedback resistor and capacitor are connected between the FB pin and the IN- pin. 7 CT Oscillating Frequency Setting pin by Timing Capacitor Oscillating Frequency should set between 5kHz and MHz. 8 GND GND pin er.4-4-

9 NJW46 Application NJW46 Manual Description of Block Features Error Amplifier Section (ER AMP).8±% precise reference voltage is connected to the non-inverted input of this section. To set the output voltage, connects converter's output to inverted input of this section (IN- pin). If requires output voltage over.8, inserts resistor divider. This AMP section has high gain and external feedback pin (FB pin). It is easy to insert a feedback resistor and a capacitor between the FB pin and the IN- pin, making possible to set optimum loop compensation for each type of application. Oscillation Circuit Section (OSC) Oscillation frequency can be set by inserting capacitor between the CT pin and GND. Referring to the sample characteristics in "Timing Capacitor and Oscillation Frequency", set oscillation frequency between 5kHz and MHz. The triangular wave of the oscillating circuit is generated in the IC, having amplitude between.4 and. at C T =47pF(ref.). If voltage of the IN- pin becomes less than.3, the oscillation frequency decreases to one third (33%) and the energy consumption is suppressed. Oscillation frequency f OSC (khz) Oscillation frequency vs.timing Capacitor ( + =, Ta=5 o C) Timing Capacitor C (pf) T PWM Comparator Section (PWM) This section controls the switching duty ratio. PWM comparator receives the signal of the error amplifier and the triangular wave, and controls the duty ratio between % and %. The timing chart is shown in Fig.. FB pin oltage. OSC Waveform.4 pin High Low GND Fig.. Timing Chart PWM Comparator and pin er

10 NJW46 Application Manual Description of Block Features (Continued) Driver Section (Driver) The output driver circuit is configured a totem pole type, it can efficiently drive a Pch MOSFET switching device. When the output is low level, the pin voltage is clamped with (typ.) by the internal regulator to protect gate of Pch MOSFET. (Ref. Fig.. pin) + 5 Regulator GS + To turn off Pch MOSFET High Level Output From PWM Comparator Driver GND OFF ON OFF ON To turn on Pch MOSFET Low Level Output Fig.. Driver Circuit and the pin oltage When supply voltage is decreasing, gate drive voltage output from the pin is also decreasing. Although the pin voltage is kept gate drive voltage by bypassing the internal regulator around supply voltage 5. Fig.3. shows the example of the pin voltage vs. supply voltage characteristic The optimum drive ability of MOSFET depends on the oscillation frequency and the gate capacitance of MOSFET. pin oltgae + - () pin oltage vs. Supply oltage (I O_SINK =ma, Ta=5 o C) Supply oltage + () Fig. 3. pin oltage vs. Supply oltage Characteristic - - er.4-4-

11 NJW46 Application NJW46 Manual Description of Block Features (Continued) Power Supply, GND pin ( +, GND) In line with MOSFET drive, current flows into the IC according to frequency. If the power supply impedance provided to the power supply circuit is high, it will not be possible to take advantage of IC performance due to input voltage fluctuation. Therefore insert a bypass capacitor close to the + pin the GND pin connection in order to lower high frequency impedance. Under oltage Lockout Function (ULO) The ULO circuit operating is released above + =.8(typ.) and IC operation starts. When power supply voltage is low, IC does not operate because the ULO circuit operates. There is 5m width hysteresis voltage at rise and decay of power supply voltage. Hysteresis prevents the malfunction at the time of ULO operating and releasing. Enable Function (Enable Control) With the voltage of the EN pin, the operation of NJW46 can be set as in Table. Table. EN pin voltage and NJW46 status Condition of applied State of NJW46 voltage to EN pin Example of connecting EN pin The EN pin voltage is clamped to Z_EN =5. (typ.) with the internal Zener diode. You should adjust the flow current into the Zener diode to less than 5 A..6 to Z_EN * *Internal Zener oltage + REN less than 5 A EN Enable Control + ON/OFF 5. Normal Mode When the EN pin is open, EN_OPEN =.8 (typ.) is generated with the internal current source and two diodes. + The EN pin OPEN EN Enable Control ON/OFF Generate.8 Connect to GND + Standby Mode to.5 EN Enable Control ON/OFF er

12 NJW46 Application Manual Description of Block Features (Continued) Over Current Protection Circuit At when the potential difference between the + pin and the SI pin becomes m or more, the over current protection circuit is stopped the switch output. The switching current is detected by inserted current sensing resistor (Rsc) between the + pin and the SI pin. Fig.4. shows the timing chart of the over current protection detection. The switching output holds low level until next pulse output at OCP operating. The NJW46 output returns automatically along with release from the over current condition because the OCP is pulse-by-pulse type. If voltage of the IN- pin becomes less than.3, the oscillation frequency decreases to one third (33%) and the energy consumption is suppressed. FB pin oltage OSC Waveform pin High Low GND IPK Rsc Sense Static State Detect Overcurrent Static State Fig. 4. Timing Chart at Over Current Detection The current waveform contains high frequency superimposed noises due to the parasitic elements of MOSFET, the inductor and the others. Depending on the application, inserting RC low-pass filter between current sensing resistor (R SENSE ) and the SI pin to prevent the malfunction due to such noise. The time constant of RC low-pass filter should be equivalent to the spike width (T R S C S ) as a rough guide (Fig. 5). R SENSE Spike Noise Low Pass Filter C S R S + SI T Current Waveform example To Pulse by Pulse IPK Current Limit Detection Fig. 5. Current Waveform and Filter Circuit - - er.4-4-

13 NJW46 Application NJW46 Manual Application Information Inductors Large currents flow into inductor, therefore you must provide current capacity that does not Current Peak Current Ipk Inductor () Continuous saturate. Current I L Conduction Mode Reducing L, the size of the inductor can be smaller. However, peak current increases and () Critical Mode adversely affecting efficiency. (3) Continuous On the other hand, increasing L, peak current Conduction Mode can be reduced at switching time. Therefore conversion efficiency improves, and output ripple voltage reduces. Above a certain level, increasing Frequency f OSC t ON t OFF inductance windings increases loss (copper loss) Fig. 6. Inductor Current State Transition due to the resistor element. Ideally, the value of L is set so that inductance current is in continuous conduction mode. However, as the load current decreases, the current waveform changes from () CCM: Continuous Conduction Mode () Critical Mode (3) DCM: Discontinuous Conduction Mode (Fig. 6.). In discontinuous mode, peak current increases with respect to output current, and conversion efficiency tend to decrease. Depending on the situation, increase L to widen the load current area to maintain continuous mode. Catch Diode When the switch element is in OFF cycle, power stored in the inductor flows via the catch diode to the output capacitor. Therefore during each cycle current flows to the diode in response to load current. Because diode's forward saturation voltage and current accumulation cause power loss, a Schottky Barrier Diode (SBD), which has a low forward saturation voltage, is ideal. An SBD also has a short reverse recovery time. If the reverse recovery time is long, through current flows when the switching transistor transitions from OFF cycle to ON cycle. This current may lower efficiency and affect such factors as noise generation. Switching Element You should use a switching element (Pch MOSFET) that is specified for use as a switch. And select sufficiently low R ON MOSFET at less than GS =5 because the NJW46 pin voltage is clamped (typ.). However, when the supply voltage of the NJW46 is low, the pin voltage becomes low. You should select a suitable MOSFET according to the supply voltage specification. (Ref. Driver section) Large gate capacitance is a source of decreased efficiency. That is charge and discharge from gate capacitance delays switching rise and fall time, generating switching loss. The spike noise might occur at the time of charge/discharge of gate by the parasitic inductance element. You should insert resistance between the pin and the gate and limit the current for gate protection when gate capacitance is small. However, it should be noted that the efficiency might decrease because the shape of waves may become duller when resistance is too large. The last fine-tuning should be done on the actual device and equipment. er

14 NJW46 Application Manual Application Information (Continued) Input Capacitor Transient current flows into the input section of a switching regulator responsive to frequency. If the power supply impedance provided to the power supply circuit is large, it will not be possible to take advantage of the NJW46 performance due to input voltage fluctuation. Therefore insert an input capacitor as close to the MOSFET as possible. Output Capacitor An output capacitor stores power from the inductor, and stabilizes voltage provided to the output. When selecting an output capacitor, you must consider Equivalent Series Resistance (ESR) characteristics, ripple current, and breakdown voltage. Also, the ambient temperature affects capacitors, decreasing capacitance and increasing ESR (at low temperature), and decreasing lifetime (at high temperature). Concerning capacitor rating, it is advisable to allow sufficient margin. Output capacitor ESR characteristics have a major influence on output ripple noise. A capacitor with low ESR can further reduce ripple voltage. Be sure to note the following points; when ceramic capacitor is used, the capacitance value decreases with DC voltage applied to the capacitor er.4-4-

15 NJW46 Application NJW46 Manual Application Information (Continued) Board Layout In the switching regulator application, because the current flow corresponds to the oscillation frequency, the substrate (PCB) layout becomes an important. You should attempt the transition voltage decrease by making a current loop area minimize as much as possible. Therefore, you should make a current flowing line thick and short as much as possible. Fig.7. shows a current loop at step-down converter. SW L SW L IN C IN SBD C IN C IN SBD C NJW46 NJW46 (a) Buck Converter SW ON (b) Buck Converter SW OFF Fig. 7. Current Loop at Buck Converter Concerning the GND line, it is preferred to separate the power system and the signal system, and use single ground point. The voltage sensing feedback line should be as far away as possible from the inductance. Because this line has high impedance, it is laid out to avoid the influence noise caused by flux leaked from the inductance. Fig. 8. shows example of wiring at buck converter. SW L IN C IN SBD C (Bypass Capacitor) + R FB C FB NJW46 IN- C T CT GND R R To avoid the influence of the voltage drop, the output voltage should be detected near the load. Separate Digital(Signal) GND from Pow er GND Because IN- pin is high impedance, the voltage detection resistance: R/R is put as much as possible near IC(IN-). Fig. 8. Board Layout at Buck Converter er

16 NJW46 Application Manual Calculation of Package Power You should consider derating power consumption under using high ambient temperature. Moreover, you should consider the power consumption that occurs in order to drive the switching element. Supply oltage: + Quiescent Current: I DD Oscillation Frequency: ON time: ton Gate charge amount: Qg f OSC The gate of MOSFET has the character of high impedance. The power consumption increases by quickening the switching frequency due to charge and discharge the gate capacitance. Power consumption: P D is calculated as follows. P D = ( + I DD ) + ( + Qg f OSC ) [W] You should consider temperature derating to the calculated power consumption: P D. You should design power consumption in rated range referring to the power dissipation vs. ambient temperature characteristics (Fig. 9). Power Dissipation P D (mw) MSOP8(SP8) Package Power Dissipation vs. Ambient Temperature (Tj= ~5 o C) At on 4 layer PC Board At on layer PC Board Power Dissipation P D (mw) DMP8 Package Power Dissipation vs. Ambient Temperature (Tj= ~5 o C) At on 4 layer PC Board At on layer PC Board Mounted on glass epoxy board. ( mm:EIA/JDEC standard size, Layers) Mounted on glass epoxy board. ( mm:EIA/JDEC standard size, 4Layers), internal Cu area: mm Fig. 9. Power Dissipation vs. Ambient Temperature Characteristics er.4-4-

17 Application Design Examples Step-Down Application Circuit Input oltage : IN = Output oltage : =5 Output Current : I =3A Oscillation frequency : fosc=3khz Output Ripple oltage : ripple(p-p) =less than m NJW46 Application NJW46 Manual IN = R SENSE.3 C IN F/5 C IN. F/5 R EN k 4 3 Pow er MOSFET L H/4A EN + SI C FB SBD pf NJW46 R FB IN- FB CT GND C F/ =5 R 7k R 5.k R NF 5k C NF,pF C T 47pF er

18 NJW46 Application Manual Application Design Examples (Continued) Setting Oscillation Frequency From the Oscillation frequency vs. Timing Capacitor Characteristic, C T =47 [pf], t=3.33[ s] at fosc=3khz. Inductance Current I L Peak Current Ipk Step-down converter duty ratio is shown with the following equation. Output Current I Duty IN F 5.4 Therefore, t ON =.5 [ s], t OFF =.83 [ s] 45 % Period t Frequency f OSC =/t t ON t OFF Selecting Inductance IL is Inductance ripple current. When to IL= output current 34%: I L =.34 I =.34 3 =. [A] Fig.. Inductor Current Waveform This obtains inductance L. DS_RON is drop voltage by MOSFET on resistance. IN DS RON L ton.5 [ H ] I L.. 5 Inductance L is a theoretical value. The optimum value varies according such factors as application specifications and components. Fine-tuning should be done on the actual device. This obtains the peak current Ipk at switching time. Ipk I I L [ A] The current that flows into the inductance provides sufficient margin for peak current at switching time. In the application circuit, use L= H/4A. Setting Over Current Detection In this application, current limitation value: I LIMIT is set to Ipk=4A. I LIMIT = IPK / R SC = m / 3m =4 [A] The limit value increases slightly according to response time from the overcurrent detection with the SI pin to the pin stop. I LIMIT _ DELAY I LIMIT L IN T DELAY 4. n 4.[ A] er.4-4-

19 NJW46 Application NJW46 Manual Application Design Examples (Continued) Selecting the Input Capacitor The input capacitor corresponds to the input of the power supply. It is required to adequately reduce the impedance of the power supply. The input capacitor selection should be determined by the input ripple current and the maximum input voltage of the capacitor rather than its capacitance value. The effective input current can be expressed by the following formula. I RMS I IN IN [A] In the above formula, the maximum current is obtained when IN =, and the result in this case is I RMS = I (MAX). When selecting the input capacitor, carry out an evaluation based on the application, and use a capacitor that has adequate margin. Selecting the Output Capacitor The output capacitor is an important component that determines output ripple noise. Equivalent Series Resistance (ESR), ripple current, and capacitor breakdown voltage are important in determining the output capacitor. The output ripple noise can be expressed by the following formula. ESR ripple( p p) I L When selecting output capacitance, select a capacitor that allows for sufficient ripple current. The effective ripple current that flows in a capacitor (I rms ) is obtained by the following equation. I rms I L [ marms] Consider sufficient margin, and use a capacitor that fulfills the above spec. In the application circuit, use C = F/6.3,. Setting Output oltage The output voltage is determined by the relative resistances of R, R. The current that flows in R, R must be a value that can ignore the bias current that flows in ER AMP. R R B 7k 5.k [ ] er

20 NJW46 Application Manual Compensation design example A switching regulator requires a feedback circuit for acquiring a stable output. Because the frequency characteristics of the application change according to the inductance, output capacitor, and so on, the compensation constant should ideally be determined in such a way that the maximum band is acquired while the necessary phase for stable operation is maintained. These compensation constants play an important role in the adjustment of the NJW46 when mounted in an actual unit. Finally, select the constants while performing measurement, in consideration of the application specifications. Feedback and Stability Basically, the feedback loop should be designed in such a way that the open loop phase shift at the point where the loop gain is db is less than -8. It is also important that the loop characteristics have margin in consideration of ringing and immunity to oscillation during load fluctuations. With the NJW46, the feedback circuit can be freely designed, enabling the arrangement of the poles and zeros which is important for loop compensation, to be optimized. The characteristics of the poles and zeros are shown in Fig.. Poles: The gain has a slope of - db/dec, and the phase shifts -9. Zeros: The gain has a slope of + db/dec, and the phase shift +9. If the number of factors constituting poles is defined as n, the change in the gain and phase will be n -fold. This also applies to zeros as well. The poles and zeros are in a reciprocal relationship, so if there is one factor for each pole and zero, they will cancel each other. Configuration of the compensation circuit Gain Phase Gain Phase f P / f Z / Pole f P f P Frequency Pole +db/dec Zero Fig.. Characteristics of Pole and Zero f Z Frequency Zero -db/dec f Z IN Driver L LC Gain RESR C CFB R ER AMP ref =.8 RFB PWM FB IN- R CNF RNF C(option) Fig.. Compensation Circuit Configuration - - er.4-4-

21 NJW46 Application NJW46 Manual Compensation Design (Continued) Poles and zeros due to the inductance and output capacitor Double poles f P(LC) are generated by the inductance and output capacitor. Simultaneously, single zeros f Z(ESR) are generated by the output capacitor and ESR. Each pole and zero is expressed by the following formula. f Z(ESR) C R ESR f P(LC) If the ESR of the output capacitor is high, f Z(ESR) will be located in the vicinity of f P(LC). In an application such as this, the zero f Z(ESR) compensates the double poles f P(LC), resulting in a tendency for stability to be readily maintained. However, if the ESR of the output capacitor is low, f Z(ESR) shifts to the high region, and the phase is shifted -8 by f P(LC).The NJW46 compensation circuit enables compensation to be realized by using zeros f Z and f Z. LC Poles and zeros due to error amplifier The single poles and zeros generated by the error amplifier are obtained using the following formula. Zero Pole fp f Z RR CNFRNF CNFA R R (Av: Amplifier Open Loop Gain=8dB) f Z C R FB f P C FB R FB NF RR R R f P3 (Option) CR LC Gain Loop Gain Compensation Gain Gain (db) Double pole -4dB/dec db frequency -db/dec * Gain increase due to Zero f Z and f Z are located on both sides of f P(LC). Because the inductance and output capacitor vary, they are each set using the following as a rough guide. f P(LC).5-fold.9-fold f P(LC).-fold.-fold f P f P(LC) f P f P3 f Z(ESR) f Z or f Z Fig. 3. Loop Gain examples There is also a method in which f Z and f Z are located at positions lower than even f P(LC). Because there is a tendency for the phase shift to increase and the gain to rise, it can be expected that the response will improve. However, there is a tendency for the phase margin to become insufficient, so care is necessary. f P creates poles in the low frequency region due to the Miller effect of the error amplifier. The stability becomes better as f P becomes lower. On the other hand, the frequency characteristics do not improve, so the response is adversely affected. f P is set using a frequency gain of db for f P(LC) as a rough guide. If the open loop gain of the error amplifier is made 8 db, design is carried out using f P < f P(LC) 3 (= 6 db) as a rough guide. Above several khz, various poles are generated, so the upper limit of the frequency range where the loop gain is db is set to fifth (/5) to tenth (/) of oscillation frequency. The f Z(ESR) in the high frequency region sometimes causes a loop gain to be generated (See Fig.3 Loop Gain ). Using f P and f P3, perform adjustment with the NJW46 mounted in an actual unit, so as to adequately reduce the loop gain in the high frequency region. er

22 NJW46 MEMO [CAUTION] The specifications on this databook are only given for information, without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - - er.4-4-