26-2 A NEW ZVS PWM VOLTAGE SOURCE INVERTER WITH ACTIVE VOLTAGE CLAMPING

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1 A NEW ZVS PWM VOLTAGE SOURCE INVERTER WITH ACTIVE VOLTAGE CLAMPING Adriano P6res'*' and Ivo Barbi INEP - Institute of Power Electronics UFSC - Federal University of Santa Catarina Phone: Fax: Cx.P.: CEP: Florian6polis - SC - Brazil inep.ufsc.br Abstract - This paper presents a new topology of a PWhl-ZVS voltage source inverter, which has been generated by generalisation of the PWM-ZVS active clamping DC-DC converters. Besides operation with soft commutation for a wide load range, the proposed topology has the feature of being modulated by any conventional PWM strategy employed in the hardswitching inverters. Operation description, analysis, design, simulation and experimental results are presented in the paper. I - INTRODUCTION To reduce the harmonic content and the audible noise in voltage source inverters it is desirable to operate at high switching frequencies. However, as the snitching frequency increases, the efficiency and reliahility of the PWM converter deteriorate significantly. Some efforts have been made to reach this aim and various topologies were proposed to achieve soft switching in voltage source inverters [I, 2,3,4,5,6]. The resonant pole inverter (RPI) [l] maybe was the first soft switching inverter topology. This circuit provides zero voltage switching (ZVS) in all switches, but it has an excessive resonant current that also circulate in the load. The rugged inverter (ARDPI) [2] combine the advantages of PWM strategy and soft switching techniques, but needs excessive resonant current to get soft commutation. The resonant current requires a minimum excess of twice the load current value. The auxiliary resonant pole inverter topology (ARF'I) [3] gives a good improvement regarding to this problem (theoretically). However it requires modification in the PWM strategy. In practice this topology needs the same level of resonant current that the ARDPI arrangement. Another topology, the auxiliary resonant commutated pole inverter (ARCPI) [4, 5, 61, has a different philosophy, the resonant pole is connected in parallel with the load. This type of circuit has a complex control strategy and the resonant current assumes large values that are reflected to the main switches increasing their current stress. In this work a new topology is presented, which combines the goals of soft switching commutation in all active switches, high frequency capability, conventional PWM strategy and no excessive additional voltage or current stress. I1 - CIRCUIT DESCRIPTION AND PRINCIPLE OF OPERATION The new zero-voltage-switching pulse-width modulation voltage-source inverter with active voltage clamping (ZVS-PWM-VSI-AVC) topology was derived from the family of ZVS-PWM activeclamping DC to DC converters [7]. The proposed inverter is shown in Fig. 1 and consists of two main switches (S2 and S3), two auxiliary switches (SI and S4), six diodes (Dl-D6), six resonant capacitors (Crler@, two resonant inductors (Lrl and Lr2) and two clamping capacitors (Cgl and Cg2), besides the DC bus and the load. I Figure 1 - The proposed ZVS-PWM voltage source inverter with active voltage clamping. The new soft commutation inverter presents nine stages of operation, explained as follows: (*) Adriano Pires is with Department of Electrical Engineering, Regional University of Blumenau (FURB). He is currently doing doctoral studies at INEPAJFSC. furb.rct-sc.br furb.rct-sc.br /99/$ IEEE

2 First Stage (to, tl): in this stage the main switch S2 is conducting. The current through Lrl is equal to the load current and the current through Lr2 is equal to zero. During this stage energy is transferred to the load. Second Stage (tl, t2): at the instant t=tl, switch S2 is turned-off and the resonant capacitors Cr2 and Cr5 are linearly charged. The voltage across Crl varies from zero to E+vgl and the voltage across Cr5 varies from zero to E. The resonant capacitors Crl and Cr6 are discharged and the voltages across their terminals vary from E+vgl and E to zero, respectively. The resonant current ilrl remains constant and equal to the load current. Third Stas (t2, f3): when the voltage across Cr2 equals E+vgl the voltage across Crl becomes null, and diode DI starts to conduct. Simultaneously the voltage across Cr5 becomes equal to E and the voltage across Cr6 becomes null, and diode 06 starts to conduct the load current. The inductor Lrl demagnetises through the clamping capacitor Cgl via DI. During this stage switch SI must be gated on, so that in the next stage soft commutation is achieved. Fourth Stage (t3, t4): when ikl becomes zero, diode DI is blocked and switch SI starts to conduct without commutation losses. Current ilrl changes its direction and increases linearly in a negative sense. Fifth Stage (t,, 5): at the instant t=t4, the switch SI is blocked. Capacitor Crl is charged and capacitor Cr2 is discharged in linear fashion, while the current through Lrl remains constant and equal to the load current. The voltage across Crl increases from zero to E+v,,, while the voltage across Cr2 decreases from tozero Sixth Stage (ts, 6): when vcrz becomes equal to zero, diode 0 2 starts to conduct the current ibj. In this stage Lrl is demagnetised through E and its energy is recovered. Seventh Stage (t6, t7): at the instant t=t6 the current through Lrl becomes null and diode 02 is blocked. Switch S2 starts to conduct without commutation losses. The current through Lrl increases sharply, fed by E via S2 and 06. Eighth Stag (t7, h): when iw becomes equal to the load current, the current in diode 06 becomes null, blocking it. A resonance involving Lrl, Crl, Cr3, Cr5 and Cr6 begins. The current through Lrl increases in sinusoidal fashion. The voltages across Crl and Cr5 decrease from E+vgl to vgl and from E to Zero, respectively, and the voltages across Cr3 and Cr6 increase from zero to E. E ilrl (t) = io( t )+-sin(wot Zn ) I and w0 =- JZZ Lr = Lrl = Lr2 and Cr = Crl =... = Cr6 Ninth Stage (ts, 4): when the voltage across Cr6 equals E, the voltage across Cr5 becomes null and diode D5 starts to conduct. The current through Lrl decreases as a consequence of the resistive elements present in the loop formed by S2, Lrl and D5. When the current through Lrl becomes equal to the load current, the first stage of operation restarts and one switching period is completed. The topological stages in one period of commutation are shown in Fig. 2, and the main theoretical waveforms are shown in Fig. 3. b) Second stage. g) Seventh stuge. h) Eighth stage. i) Ninth stage. Figure 2 - Topological stages in one switching period.

3 : j ; ; :. i ; I. I! : i. : 2,...._ i... : j io(t)! i i #,. * : Figure 4 -Normalised maximum clamping voltage. IV - COMMUTATION ANALISYS.... &... j j..,. *., Soft commutation is achieved when the following expression is satisfied. The regions for soft commutation are graphically represented by Fig :.i.... id.... *.. i,. : j. *. wt 2 asi.(s+ ( 4) Figure 3 - The main theoretical waveforms in one switching period THE CLAMPING ACTION Tjhe normalised clamped voltage vgl(t) is expressed by (2). The normalised maximum clamped voltage is given by (3) and it is represented graphically by Fig vgl(t) masin(wt) Vte*( t ) = - = E yrc fi[~-masin(wt)] -- v - g4l!5x - ma V<?I,, --- E 'yn fn(1-ma) Where: ma is the amplitude modulation ratio The maximum switches voltage is the sum of the DC bus voltage and the maximum clamped voltage. The clamped voltage can be easily controlled by an appropriate combination of resonant parameters (Cr and Lr). The resonant parameters also control the soft comniutation range. Figure 5 - SOJ? commutation regions. V - DESIGN PROCEDURE A 2.5kVA ZVS-PWM-VSI with active voltage clamping is designed to drive an induction motor with the following characteristics: Vo, =120V ; Io, = 20.8A ; fo = 6OHz ; lo,, = ; ma = 0.773; cos9 = 0.80 ; Lo = 9,2mH ; Ro = 4.6R ; Zo60Hz = The DC bus has a medium point and its total voltage is equal to E = 44W. Choosing fn=75 and the soft commutation range between 200 and 70" and with the aid of Fig. 5, y = 0. I1 76 is obtained. Hence: zo 2% = - = 48.98R Y fs = 7.8kHz fo = fs fn = 585kHz 2% Lr = - = 12.4pH 2rc fo Lr Cr = - = 1.3nF 2 zn2

4 I,?3 9 c t

5 fo = 6OHz ; ma = Ro = ; Lo = 8,54mH ; ZOt~o,yz = ; cosv = 0.80 Lr = 13.3pH ; Cr = 1.5nF; Cg = 35pF SI - S4 = SKM5OGB123D - Semikron D5-06 = HFAI5TB60 - International Rectifier The following figures show the experimental results for full load condition. Fig. 14 shows the voltage across and the current through the load. The clamping voltages across Cg1 and Cg2 - are shown in Fig. i5.?hey are limited to 40V. L L Figure I7 - Detail of Lrl current during one switching period (20Mdiv; 25ps/div). Fig. 18 shows the resonant current through Lr2 for one load period and Fig. 19 shows the same current for one switching period. Figure 14 - Voltage across and current through the load (I OOV/div; 2OMdiv; 2ms/div). Fig the L L Figure 15 - Clamped voltages in Cgl and Cg2 (IOV/div; 2ms/div). The resonant current through Lrl is shown in Fig. 16 for one load period and in Fig. 17 for one switching period. The maximum value of the resonant current is 40A. f ilrl I Figur,e 16 - Current through Lrl superposed with the load current (20Mdiv; 2ms/div). Figure 19 - Detail of Lrl current during one switching period (IOMdiv; 2Ops/div). Fig. 20 shows the voltage across S1 and the current through this switch. In Fig. 21 it is shown voltage across and current through the main switch S2. A detail of the turn-on process in the main switch is shown in Fig. 22. This figure proves that the turnon process ofs2 is entirely lossless. In Fig. 23 is shown a detail of turn-off process in the main switch S2. In this figure a superposition of the waveforms of voltage and current can be observed. This occurs because the measured current is the sum of isz and icr2. The pronounced tail current of the IGBT produces an additional power loss that can be avoided by choosing a better switch, e.g. the fourth generation IGBTs.

6 t 26-2 VIU - SUMMARY auxiliary switch SI (IOOV/div; IOAhdiv; 5 p/div). In this paper a new topology of soft commutation voltage-source inverter was presented and analysed. This new topology combines the advantages of a soft commutated converter and those of a conventional pulse-width modulation. The transistor voltage stress can be limited as close as necessary from the DC bus voltage and the maximum value of resonant current also can be controlled by the resonant parameters. Both simulation and experimental results show that the new proposed inverter reduces the losses of the IGBT by allowing zero voltage condition during tumon and turn-off process. Some of the advantages of the proposed inverter are: - zero-voltage-switching operation in a wide range of load current; - use of conventional PWM strategy; - integration of all major parasitic components; - ease of implementation with power modules. IX - REFERENCES main switch S2 (IOOV/div; IO Ndiv; Iwdiv). Figure 22 -Detail of the main switch S2 turn-on process (IOOV/div; 10 Ndiv; 2ps/div). - process (IOOV/div; IO A/div; 2OOns/div). "- [l]boyer, S.; FOCH, H.; ROUX, J.; METZ, M. Chopper and PWM Inverter Using GTO's in Dual Thyristor Operation. Proceedings of Second European Conference on Power Electronics and Applications, 1987, pp [2] CHERITI, A.; HADDAD, A.; DESSAINT, L. A.; MEYNARD, T. A.; MUKHEDKAR, D. A Rugged Soft Commutated PWM Inverter for AC Drives. Conference Records of IEEE PESC, 1990, pp [3]FOCH, H.; CHERON, Y.; METZ, M.; MEYNARD, T. Commutation Mechanisms and Soft Commutation in Static Converters. Proceedings of First Brazilian Power Electronics Conference, 1991, pp [4] BINGEN, G. Utilisation de Transistor a Fort Current e Tension Elevee. Proceedings of First European Conference on Power Electronics and Applications, 1985, pp [5] McMURRAY, W. Resonant Snubbers with Auxiliary Switches. Conference Records of IEEE IAS Annual Meeting, 1989, pp [6]DE DONCKER, R. W.; LYONS, J. P. The Auxiliary Resonant Commutated Pole Converter. Conference Records of IEEE IAS Annual Meeting, 1990, pp [7] DUARTE, C. M. C.; BARBI, I. A New Family of ZVS-PWM Active-Clamping DC-to-DC Boost Converters: Analysis, Design, and Experimentation. IEEE Transactions on Power Electronics, vol. 12, No 5, July 1997, pp [8] CARSTEN, B. Design Techniques for Transformers Active Reset Circuits at High Frequencies and Power Levels. Conference Records of IEEE HFPC 1990, pp