Soft-Switched Three Level Capacitor Clamping Inverter with Clamping Voltage Stabilization

Transcription

1 Soft-Switched Three Level Capacitor Clamping Inverter with Clamping Voltage Stabilization Xiaoming Yuan Power Electronics and Electrometrology Laboratory Swiss Federal Institute of Technology Zurich CH-8092, Switzerland Phone: Fax: Abstract: This paper proposes a zero voltage switching scheme for the three-level capacitor clamping inverter. The small rating auxiliary circuit proposed ensures not only zero voltage switching of the main switches and zero current switching of the auxiliary switches, the clamping voltage of the inverter is also stabilized. The scheme prevents any voltage or current spikes from happening over the main or auxiliary switches and no modulation constraints are necessitated. Operation, analysis, designing and testing aspects of the scheme are detailed. I. INTRODUCTION A. Neutral-Point-Clamped (NPC) Inverter [I] Versus Three Level Capacitor Clamping Inverter[4] In the recent decade, Neutral-Point-Clamped (NPC) [ 11 inverter has been increasingly used in such high power applications as traction, industrial drive and even FACTS systems [2]. With the available switching devices, the NPC inverter increases the per-unit capacity while it reduces the output voltage harmonics. However, the NPC inverter has the drawbacks that follow. a/. Two additional diodes of equal working conditions as the freewheeling diodes are required in each NPC leg for clamping of the inverter output to the neutral rail. Additional components in the leg tend to increase the physical size challenging low-inductance designing [ 21. b/. The two inner devices in each leg are not directly clamped to the DC rails and they may be subject to higher blocking voltage in practice depending on the stray inductances of the neutral rail [3]. The three level capacitor clamping inverter [4] offers an alternative approach for high power conversion. However, it had received little attention until the introduction of the so called Imbricated Cells [5]. The Imbricated Cells configuration can work either as an inverter [6] or as a chopper [7]. Chopper function of the Imbricated Cells is deemed a significant advantage over the NPC configuration, as a single NPC leg can not form a multilevel chopper, unless two legs are used [8]. The three level capacitor clamping inverter uses a storage capacitor in each leg for clamping of the two inner devices, avoiding the use of the two fast diodes in the Ivo Barbi Power Electronics Institute Federal University of Santa Catarina , Florianopolis-SC, Brazil Phone: Fax: NPC inverter. In particular, when the clamping capacitor voltage is kept stable, the two inner devices can then be clamped as tightly as that in the normal two level inverter. As the storage capacitor serves only for high frequency switching ripple filtering, the capacitance can be far smaller than the DC link storage capacitor which is always required to offer energy storage for system transience buffering. Under sub-harmonic PWM modulation, it has been well proved that the clamping capacitor voltage is selfbalancing when the inverter load is not pure-reactive [6] [3]. However, in practice, the clamping capacitor voltage may be drifted to some extent depending on the asymmetry seen in the control circuit (gating pattern, switching delay etc.) as well as in the main circuit (device conduction voltage etc.). Such drift leads to inverter output voltage distortion and unacceptable blocking voltage, which call for feedback control loop to be introduced against the drift. Sophisticated monitoring and controlling circuit will be needed adding to the cost and complexity of the system. Without regard to the modulation pattern, the monitoring shall always involve both the clamping capacitor voltage as well as the instantaneous load current. B. Auxiliary-Resonant-Commmutated-Pole-Inverter [9] (ARCPI) Versus True-PWM-Pole Zero Voltage Switching Pole Inverter [Ill and Transformer Assisted PWM Zero Voltage Switching [I21 Pole Inverter Due to the enormous switching loss, switching frequency of today s high power IGBTs under hard switching condition is severely limited to a few khz. Previous work [3] has introduced the Auxiliary-Resonant- Commutated-Pole-Inverter (ARCPI) technique [9] for zero voltage switching of the capacitor clamping inverter, as shown in Fig. 1. As has been known in the two-level case, this technique requires complicated control to ensure reliable operation of the circuit [IO]. The control complexity with the ARCPI scheme results from the DC link center-tap configuration for the auxiliary circuit. On the one hand, this configuration limits the voltage source for the commutation resonance /99/$ IEEE. 502

2 to half DC link voltage, which warrants for the boost stage to be as introduced as discussed in [9]. Further, unless specific control is included, the floating center-tap potential brings about an unreliable system [lo], especially when asymmetry between the DC link capacitors is taken into account. The True-PWM-Pole soft switching scheme [ll], as shown in Fig. 2, utilizes a half bridge structure in the auxiliary circuit, avoiding the center-tap configuration in the ARCPI scheme, while an auto-transformer is used for synthesizing the voltage source for the commutation resonance. The voltage source so built can then be valued at more than half DC link voltage by setting appropriately the auto-transformer ratio (N2/N1<1/2), which enables simultaneous turn-off of the main switch with turn-on of the corresponding auxiliary switch. The need for a boost stage for the commutation as needed in the ARCPI scheme is removed. control. Unfortunately, the feature of current sharing with the True-PWM-Pole scheme is lost. The auxiliary switch carries almost the same current as that in the ARCPI scheme I as a result. 1 I I I Fig. 2. True-PWM-Pole zero voltage switching pole inverter proposed in [I I], where k=nz/n1<1/2. Fig. 1. ARCPI three level capacitor clamping inverter scheme 131. Especially, in comparison with the ARCPI scheme, the auxiliary switch current stress in the True-PWM-Pole circuit is nearly halved ((1-k) times, k=n2/ni) as the resonant inductor current is shared between the auxiliary switch and the auto-transformer primary winding. Nevertheless, the auto-transformer in the True-PWM- Pole structure is found not being able to be reset [lo] following each commutation, due to the freewheeling paths existing between the auxiliary devices and the main devices through windings of the auto-transformer, which renders the scheme not practically applicable. The transformer assisted PWM zero voltage switching scheme recently proposed [ 121 (k=n2/n1<1/2), as shown in Fig. 3, overcomes the auto-transformer resetting problem by means of a transformer replacing the autotransformer in the auxiliary circuit, while the bridge configuration of the auxiliary devices is kept. The scheme allows for reliable high power operation with no extra Fig. 3. Transformer assisted PWM zero voltage switching pole inverter proposed in [12], where k=ndn,<i/2. C. Objective of This Paper This paper proposes a zero voltage switching threelevel capacitor clamping inverter. The circuit employs the transformer assisted PWM zero voltage switching scheme in the inner switching cell and the True-PWM-Pole zero voltage switching scheme in the outer switching cell. The True-PWM-Pole in the outer cell is no longer afflicted with the auto-transformer resetting problem existing in the normal two-level inverter, because of the clamping capacitor involved in the freewheeling paths. Most significantly, due to the charging and discharging paths 503

3 established by the True-PWM-Pole auxiliary circuit, the clamping capacitor voltage as well as the DC link neutral potential is forced to be stable without regard tc any asymmetry in the main or control circuit, no specific feedback control is needed as a result. 11. PROPOSED CIRCUIT AND ITS OPERATION I 1 Qf 1 1 c A. Proposed Circuit and Its Soft Switching Fig. 4 shows the circuit scheme of the proposed zero voltage switching three level capacitor clamping inverter. On the main circuit, SI/S4 is a switching pair forming the outer switching cell, whereas S2/S3 is another switching pair forming the inner switching cell. Given a constant clamping capacitor voltage, the two cells are actually independent from each other. Each cell can be controlled by the normal sub-harmonic PWM pattern, with the two carriers for the two switching cells being phase shifted by TC: offering an optimal output spectrum [3]. Obviously, the commutation of the inner switching cell S2/S3 is assisted by the auxiliary branch Sa21Sa3 exactly in the same way as in the two-level case [ 121. Given further a stable DC link neutral potential at 0, i.e. Vcl=Vc~=V&, the outer switching cell Sl& will see actually a similar commutation procedure as the inner one. Take D4 to SI commutation for example, refereing to Fig. 5, when S4 is turned off at ti, Sa4 will be turned on simultaneously leading to conduction of Dal and voltage of [W( l+k)]vd,/2 reflected on Nz (k=n2 /N1 <1). Capacitor Cz voltage (Vd,/2) then joins Nz voltage forcing the decreasing of the current in D4 and subsequently the resonance among LI4, Cr4 and Crl when D4 blocks at t2. Upon full discharging of CrI at t3, DI will conduct and Sf gating signal will be released by the zero voltage detecting circuit across it. SI will then start carrying current as the resonant inductor current falls below the load current at t4. Upon extinction of the resonant inductor current at t5, Sa4 gating signal can be withdrawn and SI will take the full load current. Apparently, SI to D4 commutation will proceed in a similar way and will not be addressed in details. Consequently, in the proposed circuit, with simple control for the auxiliary circuit, all the main switches work at zero voltage turn-on and capacitive turn-off, while all the auxiliary switches work at zero current turnoff and inductive turn-on, resulting in truly lossless commutations and therefore ample space for switching frequency increase. Stability of the clamping capacitor voltage, stability of the DC link neutral potential (0), as well as the resetting of the auto-transformer switching in the outer switching cell will be treated respectively as following. T Fig. 4. Proposed soft-switched three-level capacitor clamping inverter, where N~ /NI <~ and N2/Nl<l/2. APWM gating signal At ,......I Fig. 5. Relevant theoretical commutation waveforms during Dd to SI commutation and the reverse in the outer switching cell. B. Clamping Capacitor Voltage Stabilization and DC Link Neutral Potential Stabilization Thanks to the specific configuration of the proposed circuit, the clamping capacitor voltage is prevented from being higher or lower than either of the DC link capacitor voltage. This mechanism guarantees the stabilization of the clamping capacitor voltage as well as the stabilization of the DC link neutral potential, as explained following. When SI is gated, if the clamping capacitor voltage is lower than the up-capacitor CI voltage, then it will be charged by the up-capacitor through SI, Dm4, N2 and LrI4, as shown in Fig. 6(a), whereas the down-capacitor C2 is also charged. In the other instance, when S4 is gated, if 5 04

4 the clamping capacitor voltage is lower the downcapacitor C2 voltage, then it will be charged by the downcapacitor CZ through S4, DUI and Lr14, as shown in Fig. 6(b), while the up-capacitor CI is also charged. As SI and S4 conduct alternatively all the time except for the deadtime interval, the clamping capacitor voltage can not be lower than either of the DC link capacitor voltage. Also, the clamping capacitor voltage can not be higher than either of the DC link capacitor voltage. Without regard to the initial value of the clamping capacitor voltage, the clamping capacitor will be discharged to the up-capacitor C1 through D1, LrI4, NZ and Sa4 during S4 to SI commutation when Sa4 is gated, as shown in Fig. 6(c), while the down-capacitor C2 is also discharged. In the other instance, it will be discharged to the down-capacitor C2 through Sal, Nz, Lr14 and D4 during SI to S4 commutation when Sal is gated, as shown in Fig. 6(d), while the up-capacitor C1 is also discharged. In either case, if the clamping capacitor voltage is lower than corresponding up or down-capacitor voltage when the commutation ends, it will be charged subsequently by SI or S4 until arriving at the corresponding up or down capacitor voltage. On the other hand, the commutation will not end as long as the clamping capacitor voltage is higher than the corresponding up or down capacitor voltage. It will end when the clamping capacitor voltage gets equal to the corresponding DC link up or down capacitor voltage. Note that here it has been assumed that the auxiliary switch conduction duration is sufficiently long to cover the commutation resonance. r I I? I 1 (a) charging path by up DC link capacitor C, when SI is gated - lrging path by down DC link capacitor C2 when S4 is gi d (c) discharging path to up DC link capacitor C, when Sd is gated (d) discharging path to down DC link capacitor CI when Sal is gated Fig. 6. Charging (discharging) paths for the clamping capacitor through the main circuit and the auxiliary circuit. In summary, the clamping capacitor voltage can not be the DC link capacitor voltage. And, the DC link neutral lower than either of the DC link capacitor voltage due to potential must be stable even though there is an the charging paths established by the main switch SI or asymmetry existing between the two DC link capacitors. S4. Meantime, it can not be higher than either of the DC The stability of the clamping capacitor voltage as well link capacitor voltage due to the discharging paths as the DC link neutral potential is deemed an interesting established by the auxiliary switch Sa4 or Sal. As a result, property of the proposed circuit, which greatly enhances the clamping capacitor voltage must be equal to either of the practicablity of the circuit. It is also a significant

5 advantage of the proposed circuit over the ARCPI three level capacitor camping inverter, as shown in Fig. 1. C. True-PWM-Pole in the Outer Switching Cell The auto-transformer resetting problem arising from the True-PWM-Pole zero voltage switching pole inverter originates essentially from the commutation residual current flowing from the active auxiliary switch to the incoming main switch through the auto-transformer secondary winding and the resonarlt inductor [ 101, during the interval after the auto-transformer primary winding current arriving at zero and before the turning-off of the auxiliary switch. For instance, in Fig. 2, a residual current flowing from Sal through N2 and Lr to S2 after NI current reaching zero and before turning-off of Sal during Dl to Sz commutation will result in the auto-transformer magnetization not being able to be reset when auxiliary switch Sal is turned off. For the outer switching cell of the proposed circuit, however, such residual current loop always involves the clamping capacitor and the corresponding DC link up or down capacitor. For S4 to SI commutation, the loop involves LrI4. N2, SadjDsa4, C, SJDI and Cl. For SI to S4 commutation, on the other hand, the loop involves Lr14, N2, Sal/Dm,, C, SdjD4 and C2. In either case, no residual current will likely to flow in the loop continuously, as the voltage of the clamping capacitor shall become equal to the corresponding DC link capacitor voltage before the expiring of the auxiliary switch conduction duration, according to the analysis in the previous section regarding clamping capacitor voltage stabilization. This is deemed reasonable taking into account the small time constant of the charging/discharging loop (resonant inductance and thermal resistance) as well as the usual margin considered in the auxiliary switch conduction duration designing. With no residual current, the auto-transformer will be reset appropriately. As such, the True-PWM-Pole zero voltage switching pole scheme is applicable to the outer switching cell of the proposed circuit without suffering from any auto-transformer resetting problem. As mentioned before, the True-PWM-Pole scheme reduces the current rating of the auxiliary switch to nearly half (1/( l+k) times, k=n2 /NI ) in comparison to the ARCPI case or the case of the transformer assisted PWM zero voltage switching pole, in either case the auxiliary switch carries the full resonant inductor current. Note that, as shown in Fig. 4, the auto-transformer winding connection has been modified in comparison with that shown in Fig. 2. The modified connection allows the auto-transformer secondary winding to carry the auxiliary switch current, instead of the resonant inductor current, without affecting the auto-transformer secondary voltage for synthesizing the auxiliary voltage source for the commutation resonance. However, The auto-transformer size is nearly halved as a result ANALYSIS AND DESIGNING Characteristic curves for the transformer assisted PWM zero voltage switching pole inverter, including the commutation duration, the peak resonant current as well as the RMS resonant current related to the load current, transformer ratio and switching cycle, in cases of both diode to switch commutation and switch to diode commutation, have been comprehensively addressed in [ 121. These curves remain true for the True-PWM-Pole zero voltage switching pole inverter case utilized in the outer switching cell of the proposed circuit, as shown in Fig. 4, except for that the auxiliary switch current and also the auto-transformer secondary winding current (peak or RMS) is l/(l+k) times of the resonant current, as mentioned before. Designing of the circuit should be done based on these curves. Before all, the auto-transformer ratio should be set less than 1 (outer switching cell) or 1/2 (inner switching cell) dependent on the actual resonant loop resistance, to ensure the pole voltage swinging to the rail level during the commutation resonance. This requirement is hard and must be observed without bargaining. In addition, the resonant capacitance can be designed as per the device turn-off loss and the thermal conditions associated. Resonant inductance can then be decided according to the accepted resonant circuit RMS stress, taking into account the system operating frequency. Rating of the auxiliary device can be made according to the auxiliary device RMS current stress, and the peak current stress as well. In addition, gating signal width for the auxiliary switch must cover the maximum commutation duration and remains constant over the low frequency cycle. Gating signal width dimensioning must also consider the necessary margin dealing with charging and discharging interaction of the clamping capacitor with the corresponding DC link capacitor, in order to guarantee that the clamping capacitor voltage becomes equal to the corresponding DC link capacitor voltage within the auxiliary switch conduction duration. In the meantime, the minimum pulse width in the inverter PWM pattern should not be less than this duration. The next commutation should not start before the conclusion of the previous commutation. On the other hand, auto-transformer or transformer designing can be based on the knowledge of commutation (magnetization) duration and the RMS resonant inductor current stress. With peak and RMS resonant inductor current information, the resonant inductor is designed. 506

6 IV. EXPERIMENTATION VERIFICATION A half bridge three level capacitor clamping inverter prototype has been built in the laboratory. The main circuit of the prototype has been modulated by subharmonic PWh4 pattern, as detailed in [3]. Specifications of the prototype are given in Table 1. The parameters of the half bridge laboratory prototype are: b14=b23=15~h, Crl=C~=Cr3=Cr4=0. luf, N2/N1=0.4 and N2'/NI'=0.67. SI- S4 and Sal-Sa4 used are SKM50GB123D (1200V/50A), Da1-Da4, Dd'-Da3', used are HFA30T60C (600V/30A). Besides, DC capacitors used are C1=C2=3300uF, each with a nominal voltage of 350V. The clamping capacitor in use is 2750uF with a nominal voltage of 500V (two 55OOuF/25OV capacitors in series). The half bridge inverter output is installed with a second order LC filter with L~1.45mH and C,=l2uF. Gating signal width of the auxiliary switch is set at 14.4uS. Minimum pulse width is set at 28.8uS and maximum pulse width is set at 124.8~s. Dead time of 2.4uS is inserted for each switching cell. Besides, four zero voltage detecting circuits are employed to interface the four SEMIKRON SKHIlO drivers to the four main IGBTs respectively [3]. Fig. 6. Experimental three level output voltage of the 3kW half-bridge three level capacitor clamping inverter prototype. DCinput voltage output power Table 1. Specifications of the 3kW half bridge V,= 700V Po' 3kW output V0.- modula- M= voltage =140V tion index 0.62 load I,.,, switching f,- current =21 SA frequency 6.5kHz Fig. 6 shows the prototype half-bridge inverter output voltage waveform. The stable three level output verifies well the stability of the clamping capacitor voltage as well as the stability of the DC link neutral potential. Careful examine of the waveform reveals that the zero level is actually not constant at true zero voltage and instead is subject to a small fluctuation, which arises due to such diverse factors as different component conduction voltage drops, different storage capacitor charging/discharging states etc.. It is worth mentioning that the self-balancing ability contributes also to the stability of the clamping capacitor voltage. Fig. 7 shows the voltage and current waveforms of the main switch SI during turn-on and turn-off commutation processes. As expected, the main switch works with zero voltage turn-on and capacitive turn-off. Meantime, neither voltage nor current spike arises. Fig. 8 shows the waveforms of the auxiliary switch Sal voltage and current as well as the load current during turn-on and turn-off commutation processes. The auxiliary switch works with inductive turn-on and zero current turn-off.., , :..... :...:......; i... i ~ : :..,, : :..., :...: :..., :.... Fig. 7. Experimental voltage and current waveforms of the main switch SI. Main switch works with zero voltage tum-on and capacitive turn-off..:. ; ;.... : / / / /.... : : :. :......?... i....i. :. ; / j i / j IOoViDlV, IOA/DIV, IOUSiDIV Fig. 8. Experimental wavefoms of the auxiliary switch Sat voltage and current, as well as the load current. Auxiliary switch works with inductive turn-on and capacitive turn-off. 507

7 V. CONCLUSIONS The proposed soft-switched three-level capacitor clamping inverter guarantees zero voltage switching of the main switch and zero current switching of the auxiliary switch, without incurring any voltagdcurrent spikes over the main/auxiliary switches. Unlike the ARCPI three level capacitor clamping inverter circuit, the proposal requirs no additional monitoring or controlling for the auxiliary circuit. The current stress of the auxiliary switches in the outer switching cell is almost halved (U( l+k) times) due to the use of the True-PWM-Pole, without yet suffering from the auto-transformer resetting problem in the normal two level True-PWM-Pole inverter. In particular, the clamping capacitor voltage as well as the DC link neutral potential is forced to be stable during the operation, regardless of the possible asymmetry in the main or control circuit. The proposal can be used to advantage for such advanced applications in high speed drive or active power filtering areas where high switching frequency operation is necessary. [8] Hengchun Mao, Dusan Boroeyvich and Fred Lee, Multilevel 2-Quadrant Boost Choppers for Superconducting Magnetic Energy Storage, Record of IEEE APEC, 1996, pp [9] R. W. De Doncker and J. P. Lyons, The Auxiliary Resonant Commutated Pole Inverter, Record of IEEE IAS, 1990, pp [lo] Xiaoming Yuan and Ivo Barbi, Control Simplification and Stress Reduction in a Modified PWM Zero Voltage Switching Pole Inverter, Record of IEEE APEC, [ll] I. Barbi and D. C. Martins, A True-PWM-Pole Zero Voltage Switching Pole With Very Low Additional RMS Current Stress, Record of IEEE PESC, 1991, pp [12] Xiaoming Yuan and Ivo Barbi, A Transformer Assisted PWM Zero Voltage Switching Inverter, Record of IEEE PESC ACHONOLOGMENTS The advice from Dr. Roberto Rojas, a visiting scholar in the Power Electronics Institute, Federal University of Santa Catarina, Brazil, is sincerely appreciated. REFERENCES [l] A. Nabae, I. Takahashi, and A. Akagi, A New Neutral-Point Clamped PWM Inverter, IEEE Trans. Ind. App., Vol. 19, No. 5, Sep./Oct. 1981, pp [2] B. A. Renz, A. J. F. Keri, A. S. Mehraban, J. P. Kessinger, C. D. Schauder, L. Gyugyi, L. J. Kovalsky and A. A. Edris, World s First Unified Power Flow Controller, CIGRE Paper , [3] X. Yuan, Soft Switching Techniques for Multilevel Inverters, Ph. D Thesis, INEP-UFSC, [4] T. Maruyama and M. Kumano, New PWM Control for A Three-Level Inverter, Record of IPEC, 1990, pp [5] T. Meynard and H. Foch, Multi-Level Conversion: High Voltage Choppers and Voltage Source Inverters, Record of IEEE PESC, 1992, pp [6] P. Cadre, T. Meynard and J. P. Lavieville, 4000V- 300A Eight-Level IGBT Inverter Leg, Record of EPE Conference, 1995, pp [7] F. Hamma, T. A. Meynard, F. Tourkhani and P. Viarouge, Charcteristics and Design of Multilevel Choppers, Record of IEEE PESC, 1995, pp