2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT 2016)
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1 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT 2016) Hsinchu, Taiwan April 2016 IEEE Catalog Number: ISBN: CFP16847-POD
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3 TABLE OF CONTENTS A MHZ PASSIVE NFC TAG IC IN 0.18-µM CMOS PROCESS FOR BIOMEDICAL APPLICATIONS... 1 Chi-Huan Lu ; Ji-An Li ; Tsung-Hsien Lin MULTIPLE OUTPUT SWITCHED CAPACITOR DC-DC CONVERTER WITH CAPACITOR SHARING FOR SENSOR-FUSION PLATFORMS... 5 Yu-Jie Liang ; Po-Hung Chen ; Hung-Pin Lu ; Yuan-Hua Chu ; Wei Hwang A LOW-POWER OSCILLATOR-BASED READOUT INTERFACE FOR MEDICAL ULTRASONIC SENSORS... 9 Teng-Chuan Cheng ; Chih-Wei Chen Hsu ; Hui-Chun Wang ; Tsung-Heng Tsai A 12B 10MS/S 18.9FJ/CONVERSION-STEP SUB-RADIX-2 SAR ADC Kwuang-Han Chang ; Chih-Cheng Hsieh A 2.5-BIT/CYCLE 10-BIT 160-MS/S SAR ADC IN 90-NM CMOS PROCESS Chia-Hsin Lee ; Chih-Huei Hou ; Chun-Po Huang ; Soon-Jyh Chang ; Yuan-Ta Hsieh ; Ying-Zong Juang DAC LINEARITY IMPROVEMENT ALGORITHM WITH UNIT CELL SORTING BASED ON MAGIC SQUARE Masashi Higashino ; Shaiful Nizam Mohyar ; Haruo Kobayashi FUNDAMENTAL DESIGN CONSIDERATION OF SAMPLING CIRCUIT Keita Kurihara ; Kensuke Kobayashi ; Masafumi Uemori ; Miho Arai ; Haruo Kobayashi LINEAR PRECODING AND ADAPTIVE MULTI-TAPER SPECTRUM DETECTOR FOR COGNITIVE RADIOS Yi-Han Tseng ; Terng-Hsing Chiu ; Jung-Mao Lin ; Hsi-Pin Ma TEMPERATURE TRACKING SCHEME FOR PROGRAMMABLE PHASE-SHIFTER IN PULSED RADAR SOC Yun-Jia Liao ; Shi-Yu Huang TIME-DOMAIN CHARACTERISTICS OF BODY CHANNEL COMMUNICATION (BCC) AND BCC TRANSCEIVER DESIGN Ching-Che Chung ; Chih-Yu Lin ; Jia-Zong Yang A 7 GB/S HALF-RATE CLOCK AND DATA RECOVERY CIRCUIT WITH COMPACT CONTROL LOOP Yu-Po Cheng ; Yen-Long Lee ; Ming-Hung Chien ; Soon-Jyh Chang A 2X25GB/S 20MW SERIALIZING TRANSMITTER WITH 2.5:1 MULTIPLEXERS IN 40NM TECHNOLOGY Bo-Jing Lin ; Wei-Sung Chang ; Tai-Cheng Lee A HYBRID FREQUENCY/PHASE-LOCKED LOOP FOR VERSATILE CLOCK GENERATION WITH WIDE REFERENCE FREQUENCY RANGE Sitao Lv ; Ni Xu ; Woogeun Rhee ; Zhihua Wang THE LED DRIVER IC OF VISIBLE LIGHT COMMUNICATION WITH HIGH DATA RATE AND HIGH EFFICIENCY Yu-Chen Lee ; Jyun-Liang Lai ; Chueh-Hao Yu AN INTEGRATED PLACEMENT AND ROUTING FOR RATIOED CAPACITOR ARRAY BASED ON ILP FORMULATION Pang-Yen Chou ; Mark Po-Hung Lin ; Helmut Graeb AUTOMATIC SYNTHESIS FLOW FOR VOLTAGE RECTIFIERS WITH IMPEDANCE CONSIDERATION Fang-Yu Jhou ; Chang-Han Wang ; Tsung-Yueh Wu ; Yu-Kang Lou ; Chien-Nan Jimmy Liu AREA MINIMIZATION METHOD FOR CMOS CIRCUITS USING CONSTRAINT PROGRAMMING IN ID-LAYOUT STYLE Hayato Mashiko ; Yukihide Kohira THERMPL: THERMAL-AWARE PLACEMENT BASED ON THERMAL CONTRIBUTION AND LOCALITY Jiaxing Song ; Yu-Min Lee ; Chia-Tung Ho MIRAVISION TM SMARTSCREEN - MEDIATEK'S APPROACH TO POWER SAVING FOR DISPLAYS Ying-Jui Chen ELECTRICAL/THERMAL CO-DESIGN AND CO-SIMULATION, FROM CHIP, PACKAGE, BOARD TO SYSTEM C. T. Kao ; An-Yu Kuo ; Yun Dai
4 ARM PLATFORM FOR PERFORMANCE AND POWER EFFICIENCY - HARDWARE AND SOFTWARE PERSPECTIVES Ivan Lin ; Brian Jeff ; Ian Rickard A 98.6µW ACOUSTIC SIGNAL PROCESSOR FOR FULLY-IMPLANTABLE COCHLEAR IMPLANTS Hao-Min Liu ; Yung-Jen Lin ; Yu-Chi Lee ; Cheng-Yen Lee ; Chia-Hsiang Yang A 1.4 MW LOW-POWER FEED-BACK FXLMS ANC VLSI DESIGN FOR IN-EAR HEADPHONES Hong-Son Vu ; Kuan-Hung Chen A MULTI-AXIS READOUT CIRCUIT USING IN FEMALE OVULATION MONITORING PLATFORM Hsin-Yi Yu ; Kelvin Yi-Tse Lai ; Hsie-Chia Chang ; Chen-Yi Lee 2.5D SYSTEM SYNTHESIS METHODOLOGY UNDER PERFORMANCE, POWER AND THERMAL CONSTRAINTS Chung-Han Chou ; Zhi-Yang Wang ; Tsui-Yun Chang ; Shih-Hsu Huang ; Shih-Chieh Chang GUIDELINES FOR EFFECTIVE AND SIMPLIFIED DYNAMIC SUPPLY AND THRESHOLD VOLTAGE SCALING Toshinori Takeshita ; Tohru Ishihara ; Hidetoshi Onodera A HIGH-LEVEL SYNTHESIS ALGORITHM FOR FPGA DESIGNS OPTIMIZING CRITICAL PATH WITH INTERCONNECTION-DELAY AND CLOCK-SKEW CONSIDERATION Koichi Fujiwara ; Kazushi Kawamura ; Masao Yanagisawa ; Nozomu Togawa SINGLE LAYER DIFFERENTIAL GROUP ROUTING FOR FLIP-CHIP DESIGNS I-Jye Lin ; Ming-Jen Yang ; Kai-Shun Hu AUTOMATIC MIXED-SIGNAL BEHAVIORAL MODEL GENERATION ENVIRONMENT Yun-Jing Lin ; Meng-Jung Lee ; Yu-Lan Lo ; Shu-Yi Kao DATA ANALYTICS TO AID DETECTION OF MARGINAL DEFECTS IN SYSTEM-LEVEL TEST Harry H. Chen 28NM ULTRA-LOW POWER NEAR-/SUB-THRESHOLD FIRST-IN-FIRST-OUT (FIFO) MEMORY FOR MULTI-BIO-SIGNAL SENSING PLATFORMS Wei-Shen Hsu ; Po-Tsang Huang ; Shang-Lin Wu ; Ching-Te Chuang ; Wei Hwang ; Ming-Hsien Tu ; Ming-Yu Yin A 128-KB 25% POWER REDUCED 1T HIGH DENSITY ROM WITH 0.55 NS ACCESS TIME USING LOW SWING BITLINE EDGE SENSING IN 16NM FINFET TECHNOLOGY Sachin Taneja ; Vaibhav Verma ; Prashant Dubey A 1V 800MHZ 140KB REGISTER FILE COMPILER USING VARIATION AWARE SELF- TIMING IN 40NM BULK CMOS Rachit Dave ; Vivek Kumar Dikshit ; Prshant Dubey 3D-IC TEST ARCHITECTURE FOR TSVS WITH DIFFERENT IMPACT RANGES OF CROSSTALK FAULTS Wen-Hsuan Hsu ; Michael A. Kochte ; Kuen-Jong Lee SERL: SOFT ERROR RESILIENT LATCH DESIGN Chun-Wei Jacky Chang ; Hsuan-Ming Ryan Huang ; Yuwen Lin ; Charles H. -P. Wen A TEST-PER-CYCLE BIST ARCHITECTURE WITH LOW AREA OVERHEAD AND NO STORAGE REQUIREMENT Chung-Min Shiao ; Wei-Cheng Lien ; Kuen-Jong Lee ARCHITECTURE AGNOSTIC ENERGY MODEL FOR GPU-BASED DESIGN Arthur Marmin ; Chun-Hung Lai ; Haruyuki Tago ; Hsun-Lun Huang ; Juin-Ming Lu SNIPER-TEVR: CORE-VARIATION SIMULATION PLATFORM WITH REGISTER-LEVEL FAULT INJECTION FOR ROBUST COMPUTING IN CMP SYSTEM Ching-Yao Chou ; Yi-Chieh Ho ; Huai-Ting Li ; An-Yeu Andy Wu INTERFERENCE-AWARE BATCH MEMORY SCHEDULING IN HETEROGENEOUS MULTICORE ARCHITECTURE Chun-Hsien Lu ; Hung-Lin Chao ; Yi-Chien Song ; Pao-Ann Hsiung SCALABLE MUTLI-LAYER BARRIER SYNCHRONIZATION ON NOC Yu-Lun Tseng ; Kun-Hua Huang ; Bo-Cheng Charles Lai NON-VOLATILE MEMORY VERSUS BIG DATA Tei-Wei Kuo STORAGE CONSIDERATION FOR BIG DATA IN THE CLOUD Yun-Ping Hsu
5 SDA: SOFTWARE-DEFINED ACCELERATOR FOR LARGE-SCALE DEEP LEARNING SYSTEM Jian Ouyang UNSUPERVISED HIERARCHICAL CLUSTERING BASED ON SEQUENTIAL PARTITIONING AND MERGING Sheng-Jyh Wang MANUFACTURING INTELLIGENCE AND SMART PRODUCTION FOR INDUSTRY 3.5 AND EMPIRICAL STUDY OF DECISION-BASED VIRTUAL METROLOGY FOR CONTROLLING OVERLAY ERRORS Chen-Fu Chien ; Ying-Jen Chen INNOVATIONS SUCH AS AUTONOMOUS DRIVING DEMAND NEW METHODS AND TOOLS IN SYSTEMS ENGINEERING Eric Sax MICROCONTROLLER IMPLEMENTATION OF LOW-POWER COMPRESSION FOR WEARABLE BIOSIGNAL TRANSMITTER Chih-Ting Chang ; Chen-Ming Nien ; Robert Rieger AN EFFICIENT AND EFFECTIVE PERFORMANCE ESTIMATION METHOD FOR DSE Chen Lin ; Xueliang Du ; Xinwei Jiang ; Donglin Wang A SMART SURVEILLANCE SYSTEM WITH MULTIPLE PEOPLE DETECTION, TRACKING, AND BEHAVIOR ANALYSIS Chia-Jui Yang ; Ting Chou ; Fong-An Chang ; Chang Ssu-Yuan ; Jiun-In Guo DESIGN AND IMPLEMENTATION OF A DANGEROUS DRIVING BEHAVIOR ANALYSIS SYSTEM Chun-Yu Chung ; Yi-Ting Lai ; Jiun-In Guo A 70NW, 0.3V TEMPERATURE COMPENSATION VOLTAGE REFERENCE CONSISTING OF SUBTHRESHOLD MOSFETS IN 65NM CMOS TECHNOLOGY Ting-Chou Lu ; Ming-Dou Ker ; Hsiao-Wen Zan A PRECISE DECIBEL-LINEAR PROGRAMMABLE-GAIN AMPLIFIER FOR ULTRASOUND IMAGING RECEIVERS Pei-Keng Tsai ; Po-Chih Ku ; Chih-Cheng Lu ; Cheng-Ming Shih ; Liang-Hung Lu AN ANALOG FRONT-END WITH FAST MOTION ARTIFACT RECOVERY FOR BIO-SIGNAL RECORDING Yu-Ting Jhong ; Po-Chiun Huang OVERLAY-AWARE LAYOUT LEGALIZATION FOR SELF-ALIGNED DOUBLE PATTERNING LITHOGRAPHY Chong-Meng Huang ; Shao-Yun Fang TRIM MASK OPTIMIZATION FOR HYBRID MULTIPLE PATTERING LITHOGRAPHY Yin-Lu Chang ; Shao-Yun Fang A LITHOGRAPHIC MASK MANUFACTURABILITY AND PATTERN FIDELITY AWARE OPC ALGORITHM Ahmed Awad ; Atsushi Takahashi AN ENERGY-EFFICIENT NONVOLATILE MICROPROCESSOR CONSIDERING SOFTWARE- HARDWARE INTERACTION FOR ENERGY HARVESTING APPLICATIONS Tsai-Kan Chien ; Lih-Yih Chiou ; Chang-Chia Lee ; Yao-Chun Chuang ; Shien-Han Ke ; Shyh-Shyuan Sheu ; Heng-Yuan Li ; Pei-Hua Wang ; Tzu-Kun Ku ; Ming-Jinn Tsai ; Chih-I Wu HIGH PERFORMANCE VLSI ARCHITECTURE FOR 3-D DISCRETE WAVELET TRANSFORM B. K. N. Srinivasarao ; Indrajit Chakrabarti A VARIABLE-LATENCY, ULTRA-LOW-VOLTAGE RISC PROCESSOR WITH A NEW IN-SITU ERROR DETECTION AND CORRECTION TECHNIQUE Chi-Chun Lin ; Kuo-Chiang Chang ; Chih-Wei Liu TEST COVERAGE DEBUGGING FOR DESIGNS WITH TIMING EXCEPTION PATHS Kun-Han Tsai AN IR-DROP GUIDED TEST PATTERN GENERATION TECHNIQUE Li-Chen Tsai ; Jiun-Zong Li ; Yi-Tsung Lin ; Jiun-Lang Huang ; Ann Shih ; Zoe F. Conroy ON GATE FUNCTION BASED TESTS FOR SCAN DESIGNS Xijiang Lin ; Sudhakar M. Reddy THE PRESENT AND FUTURE OF MOORE'S LAW Peng Bai NEW SYSTEMS OPPORTUNITIES IN CLOUD-SCALE DATA CENTER Tzi-Cker Chiueh MORE THAN MOORE - EXPANDS THE SEMICONDUCTOR WORLD Hidemi Hank Takasu
6 MORE THAN MOORE'S LAW - SCALING WITH SILICON PHOTONICS Young-Kai Chen TREND, TECHNOLOGY AND ARCHITECTURE OF SMALL CELL IN 5G ERA Chun-Nan Liu DOHERTY TECHNIQUES FOR 5G RF AND MM-WAVE POWER AMPLIFIERS Patrick Reynaert ; Yuhe Cao ; Marco Vigilante ; Paramartha Indirayanti MIXED ANALOG-DIGITAL PULSE-WIDTH MODULATOR FOR MASSIVE-MIMO TRANSMITTERS Yannis Papananos ; Nikolaos Alexiou ; Konstantinos Galanopoulos ; David Seebacher ; Franz Dielacher ULTRA-LOW POWER SOC FOR WEARABLE & LOT Uming Ko 5G AND IOT Li Fung Chang FOR YOUR EYES ONLY? UAV AND DJI Zexiang Li Author Index
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