Rayson Bluetooth Module

Transcription

1 Rayson Bluetooth Module BC08 Class Stereo ROM Module BTM-640/645 Features Outline The module is a Max.4dBm( Class ) module. Fully Qualified Bluetooth v.0. Integrated Switched-Mode Regulator. Integrated Battery Charger. Embedded Kalimba DSP Co-Processor. Integrated 6-bit Stereo Audio CODEC 9dB SNR for DAC. CSR s latest CVC technology for narrowband and wideband voice connections including wind noise reduction. Wideband speech supported by HFP v.6 Profile and msbc codec. Multipoint HFP connection to phones for voice. Multipoint ADP connection enables a headset(adp) connection to ADP source device for music playback. Support Digital Audio Bus : PCM and I S. Support Host Interface: USB.0 or UART. SBC, MP, AAC, Faststream(BTM640), APTX(BTM645) decoder support. HSP v./ HFP v.6/ ADP v./ AVRCP v.4 Voice prompts (SPI Flash) RoHS compliant. Small outline..4 x.4 x.7mm(8m SPI Flash).4 x.4 x.9mm(64k EEPROM) Applications. Stereo Wireless Headsets. Wired stereo headsets and headphones. Portable stereo speakers. V0 0.0.

2 General Electrical Specification Absolute Maximum Ratings: Ratings Min. Max. Storage Temperature Supply Voltage (VCHG) -0.4V 5.75V Supply Voltage (VREG_ENABLE,_SENSE) -0.4V 4.V Supply Voltage (LED[:0]) -0.4V 4.4V Supply Voltage (PIO_POWER) -0.4V.6V Recommended Operating Condition: Operating Condition Operating Temperature range Supply Voltage ().7V 4.5V Supply Voltage (VCHG) 4.75V /.0 V 5.5V Supply Voltage (VREG_ENABLE,_SENSE) 0V 4.V Supply Voltage (LED[:0]).0V 4.5V Supply Voltage (PIO_POWER)*.7V.6V.8V Switch-mode Regulator.8V Switch-mode Regulator Min Typ Max Unit Input voltage () V Output voltage (V8_SMPS) V Normal Operation Transient settling time s Load current ma Current available for external use, stereo audio with 6 load (a) ma Peak conversion efficiency % Switching frequency MHz Low-power Mode, Automatically Entered in Deep Sleep Transient settling time s Load current ma Current available for external use ma Peak conversion efficiency % Switching frequency khz (a) More current available for audio loads above 6.

3 Regulator Enable VREG_ENABLE, Switching Threshold Min Typ Max Unit Rising threshold V Battery Charger Battery Charger Min Typ Max Unit Input voltage, VCHG (a) 4.75 / V (a) Reduced specification from. to Full specification > 4.75V. Trickle Charge Mode Min Typ Max Unit Charge current I trickle, as percentage of fast charge current 8 0 % V fast rising threshold V V fast rising threshold trim step size V V fast falling threshold V Fast Charge Mode Min Typ Max Unit Charge current during constant Current mode, I fast Reduced headroom charge current, As a percentage of I fast Max, headroom > 0.55V ma Min, headroom > 0.55V 0 ma Mid, headroom=0.5v % I-CTRL charge current step size ma V float threshold, calibrated V Standby Mode Min Typ Max Unit Voltage hysteresis on, V hyst mv Error Charge Mode Min Typ Max Unit Headroom (a) error rising threshold 0-50 mv Headroom (a) error threshold hysteresis 0-0 mv (a) Headroom=VCHG- External Charge Mode Min Typ Max Unit Fast charge current, I fast ma Control current into CHG_EXT 0-0 ma Voltage on CHG_EXT V External pass device h fe Sense voltage, between _SENSE and at maximum current mv (a) In the external mode, the battery charger meets all the previous charger electrical characteristics and the additional or superseded electrical characteristics are listed in this table. Stereo Codec: Analogue to Digital Converter Analogue to Digital Converter Parameter Conditions Min Typ Max Unit

4 Resolution Bits Input Sample Rate, Fsample khz SNR THD+N fin = khz B/W = 0Hz Fsample/ (0kHz max) A-Weighted THD+N < %.6Vpk-pk input fin = khz B/W = 0Hz Fsample/ (0kHz max).6vpk-pk input F sample 8kHz db 6kHz db khz db 44.kHz db 48kHz db F sample 8kHz % 48kHz % Digital gain Digital gain resolution = / db Analogue gain Pre-amplifier setting = 0dB, 9dB, db or0db Analogue setting = -db to db in db steps db Stereo separation (crosstalk) db Stereo Codec: Digital to Analogue Converter Digital to Analogue Converter Parameter Conditions Min Typ Max Unit Resolution Bits Output Sample Rate, Fsample khz fin = khz Fsample Load B/W = 0Hz 0kHz 48kHz 00k db SNR A-Weighted THD+N < 0.% 48kHz db 0dBFS input 48kHz db Fsample Load 8kHz 00k % fin = khz 8kHz % THD+N B/W = 0Hz 0kHz 8kHz % 0dBFS input 48kHz 00k % 48kHz % 48kHz % Digital Gain Digital Gain Resolution = / db

5 Analogue Gain Analogue Gain Resolution = db db Stereo separation (crosstalk) db Digital Digital Terminals Min Typ Max Unit Input Voltage V IL input logic level low V V IH input logic level high 0.7xPIO_POWER - PIO_POWER+0.4 V Tr/Tf ns Output Voltage V OL output logic level low, I OL = 4.0mA V V IH output logic level high, I OH = -0.4mA 0.75xPIO_POWER - - V Tr/Tf ns Input and Tristate Currents Strong pull-up ua Strong pull-down ua Weak pull-up ua Weak pull-down ua C I input Capacitance pf LED Driver Pads LED Driver Pads Min Typ Max Unit Current, I PAD High impedance state A Current sink state ma LED pad voltage, V PAD I PAD = 0mA V LED pad resistance V PAD < 0.5V V OL output logic level low (a) V V OH output logic level high (a) V V IL input logic level low V V IH input logic level high V (a) LED output port is open-drain and requires a pull-up Auxiliary ADC Auxiliary ADC Min Typ Max Unit Resolution Bits Input voltage range(a) V Accuracy INL - - LSB (Guaranteed monotonic) DNL 0 - LSB Offset - - LSB Gain error %

6 Input bandwidth khz Conversion time s Sample rate(b) Samples/s (a) LSB size = VDD_AUX/0 (b) The auxiliary ADC is accessed through a VM function. The sample rate given is achieved as part of this function. Auxiliary DAC Auxiliary DAC Min Typ Max Unit Resolution Bits Supply voltage, VDD_DAC V Output voltage range V Full-scale output voltage V LSB size mv Offset mv Integral non-linearity - 0 LSB Settling time(a) ns (a) The settling time does not include any capacitive load Power Consumption DUT Role Connection Packet Type Packet Size Average Unit Current Slave SCO HV 0 TBD ma Slave esco EV 0 TBD ma Slave esco EV 60 TBD ma Slave esco EV 0 TBD ma Slave SCO -mic CVC HV 0 TBD ma Slave esco -mic CVC EV 60 TBD ma Slave esco -mic CVC EV 0 TBD ma Stereo high quality: Slave Slave SBC 50kbps No sniff Stereo high quality: SBC 50kbps Sniff TBD TBD TBD ma TBD TBD TBD ma

7 Slave Stereo high quality: MP 8kbps TBD TBD TBD ma No sniff Slave Stereo high quality: MP 8kbps Sniff TBD TBD TBD ma Slave ACL Sniff = 00ms - - TBD ma Slave ACL Sniff = 500ms - - TBD ma Slave ACL Sniff = 80ms - - TBD ma Master SCO HV 0 TBD ma Master esco EV 0 TBD ma Master esco EV 60 TBD ma Master esco EV 0 TBD ma Master SCO -mic CVC HV 0 TBD ma Master esco -mic CVC EV 60 TBD ma Master esco -mic CVC EV 0 TBD ma Master ACL Sniff = 00ms - - TBD ma Master ACL Sniff = 500ms - - TBD ma Master ACL Sniff = 80ms - - TBD ma Note: Current consumption values are taken with: pin =.7V RF TX power set to 0dBm No RF retransmissions in case of esco Microphones and speakers disconnected, with internal microphone bias circuit set to minimum current level Audio gateway transmits silence when SCO/eSCO channel is open LEDs disconnected

8 Block Diagram RF Specification: Temperature=+0 Transmitter Min Typ Max Bluetooth Unit Specification Maximum RF transmit power - TBD - -6 to +4 dbm RF power control range - TBD - db RF power range control resolution - TBD - - db 0dB bandwidth for modulated carrier - TBD - khz Adjacent channel transmit power F = F0 ± - TBD - -0 dbm MHz Adjacent channel transmit power F = F0 ± - TBD dbm MHz Adjacent channel transmit power F = F0 ± - TBD dbm > MHz - TBD - 40<favg<75 khz

9 - TBD - 5 khz - TBD - Initial carrier frequency tolerance - TBD - ±75 khz Drift Rate - TBD - Drift (single slot packet) - TBD - khz Drift (five slot packet) - TBD - khz nd Harmonic Content - TBD - -0 dbm rd Harmonic Content - TBD - -0 dbm Receiver Freque ncy (GHz) Min Typ Max Bluetooth Specificatio n Unit Sensitivity at 0.% BER.40 - TBD dbm for all packet types.44 - TBD TBD - Maximum received signal at 0.% BER - TBD -0 dbm C/I co-channel - TBD - db Adjacent channel selectivity C/I - TBD - db F = F0 + MHz Adjacent channel selectivity C/I - TBD - db F = F0 - MHz Adjacent channel selectivity C/I - TBD - -0 db F = F0 + MHz Adjacent channel selectivity C/I - TBD - -0 db F = F0 - MHz Adjacent channel selectivity C/I - TBD db F = F0 - MHz Adjacent channel selectivity C/I - TBD db F = F0 + 5MHz Adjacent channel selectivity C/I - TBD - -9 db F = FImage Maximum level of intermodulation - TBD - -9 dbm interferers Spurious output level - TBD - dbm/ Hz

10 BTM-640/645 Pin Functions No. Pin Name Pin Type Supply Domain Pin Description SPKR_R_N Analogue VDD_AUDIO_DRV (V8_SMPS) Speaker output negative, right SPKR_R_P Analogue VDD_AUDIO_DRV (V8_SMPS) Speaker output positive, right SPKR_L_N Analogue VDD_AUDIO_DRV (V8_SMPS) Speaker output negative, left 4 SPKR_L_P Analogue VDD_AUDIO_DRV (V8_SMPS) Speaker output positive, left 5 Common Ground 6. RF_IO Analogue Connect to 50 ohm Antenna (RF Signal) 7. Common Ground 8. Common Ground 9. Common Ground 0. AIO0 Bi-directional VDD_AUX(.5V) Analogue programmable input/output line. PIO6 Bi-directional PIO_POWER Programmable input/output line. PIO7 Bi-directional PIO_POWER Programmable input/output line. RST# Input with strong PIO_POWER Reset if low. Pull low for pull-up minimum 5ms to cause a reset 4 LED0 Open drain PIO_POWER output LED Driver 5 LED Open drain PIO_POWER output LED Driver Bi-directional PIO_POWER Programmable input/output line Altemative functions: 6. PIO4 SPI_CSB:chip select for SPI, active low PCM_SYNC: PCM synchronous data sync Bi-directional PIO_POWER Programmable input/output line Altemative functions: 7. PIO SPI_MOSI:SPI data input PCM_IN: PCM synchronous data input 8. PIO5 Bi-directional PIO_POWER Programmable input/output line Altemative functions:

11 SPI_CLK:SPI clock PCM_CLK: PCM synchronous data clock Bi-directional PIO_POWER Programmable input/output line Altemative functions: 9. PIO SPI_MISO:SPI data output PCM_OUT: PCM synchronous data output 0. PIO_POWER VDD Positive supply for PIO. VREG_ENABLE Analogue Regulator enable input SPI/PCM# select input: Input with weak. SPI/PCM# PIO_POWER 0=PCM/PIO interface pull-down =SPI. VCHG Charger input Lithium ion/polymer battery charger input 4. Common Ground 5. CHG_EXT External charger control. Otherwise leave unconnected. 6. _SENSE Battery charger sense input Lithium ion/polymer battery 7. switch-mode regulator Battery terminal positive terminal. Battery +ve charger output and input to 8. V8_SMPS VDD V8 Output 9. PIO6 Bi-directional PIO_POWER Programmable input/output line 0. PIO7 Bi-directional PIO_POWER Programmable input/output line. PIO8 Bi-directional PIO_POWER Programmable input/output line. PIO9 Bi-directional PIO_POWER Programmable input/output line. PIO Bi-directional PIO_POWER Programmable input/output line 4. PIO0 Bi-directional PIO_POWER Programmable input/output line 5. PIO9 Bi-directional PIO_POWER Programmable input/output line 6. Common Ground 7. PIO0 Bi-directional PIO_POWER Programmable input/output line 8. PIO Bi-directional PIO_POWER Programmable input/output line 9. PIO8 Bi-directional PIO_POWER Programmable input/output line 40. USB_DN Bi-directional V_USB USB data minus 4. USB_DP Bi-directional V_USB USB data plus 4. LED Open drain PIO_POWER output LED Driver 4 MIC_BIAS Analogue /V_USB Microphone bias 44. MIC_BN Analogue VDD_AUDIO(.5V) Microphone input negative,

12 right 45. MIC_BP Analogue VDD_AUDIO(.5V) Microphone input positive, right 46. MIC_AN Analogue VDD_AUDIO(.5V) Microphone input negative, left 47. MIC_AP Analogue VDD_AUDIO(.5V) Microphone input positive, left 48. Common Ground

13 . Serial Interface. USB Interface BTM-640/650 has a full-speed (Mbps) USB interface for communicating with other compatible digital devices. The USB interface on BTM-640/645 acts as a USB peripheral, responding to requests from a master host controller. BTM-640/645 contains internal USB termination resistors and requires no external resistor matching. BTM-640/645 supports the Universal Serial Bus Specification, Revision v.0 (USB v.0 Specification), supports USB standard charger detection and fully supports the USB Battery Charging Specification, available from For more information on how to integrate the USB interface on BTM-640/645 see the Bluetooth and USB Design Considerations Application Note. As well as describing USB basics and architecture, the application note describes: Power distribution for high and low bus-powered configurations Power distribution for self-powered configuration, which includes USB VBUS monitoring USB enumeration Electrical design guidelines for the power supply and data lines, as well as PCB tracks and the effects of ferrite beads USB suspend modes and Bluetooth low-power modes: Global suspend Selective suspend, includes remote wake Wake on Bluetooth, includes permitted devices and set-up prior to selective suspend Suspend mode current draw PIO status in suspend mode Resume, detach and wake PIOs Battery charging from USB, which describes dead battery provision, charge currents, charging in suspend modes and USB VBUS voltage consideration USB termination when interface is not in use Internal modules, certification and non-specification compliant operation. Programming and Debug Interface BTM-640/645 provides a debug SPI interface for programming, configuring (PS Keys) and debugging the BTM640/645. Access to this interface is required in production. Ensure the 4 SPI signals and the SPI/PCM# line are brought out to either test points or a header. To use the SPI interface, the SPI/PCM# line requires the option of being pulled high externally... Multi-slave Operation Avoid connecting BTM-640/645 in a multi-slave arrangement by simple parallel connection of slave MISO lines. When BTM640/645 is deselected (SPI_CS# = ), the SPI_MISO line does not float. Instead, BTM-640/645 outputs 0 if the processor is running or if it is stopped.. interfaces. Analogue I/O Ports, AIO

14 BTM-640/645 has general-purpose analogue interface pin, AIO[0]. Typically, this connects to a thermistor for battery pack temperature measurements during charge control.. LED Drivers BTM-640/645 includes a -pad synchronised PWM LED driver for driving RGB LEDs for producing a wide range of colours. All LEDs are controlled by firmware. The terminals are open-drain outputs, so the LED must be connected from a positive supply rail to the pad in series with a current-limiting resistor. Figure.: LED Equivalent Circuit From Figure. it is possible to derive Equation. to calculate ILED. If a known value of current is required through the LED to give a specific luminous intensity, then the value of RLED is calculated. Equation.: LED Current For the LED pads to act as resistance, the external series resistor, RLED, needs to be such that the voltage drop across it, VR, keeps VPAD below 0.5V. Equation. also applies. VDD = VF + VR + VPAD Equation.: LED PAD Voltage Note: The LED current adds to the overall current. Conservative LED selection extends battery life.. Power Control and Regulation. Voltage Regulator Enable When using the integrated regulators the voltage regulator enable pin, VREG_ENABLE, enables the BTM-640/645 and the following regulators:.8v switch-mode regulator.5v switch-mode regulator Low-voltage VDD_DIG linear regulator Low-voltage VDD_AUX linear regulator The VREG_ENABLE pin is active high. BTM-640/645 boots-up when the voltage regulator enable pin is pulled high, enabling the regulators. The firmware

15 then latches the regulators on, it is then permitted to release the voltage regulator enable pin. The status of the VREGENABLE pin is available to firmware through an internal connection. VREGENABLE also works as an input line.. Reset, RST# BTM-640/645 is reset from several sources: RST# pin Power-on reset USB charger attach reset Software configured watchdog timer The RST# pin is an active low reset and is internally filtered using the internal low frequency clock oscillator. Rayson recommends applying RST# for a period >5ms. At reset the digital I/O pins are set to inputs for bidirectional pins and outputs are set to tristate.. Digital Pin States on Reset Table.. shows the pin states of BTM-640/645 on reset. Pin Name / Group I/O Type Full Chip Reset USB_DP Digital bidirectional N/A USB_DN Digital bidirectional N/A PIO[0] Digital bidirectional PUS PIO[] Digital bidirectional PUS PIO[] Digital bidirectional PDW PIO[] Digital bidirectional PDW PIO[4] Digital bidirectional PDW PIO[5] Digital bidirectional PDW PIO[6] Digital bidirectional PDS PIO[7] Digital bidirectional PDS PIO[8] Digital bidirectional PUS PIO[9] Digital bidirectional PDS PIO[6] Digital bidirectional PUS PIO[7] Digital bidirectional PDS PIO[8] Digital bidirectional PDW PIO[9] Digital bidirectional PDW PIO[0] Digital bidirectional PDW PIO[] Digital bidirectional PDW Table..: Pin States on Reset Note: PUS = Strong pull-up PDS = Strong pull-down PUW = Weak pull-up PDW = Weak pull-down

16 4. Battery Charger 4. Battery Charger hardware Operating Modes The battery charger hardware is controlled by the VM. The battery charger has 5 modes: The battery charger operating mode is determined by the battery voltage and current. The internal charger circuit can provide up to 00mA of charge current, for currents higher than this the BTM640/BTM645 can control an external pass transistor 4. External Mode The external mode is for charging higher capacity batteries using an external pass device. The current is controlled by sinking a varying current into the CHG_EXT pin, and the current is determined by measuring the voltage drop across a resistor, Rsense, connected in series with the external pass device, see Figure 4... The voltage drop is determined by looking at the difference between the _SENSE and pins. The voltage drop across Rsense is typically 00mV. The value of the external series resistor determines the charger current. This current can be trimmed with a PS Key. In Figure 4.., R (0m ) and C (4.7 F) form a RC snubber that is required to maintain stability across all battery ESRs. The battery ESR must be <.0 Figure 4..: Battery Charger External Mode Typical Configuration

17 Figure 4..: Optional Ancilliary Circuits In Figure 4.., Optional fast charge,400m

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19 4 RSTB PIO8 D PIO R6 K0 STAR 4u7 D SW6 VOL- Low Reset PIO7 R7 K0 AMP_ V Power Optional Ancilliary Circuits Keys MIC_AN MIC_AP MIC_BIAS BTM640_BTM645 R 0805 package R4 060 package Q R R4 VBUS BCX5 00mR/%/ mR/%/0805 Option Fast Charge 400mR = 500mA Connect _SENSE to if Not Using This Circuit J PIO6 C C MIC AMP MIC_BN MIC_BP SPKR_B_N SPKR_B_P P RINP 5 B C6 B SPKR_A_P SPKR_A_N High for SPI Low for PCM USB / Charger Interface SW7 R9 VREG_ENABLE PIO_POWER C4 47p 0k A A LED PIO_POWER ON/OFF SPI_PCMB_SEL Title <Title> Battery Temperature Sensor USB_DN USB_DP BTM640/BTM645 Rayson Size Document Number Rev Custom <Doc> <RevCode> Date: Tuesday, February, 0 Sheet of LED0 LED LED PIO9 PIO0 SW MFB PIO_POWER SW FWB CHG_EXT _SENSE R8 0R L 5nH U L XC609FMRN V 0R Vin Vout 5 C4 V8_SMPS C C5 CE BTP 4 C6 C7 u0 0uF u0 0.u 0.u VBUS AIO0 V8_SMPS AUDIO_OUT_R AUDIO_OUT_L MISO CSB MOSI CLK SPKR_B_N SPKR_B_P V8_SMPS _SENSE CHG_EXT VBUS RSTB LED0 LED CSB MOSI CLK MISO PIO_POWER VREG_ENABLE SPI_PCMB_SEL MIC_AP MIC_AN MIC_BP MIC_BN MIC_BIAS LED USB_DP USB_DN STAR SP R K0 SW4 REW SW5 VOL+ R0 0R C u C 0uF SP C 0.u C8 LUMBURG AMP_ V C7 u0 R 0R U4 ROUT PVDD SVSS PVSS PAD S SVDD SVDD LOUT R K C 47p MAX97AETE R0 0k 0k R4 RINN 4 SHDN LINP LINN C8 u0 V C5 DNI R4 k R 0R C4 u C5 u C0 DNI C9 5p C DNI R7 K5 R8 K8 AIO0 PIO6 SPKR_A_N U PIO0 SPKR_A_P 4 PIO 5 BTM640/BTM645 PIO9 6 PIO8 7 PIO VBUS V8_SMPS VBUS V C4 0u SPRK_RN SPRK_RP SPKR_LN SPKR_LP RF_IO AIO_0 PIO6 PIO7 PIO9 PIO0 PIO PIO9 PIO8 PIO7 PIO6 V8_SMPS _SENSE CHG_EXT RST# LED_0 LED_ PIO4 PIO PIO5 PIO PIO_POWER VREG_ENABLE SPI/PCMB# VCHG PIO0 PIO PIO8 USB_DN USB_DP LED_ MIC_BIAS MIC_BN MIC_BP MIC_AN MIC_AP J LUMBURG SW L 5nH R K0 R5 K0 C0 5p R9 K C DNI J C9 u Q FDV0N S D TH 0K V R DNI C0 u0 L4 5N L5 5N C7 5p C 47p C9 47p R0 0k R k C u C6 u E ANTENNA 4 5 J4 4 CON D LN040 R 0R R5 DNI C 0.u V V8_SMPS R7 DNI R9 0R PIO_POWER G R5 0k 4 5 U USB mini VBUS D- D+ ID 6 7 J6 PHONOJACK STEREO-4 4 C u0 u0 STAR SP R 0R R6 k R8 k C u C8 u R6 K0 C5 00nF