Design Consideration of the Active-Clamp Forward Converter With Current Mode Control During Large-Signal Transient

Transcription

1 958 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 18, NO. 4, JULY 2003 Design Consideration of the Active-Clamp Forward Converter With Current Mode Control During Large-Signal Transient Qiong M. Li, Member, IEEE, and Fred C. Lee, Fellow, IEEE Abstract The design issues of the active-clamp forward converter circuit with peak current mode control in small signal stability and large-signal transients are discussed. A design procedure is provided to solve circuit issues under these conditions. It is the first time that with the aid of simulation, we are able to optimize the circuit design of the active-clamp forward converter for large-signal transient behaviors. Index Terms Active-clamp, forward converter, large-signal transient. I. INTRODUCTION THE forward converter with the active-clamp reset offers many advantages over the forward converter with other transformer reset methods [1]. However, during the large-signal transients, the maximum magnetizing current of the transformer and the peak voltage of the primary switch are strongly affected by the active-clamp circuit dynamics. Although some design issues have been discussed [2] [6], the design of active-clamp forward converter is still based on steady state performance. The voltage and current stresses of the circuit are very hard to predict during the large-signal transient and under abnormal conditions due to the nonlinearity of the circuit, and the conflict effect of the different parameters makes it even harder to generate a design procedure [6], [7]. This paper focuses on design issues related to the active-clamp reset circuit. The design procedures of the forward converter, such as L, C output filter design and current control loop design have been discussed in many literatures such as in [8] [10]. A design procedure for the active-clamp forward circuit is proposed by using design curves that are generated by running a large amount of simulations. The design procedure will cover the problems related to the large-signal transient as well as to the small-signal stability. It shows that the dynamic performance and the robustness of the circuit can be improved by using this approach. It is the first time that with the aid of simulation, we are able to optimize the circuit design of the active-clamp forward converter for the large-signal transient behaviors. An active-clamp forward converter circuit with peak current mode control is used as an example. Fig. 1. Fig. 2. Active-clamp forward converter circuit diagram. Active-clamp circuit problems during large-signal transient. Manuscript received October 6, 2000; revised February 14, Recommended by Associate Editor K. Smedley. Q. M. Li is with the Philips Research USA, Briarcliff Manor, NY USA. F. C. Lee is with the Center for Power Electronics Systems, Virginia Polytechnic Institute and State University, Blacksburg, VA USA. Digital Object Identifier /TPEL Fig. 3. Stability problem due to the resonant network of the active-clamp reset circuit. II. DESIGN ISSUES OF THE ACTIVE-CLAMP CIRCUIT The active-clamp forward converter circuit diagram is shown in Fig. 1. Fig. 2 shows the load transient waveforms of the ac /03$ IEEE

2 LI AND LEE: DESIGN CONSIDERATION OF THE ACTIVE-CLAMP FORWARD CONVERTER 959 Fig. 4. Large-signal response waveform at Vin = 36 V, Io from no load to full load then to no load transient. Load step slew rate is 1 A/us: (a) measurement and (b) simulation. tive-clamp circuit, where is the output voltage, is the voltage across the main switch, and is the magnetizing current of the transformer. From Fig. 2 we can see that the maximum voltage of the main switch and the maximum magnetizing current of the transformer during transient are much larger than that at the steady state. These can cause circuit problems such as voltage stresses, transformer saturation, and the diode reverse recovery problem [2], [3], [6], which are marked as dotted circles in Fig. 2. Besides the large-signal transient problems, circuit can have stability problem due to the interaction of the resonant network of the active-clamp-reset circuit [4]. Fig. 3 shows small-signal transfer function of the loop gain at V. The phase margin of the loop gain at crossover frequency is negative due to the additional pole in the active-clamp-reset circuit near the resonant frequency. This paper is going to demonstrate how to design the circuit to solve these problems. III. CIRCUIT UNDER WORST CASE CONDITION The fist step before we start the design is to find the worst case condition during the large-signal transient, so we can design the circuit under the worst case condition. In a current-mode-controlled circuit, the output voltage is not sensitive to the line change because of the feed-forward effect in the control [7], [8]. The same is true for the stresses of voltage and current in the active-clamp circuit. Simulation results also verified that the voltage and current stresses in the active-clamp circuit is not a problem during line step changes in a current-mode-controlled circuit [7]. While in a load transient, the worst condition happens from no load to full load change at low line condition [6], [7]. The main reason is that the clamp capacitor voltage is a function of the duty cycle where n is the transformer turns ratio. At low line, circuit has the largest duty cycle in steady state. While a no load to full load change drives the duty cycle even larger during the transient, (1) most of the time to the maximum duty cycle, which is limited by the controller chip. A virtual prototype test procedure is used to detect the circuit worst case condition by simulating the circuit dynamic performance under different lines, loads, and the abnormal conditions [7]. From the simulation, it shows that the worst condition occurs when the circuit has a large load transient from no load to full load at low line. In order to verify the accuracy of simulation, a circuit prototype was built to compare the circuit dynamic performance. An active-clamp forward converter circuit with peak current mode control is used as an example to demonstrate the design process. The circuit has input voltage V and full load 30 A. The switching frequency is 500 khz and the duty cycle limit of the controller chip is The control bandwidth of the circuit is 14 khz, the transformer turns ratio is 4, the active clamp circuit is 80 uh, and is 0.01 uf. Fig. 4 shows the measured and simulated large-signal responses at V, Io from no load to full load to no load transient. The full load is 30 A and the load step slew rate is 1 A/us. Fig. 4(a) is the measurement and Fig. 4(b) is the simulation result. Fig. 5 is the zoomed-in waveforms of Fig. 4. Fig. 5(a) is the measured waveform from no load to full load transient. Fig. 5(b) is the simulated waveform from no load to full load transient. Fig. 5(c) is the measured waveform from full load to no load transient. Fig. 5(d) is the simulated waveform from full load to no load transient. Comparing the measurement and simulation, it shows that the simulation is accurate enough to provide the design information and predict the dynamic behavior of the system. IV. DESIGN PROCEDURE OF THE ACTIVE-CLAMP CIRCUIT Although it is possible to adjust the circuit parameters by trials and errors to fix the problems, the problem s solution is not straightforward. It may require a lot of time and effort but still not come out a robust design, since these parameters are not independent parameters and involve different circuit design issues.

3 960 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 18, NO. 4, JULY 2003 Fig. 5. Zoomed-in waveforms of Fig. 4 from no load to full and then full load to no load transient. (a) Measured waveform of no load to full load transient. (b) Simulated waveform of no load to full load transient. (c) Measured waveform of full load to no load transient. (d) Simulated waveform of full load to no load transient. This section will demonstrate how to generate design information and optimize the design parameters related to these design issues. The design parameters discussed here are the magnetizing inductance of the transformer, the clamp capacitance, the control bandwidth, and the maximum duty cycle limit Dmax. It is recommended to have an initial design of the circuit as a conventional forward converter before the active-clamp reset circuit design, then to follow the design procedure proposed here to prevent problems related to active-clamp circuit. The design process focuses on solving the potential problems in the circuit: voltage stress of the main switch, transformer core saturation, diode reverse recovery of the active-clamp switch, small-signal instability due to the active-clamp resonant network. A. Normalization The normalized peak voltage and peak current values will be used in the design curve. The normalized switch voltage is and the normalized magnetizing current is. The x-axis of the design curve uses resonant frequency,, as a parameter, and is the characteristic impedance B. Design Constraints There are four design criteria: the voltage stress of the main switch, the transformer saturation, the reverse recovery problem of the body diode of the active clamp switch, and the smallsignal stability problem. 1) Design constraint 1: switch voltage stress The design constraint for the switch voltage stress is (2) (3) peak rating (4)

4 LI AND LEE: DESIGN CONSIDERATION OF THE ACTIVE-CLAMP FORWARD CONVERTER 961 Fig. 6. Relation of the saturation flux to the saturation magnetizing current. Fig. 7. Transformer saturation area. Where, peak is the peak voltage during the transient, rating is the device voltage rating of the main switch. If the voltage stress is unknown, which is the case in the design sometime, we can eliminate the voltage overstress restriction. 2) Design constraint 2: small signal stability Studies show that the active-clamp reset circuit introduces an additional pair of moving pole and zero in the loop gain [5], [11]. The frequency,, of the moving pole is a function of the resonant frequency In order to guarantee a stable operation in the circuit, the moving frequency,, has to be designed away from the crossover frequency (e.g., two times larger). The smallest happens at the maximum duty cycle, so the resonant frequency of the active-clamp circuit should meet the following equation in order to have a stable system and not affect the phase margin where is the duty cycle limit value of the controller chip, is the control bandwidth. 3) Design constraint 3: transformer saturation Fig. 6 shows the relation between the flux and the magnetizing current, where, is the effective cross sectional area of the core, is the magnetizing current. From Fig. 6, we can get (5) (6) (7) We can rewrite the saturating magnetizing current into The design constraint for the transformer saturation is (8) (9) The design constraint for the transformer saturation is shown as the shaded area in Fig. 7. It is a straight line in the normalized design curve. Fig. 8. Diode reverse recovery problem area. 4) Design constraint 4: diode reverse recovery problem The magnetizing current to prevent the diode from reverse recovery problem is where, The ripple current can be written as (10) (11) (12) The diode reverse recovery problem area is shown as in Fig. 8. It is a straight line in the normalized design curve. According to four design constraints, we can draw the feasible operating regions for voltage and magnetizing current as shown in Fig. 9. If the voltage stress is unknown, which is the case in the design sometime, we can ignore the voltage overstress area in Fig. 9(a) to get an easier start. After defining the design regions to meet other constraints, the circuit parameters with smallest voltage stress value can be selected from the design curve. C. Generating Design Curves The worst case happens at low line and load from low to high transient. In this example, Vin is 36 V, and Io changes from 0 A to 30 A. A set of design curves is generated by varying and values with a fixed control bandwidth, 14 khz, and

5 962 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 18, NO. 4, JULY 2003 (a) Fig. 10. Design curve of the normalized peak switch voltage versus f. (b) Fig. 9. Feasible operating regions for voltage and magnetizing current. (a) Design area for normalized switch voltage curve. (b) Design area for normalized magnetizing current curve. maximum duty cycle limit, Each single simulation generates one point in the voltage design curve and one point in the magnetizing current curve. The normalized design curve for peak voltage and magnetizing current are shown in Fig. 10 and Fig. 11, respectively. The shaded areas are the design prohibited area. The total simulation CPU time is only 9 minutes by using an adequate simulation and modeling approach [7]. D. Feasible and to Meet the Design Constraints After we generate the design curves with design constraints, the feasible and to meet all the design criteria can be easily determined. Assuming the device rating of the main switch is 180 V, so the normalized boundary of the voltage stress is 5 when V. When the control bandwidth, khz, and maximum duty cycle limit,, the boundary of the resonant frequency for small-signal stability is 112 khz. The feasible and can be determined by three steps. 1) Find the desired parameter ranges for and in peakvoltage design curves. Fig. 10 is the peak-voltage design curves with 14 khz and These is a big dot in Fig. 10, which corresponds to the original design, uh and uf. The maximum voltage is about 200 V, so the original design exceeds the 180 V voltage rating of the switch under worst case condition. Fig. 11. Design curve of normalized peak magnetizing current versus f. The dotted lines covered area is the desired design area to meet voltage stress limitation and small signal stable criterion in the normalized peak switch voltage versus curves. We can see that only the curve at uh meets the constraints when is at 100 khz to 480 khz range. 2) Within the defined ranges for and in step 1, we can find the desired ranges for and that also meet the magnetizing current constraints. Fig. 11 is the peak magnetizing-current design curves with 14 khz and These is a big dot in Fig. 11, which corresponds to the original design, uh and uf. It shows that the original design has diode reverse recovery problem and is at the boundary of the transformer saturation. From the design curves, we can see that has to be larger than 530 khz in order to meet magnetizing current constrains. So there are no feasible parameters available within the desired areas from step1. It also means that there is no feasible and can meet all the design constraints in the previous circuit condition.

6 LI AND LEE: DESIGN CONSIDERATION OF THE ACTIVE-CLAMP FORWARD CONVERTER 963 Fig. 12. Normalized voltage design curve reduced maximum duty cycle limit. The Dlim is reduced from 0.75 to 0.7. The design area to meet voltage stress limitation and small signal stable criteria is shown in the dotted area. 3) If we find the desired ranges for and from step 1 and 2, can be calculated by (13) Within the desired parameter range, a smaller, thus a larger is preferred to reduce the voltage and current stresses. V. DESIGN TRADE-OFF Previous example shows that there is no adequate and to meet all the design criteria. The design curve of normalized peak switch voltage versus (Fig. 10) requires khz khz, while the design curve of normalized peak magnetizing current versus (Fig. 11) requires khz with uh. There is not any to meet both conditions. There are several design trade-off and solutions to solve the problem. A. Design Trade-Off 1: Increasing Device Rating From Fig. 10 and Fig. 11, we see that if we do not restrict the device voltage rating to 180 V, voltage constrain becomes: khz, so there is a small area in Fig. 11 which can meet all the design criteria: khz. The design result with this trade-off will be uh and khz, which gives any smaller than 4.5 nf to meet the requirement. The disadvantages of this solution are the higher voltage rating device and the high ripple current of the magnetizing current due to a much smaller. It is worth of mentioning that a very small magnetizing inductance could have a high ripple of the magnetizing current which will increase the loss of the circuit and may affect the main converter operation if the ripple of the magnetizing current is not negligible to the reflected load. B. Design Trade-Off 2: Getting Rid of the Constraint of the Body Diode Reverse Recovery From Fig. 11, we see that the diode reverse recovery constraint is the hardest one to meet in the parameter design. The de- Fig. 13. Normalized magnetizing current design curve with reduced maximum duty cycle limit. The Dlim is reduced from 0.75 to 0.7. The design area without transformer saturation and diode reverse recovery problem shows in the dotted line. sign is more flexible without this constraint. This can be done by connecting a Schottky diode in series with the auxiliary switch to block the conduction of the body diode, and then to connect a fast-recovery anti-parallel diode around the series connection of the Schottky and the auxiliary switch [2]. The disadvantage is the additional components to increase the cost of the circuit. With this trade-off, we relaxed the second condition (magnetizing current). For example, if we select uh, we get khz from Fig. 11. The final solution will be khz khz, thus nf nf. C. Design Trade-Off 3: Decreasing Control Bandwidth A smaller bandwidth in the design can reduce the peak voltage and magnetizing current during load transients. The disadvantage is a slower recovery from the transient in the output voltage of the main converter. For example, if we reduced the bandwidth from 14 khz to 8 khz, one of the design result can be uh and nf. D. Design Trade-Off 4: Reducing Maximum Duty Cycle Limit Value The voltage and current stresses can also be reduced by reducing the maximum duty cycle limit value. Similar to solution 3, the disadvantage is a slower recovery from transient in the output voltage of the main converter. One of the design result is uh and nf. The next section will show the design curves and result using this trade-off as an example. E. Circuit Redesign by Using Trade-Off 4 Fig. 12 and Fig. 13 shows the normalized voltage design curve with reduced maximum duty cycle limit. The maximum duty cycle limit is reduced from 0.75 to 0.7. The design curve of normalized peak switch voltage versus (Fig. 12) requires khz, while the design curve of normalized peak magnetizing current versus (Fig. 13) requires khz when we select uh. So one of the design result is uh, is less than 5.2 nf. A smaller has a larger voltage stress,

7 964 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 18, NO. 4, JULY 2003 Fig. 14. Design verification of dc bias of magnetizing current of transformer at steady state. (a) Fig. 15. Design verification of the small signal analysis. (b) Fig. 16. Design verification of the large-signal transient analysis with worst case: Vin = 36 V, Io = 0 to 30 A. (a) Waveforms with original design and (b) waveforms after design modification. but more design margin without saturation and diode reverse recovery problem. VI. VALIDATION OF THE DESIGN BY VIRTUAL PROTOTYPE TEST This section shows the comparisons between the original circuit problems and the circuit behavior after the final design modification. The circuit parameters are modified by reducing the maximum duty cycle limit from 0.75 to 0.7 and magnetizing inductance from 80 uh to 40 uh. The clamp capacitance is 5 nf. Fig. 14 shows design verification of dc bias of magnetizing current of transformer. The dc bias of the magnetizing current does not shown any problems since the magnetizing current ripple is about 800 ma. Fig. 15 shows the design verification of the small signal analysis under worst case condition. The resonant frequency of the active-clamp circuit has been pushed high enough and does not interfere with the crossover frequency of the loop gain. Fig. 16 shows the design verification of the large-signal transient analysis under worst case: V, to 30 A. Fig. 16(a) shows the waveforms with original design. Fig. 16(b) shows the waveforms after design modification. The original circuit problems during large-signal transient are solved. VII. CONCLUSION The design issues of the active-clamp forward converter circuit with peak current mode control in small signal stability and large-signal transients are discussed. A design procedure is proposed to solve design issues. The circuit performances of the power supply system design are improved by redesign the active-clamp reset circuit. It is the first time that with the aid of the virtual prototype, we are able to optimize the circuit design of the active-clamp forward converter for large-signal transient behaviors. REFERENCES [1] P. Vinciarelli, Optimal resetting of the transformer s core in single ended forward converters, U.S. Patent , Apr [2] B. Carsten, Design techniques for transformer active reset circuits at high frequencies and power levels, in Proc. Conf. High Freq. Power Conv., 1990, pp [3] D. Dalal and L. Wofford, Novel control IC for single-ended active clamp converters, in Proc. Conf. High Freq. Power Conv., 1995, pp [4] Q. Li, F. C. Lee, and M. M. Jovanovic, Design considerations of transformer DC bias of forward converter with active-clamp reset, in Proc. IEEE APEC, 1999, pp [5] A. Fontan, S. Ollero, E. de la Cruz, and J. Sebastian, Peak current mode control applied to the forward converter with active clamp, in IEEE PESC Rec., 1998, pp [6] Q. Li, F. C. Lee, and M. M. Jovanovic, Large-signal transient analysis of forward converter with active-clamp reset, IEEE Trans. Power Electron., vol. 17, pp , Jan

8 LI AND LEE: DESIGN CONSIDERATION OF THE ACTIVE-CLAMP FORWARD CONVERTER 965 [7] Q. Li, Developing modeling and simulation methodology for virtual prototype power supply system, Ph.D. dissertation, VPI&SU, Blacksburg, VA, Mar [8] R. W.Robert W. Erickson and D.Dragan Maksimovic, Fundamentals of Power Electronics, 2nd ed. Boston, MA: Kluwer, [9] R. B. Ridley, Secondary LC filter analysis and design techniques for current-mode-controlled converters, IEEE Trans. Power Electron., vol. PE-3, pp , Oct [10] F. C. Lee, Y. Yu, and M. F. Mahmoud, A unified analysis and design procedure for the standardized control module for DC-DC switching regulators, in IEEE PESC Rec., 1980, pp [11] G. Stojcic, F. C. Lee, and S. Hiti, Small-signal characterization of active-clamp PWM converters, in Proc. Conf. High Freq. Power Conv., 1996, pp Qiong M. Li (S 93 M 99) received the B.S. and M.S. degrees in electrical engineering from Xian Jiaotong University, Xian, China, in 1988 and 1991, respectively, and the Ph.D. degree in electrical and computer engineering from the Center for Power Electronics Systems (CPES), Virginia Polytechnic Institute and State University, Blacksburg, in She is a Senior Member of Research Staff at Philips Research USA, Briarcliff Manor, NY, where she is mainly responsible for the research and technology development of digital control systems for power supplies and lighting applications. Her main research interests include power converter analysis and design, digital control system implementation, DSP control algorithms, modeling, and simulation of power converters. Dr. Li is a member of the IEEE Power Electronics Society, Phi Kappa Phi, and Eta Kappa Nu. Fred C. Lee (S 72 M 74 SM 87 F 90) received the B.S. degree in electrical engineering from the National Cheng Kung University, Taiwan, R.O.C., in 1968 and the M.S. and Ph.D. degrees in electrical engineering from Duke University, Durham, NC, in 1971 and 1974, respectively He is a University Distinguished Professor with Virginia Polytechnic Institute and State University (Virginia Tech), Blacksburg, and prior to that he was the Lewis A. Hester Chair of Engineering at Virginia Tech. He directs the Center for Power Electronics Systems (CPES), a National Science Foundation engineering research center whose participants include five universities and over 100 corporations. In addition to Virginia Tech, participating CPES universities are the University of Wisconsin-Madison, Rensselaer Polytechnic Institute, North Carolina A&T State University, and the University of Puerto Rico-Mayaguez. He is also the Founder and Director of the Virginia Power Electronics Center (VPEC), one of the largest university-based power electronics research centers in the country. VPEC s Industry-University Partnership Program provides an effective mechanism for technology transfer, and an opportunity for industries to profit from VPEC s research results. VPEC s programs have been able to attract world-renowned faculty and visiting professors to Virginia Tech who, in turn, attract an excellent cadre of undergraduate and graduate students. Total sponsored research funding secured by him over the last 20 years exceeds $35 million. His research interests include high-frequency power conversion, distributed power systems, space power systems, power factor correction techniques, electronics packaging, high-frequency magnetics, device characterization, and modeling and control of converters. He holds 19 U.S. patents, and has published over 120 journal articles in refereed journals and more than 300 technical papers in conference proceedings. Dr. Lee received the Society of Automotive Engineering s Ralph R. Teeter Education Award (1985), Virginia Tech s Alumni Award for Research Excellence (1990), and its College of Engineering Dean s Award for Excellence in Research (1997), in 1989, the William E. Newell Power Electronics Award, the highest award presented by the IEEE Power Electronics Society for outstanding achievement in the power electronics discipline, the Power Conversion and Intelligent Motion Award for Leadership in Power Electronics Education (1990), the Arthur E. Fury Award for Leadership and Innovation in Advancing Power Electronic Systems Technology (1998), the IEEE Millennium Medal, and honorary professorships from Shanghai University of Technology, Shanghai Railroad and Technology Institute, Nanjing Aeronautical Institute, Zhejiang University, and Tsinghua University. He is an active member in the professional community of power electronics engineers. He chaired the 1995 International Conference on Power Electronics and Drives Systems, which took place in Singapore, and co-chaired the 1994 International Power Electronics and Motion Control Conference, held in Beijing. During , he served as President of the IEEE Power Electronics Society and, before that, as Program Chair and then Conference Chair of IEEE-sponsored power electronics specialist conferences.