Parallel-Connected Converters with Maximum Power Tracking

Transcription

1 Parallel-Connected Converters with Maximum Power Tracking Kasemsan Siri and Kenneth A. Conner Power and Analog Engineering Section, Electrical and Electronic Systems Department The Aerospace Corporation M/S M E. El Segundo Blvd. El Segundo, CA (310) ABSTRACT An improved maximum power tracking (MPT) approach with dither signal injection is presented, including the results of computer simulation and prototype testing. It incorporates a shared-bus current-sharing method that can regulate many paralleled current-mode dc-dc converters. The approach yields nearly uniform current-sharing as well as reliable MPT performance. Utilizing the combined currentsharing and MPT approaches, the MPT power system provides several advantages: (1) ease of system power expansion, (2) stable current-sharing, and (3) autonomous MPT during loss of output voltage regulation. The robust MPT control maintains both stable amplitude and frequency of solar-array voltage ripple. I. Introduction Power conversion from solar-array sources [1-7] requires a more robust power system design than that for power systems with stiff voltage sources due to risks of an array voltage collapse under peak load demand or severe changes in the array characteristics. In satellite power systems, examples could be load demand above the array peak power, low solar flux, incomplete solar-array deployment, and an array pointing angle that is unexpectedly off the sun direction. while continually tracking the array peak power that varies with changes in environmental conditions. Some existing MPT control approaches rarely achieve stability in both amplitude and frequency of the oscillatory array voltage ripple. These MPT approaches can lose their peak-power tracking ability and lock up in a trapped state far from the array peak power point. This is due to inadequacies of the feedback signals used for determining the proper control direction towards the maximum power point. Presented herein is an improved MPT control approach, using dither signal injection and array voltage regulation that optimally transfers the array peak power to the load under severe conditions. The concept is validated through computer simulation and testing of a 750-W MPT power system prototype. II. Fundamentals of the Array Voltage Regulation Control System with Maximum Power Tracking Fig. 1 shows a basic power system with the solar-array voltage regulation and MPT control. The system consists of a solar-array source, current-mode converter power stage with a built-in line-filter, load, input bus stabilizer, output bus stabilizer, output voltage regulation control circuit, array voltage regulation control circuit, and an MPT control circuit. The current-mode converter power stage [8-10] is Array voltage regulation is a robust method of preventing the voltage collapse since it regulates the array voltage to the voltage set point when the load demand exceeds the array peak power. To achieve near-optimum end-of-life (EOL) performance, the array voltage set point remains fixed near or at the array voltage corresponding to the array peak power at EOL. During periods of reduced solar flux or severe degradation of the array characteristics, the clamped array voltage enables reliable power transfer to the load without requiring unnecessary power drain from standby batteries to fulfill the load demand. In this case, it is best to apply an MPT approach to continuously clamp the array voltage at a level corresponding to the array peak power. The MPT control usually operates in an oscillatory mode in which the array voltage contains an ac ripple component, Fig. 1 MPT current-mode converter power system under array voltage regulation control mode.

2 generally a conventional PWM (Pulse-Width Modulation) controlled dc-dc converter. It can be a buck (step-down), buck-boost (step-down or step-up), or boost circuit (step-up) topology. The line-filter provides a means of smoothing the input current drawn from the solar array. This maintains the array current close to its steady dc value, with such a small switching ripple that the solar array operating point is considered to be stationary or nearly in a quiescent steadystate. During typical operating conditions, the power system is in output voltage regulation mode. This occurs when the solar-array voltage is above the clamping set point corresponding to V setpoint. Parallel-connected dc-dc converters are usually operated in output voltage regulation (OVR) mode when system load demand is less than the array peak power. On the array I-V characteristic curve, the OVR mode usually yields the array operating voltage above the array peak-power voltage where the array source behaves similar to a voltage source of low internal impedance. As the load increases, the solar array operating voltage decreases until it reaches the maximum power point while the system output voltage remains regulated. Without MPT control [1-4], when the load current is above the level corresponding to the array maximum power, the array voltage decreases below the array peak-power voltage, and the system output voltage loses regulation. Without proper control, the array voltage can collapse toward zero when load demand is above the maximum power available from the array, particularly when supplying a constant-power type of load. Properly applied, MPT control can prevent the collapse of the array voltage when the power system experiences excessive load demand. One proper approach is to operate the system in a solar array voltage regulation mode in which the array voltage is clamped to a commanding set point, V setpoint, which is dynamically updated by the MPT control circuit. The control processes two feedback signals, the rate of change in the array power and the rate of change in the array voltage. Eventually, this continuously updated set point will fluctuate around the voltage corresponding to the array peak power point. The bus stabilizer across the array voltage is properly designed [9] to achieve a small array voltage ripple and reliable stability during steadystate, step-line, or step-load conditions. injection, experience two major difficulties. One is a trapped state in which the array voltage is stabilized far from the peak-power voltage. The other is that the operating amplitude and frequency of the array voltage ripple around the peak power point are not fixed and difficult to analyze because of load dependency. Consequently, multiple MPT controllers can be employed to process power flowing from independently distributed solar-array sources. These controllers can be synchronized by sharing the same dither signal, enabling the ac voltage ripples superimposed on the distributed array voltages to have the same amplitude and frequency whenever respective sets of paralleled dc-dc converters are controlled in tandem to operate in the MPT mode. Referring to Fig. 1, the frequency of the dither signal is selected to be significantly below the resonant frequency, 1/ LC, formed by the net capacitance, C, across the solar array and the inductance, L, within the line-filter of the current-mode dc-dc converter. The power input port of the paralleled dc-dc converter modules requires a bus stabilizer (BS1) terminated across the solar-array source but located as close to the system input as possible to damp out ac energy, thus ensuring system stability during MPT. III. Paralleled Converter System with MPT Shown in Fig. 2 is the basic architecture of the MPT solararray power system [11] that autonomously adjusts its operating condition to be near or at the maximum power point of the solar-array source, SA, or regulates the system output voltage, V O, when the net load demand is below the peak power. At the same time, near-uniform current-sharing [8, 10] among dc-dc converter modules connected in parallel is achieved through the use of a shared-bus (SB) A dominant feature of the MPT approach, employing a dither signal superimposed on the updated set point, is the controllability of the amplitude and frequency of the array voltage ripple with respect to the amplitude and frequency of the dither signal. Using the dither signal to properly perturb the MPT control loop, the power system can operate without a trapped state in which the array voltage is settled far above or below the peak power voltage. In contrast, several MPT approaches, without dither signal Fig. 2 Basic Configuration of Paralleled Converters with MPT Controller and Single Shared-Bus

3 and parallel control pins (PP). One shared-bus (SB) is used in this power system architecture, providing system control for uniform current-sharing while also satisfactorily meeting the control purpose maximum power tracking when experiencing over-demanding load, or system output voltage regulation when the net load demand is below the available source peak power. Each converter module may have its SB and PP unconnected (floating) when used as a stand-alone unit, thus regulating its own output voltage. Otherwise, the SB or the PP of each converter module is used as a commanding voltage input for regulating the converter power stage as a voltage-controlled current source. When the parallel pins and shared-buses of many identical converter modules are respectively tied together to form two unified control ports, all converter modules are regulated by the same controlling voltage generated from either the MPT controller or the OVR circuits residing within the paralleled converters. This results in not only nearly a uniform distribution of the converter output currents but also the elimination of undesirable interactions experienced by other approaches of current-sharing during output voltage regulation mode. The implemented configuration shown in Fig. 2 is a parallel-connected dc-dc converter system interfacing between a solar-array source and a common system load. In this configuration, only one MPT controller is needed for tracking the peak-power point of the solar array source. The MPT controller has a controlling output port commonly connected to the paralleled SB provided by the parallel-connected dc-dc converters. Therefore, physical layout and inter-connection of the system should be carefully implemented to minimize chances of a singlepoint failure on the paralleled shared bus or parallel-pins. As an option shown in Fig. 2, the battery charging circuitry as well as the standby battery set-up can be connected across the system output bus, V O, to either replenish the battery charge or supplement the load demand. IV. Power System Simulation with MPT A computer model of the MPT converter power system shown in Fig. 1 was developed and simulated under two different levels of solar flux. Shown in Fig. 3 is the simulated trajectory of the power system input voltage and current overlaid on the solar-array I-V characteristics. The solar-array voltage regulation control circuit is simply an integral-lead-lag error amplifier. As the solar array voltage drops to a value less than or equal to the target regulatedlevel corresponding to its voltage set-point (V setpoint ), the clamp error amplifier reduces the controlling signal, V C, feeding the control port of the current-mode converter power stage. Therefore, the solar-array voltage is regulated to the level corresponding to the set-point voltage that is continually updated by the MPT control circuit. Fig. 3 Trajectory, between two peak power points, of the MPT power system input voltage and current overlaid on the solar array I-V curves. Fig. 4 depicts the transient and near-steady responses of the array and output voltages of the basic system operating in the MPT and the OVR modes. Fig. 4 Transition from the MPT mode to OVR mode, illustrating the array and output voltages. V. Guidelines for Stable MPT Power System Some simple guidelines help the system design achieve robust stability. First, solar-array voltage regulation control is used as the basic control loop for operation of MPT, providing adequate bandwidth of the control loop response and being well compensated for adequate stability margin. Second, the MPT control circuit updates the voltage commanding set-point (VCSP) slowly and smoothly when compared to the speed of the array voltage regulation control loop. Finally, a small but sufficient dither signal, at a low frequency, is superimposed on the VCSP to ensure reliable and predictable processing of the MPT algorithm. To achieve stability during MPT operation, first the crossover frequency of the array-voltage regulation loop

4 gain (or the unity gain bandwidth) must be sufficient. Second, the resonant frequency [9] of the high-q L-C circuit at the converter input must be sufficiently greater than the control loop crossover frequency so that instability due to its peaking effect is not present. This eliminates multiple crossover frequencies around such a resonant frequency. However, if the resonant frequency is designed to be in the vicinity above the loop-gain crossover frequency, instability due to the resonance peaking effect is very likely. An additional ac damping circuit across the converter input is needed to damp out the resonance peaking effect. VI. Experimental Prototype of a 750-W MPT System According to the system block diagram shown in Fig. 2, an MPT power system prototype, consisting of one power board and one MPT control board without the stand-by battery and its charger, was developed to validate the dithered MPT and current-sharing approach. As shown in Fig. 5, the power board consists of three 250-W paralleled converters. The converters are commercial-off-the-shelf (COTS) products that are currently available with output ratings of 28 9 A with input voltage requirements of 36 V to 72 V. Each COTS converter is provided with a parallelpin (PP). As shown in Fig. 1, a PNP transistor Q is used as a distributed current-sink via its emitter and collector pins which are physically terminated right across the PP and the converter input-return terminals. Connected to the base of the transistor and the output of the MPT controller, the SB terminal draws much less controlling current. Two paralleled solar-array-source simulators (SASs) were used to represent a solar array capable of delivering up to 960 W power with programmable maximum short-circuit current of 16.3 A and maximum open-circuit voltage of 60 V. The load circuit is simply a selectable combination of paralleled resistors. converter modules through the SB as shown in Fig. 1. SB and PP pins can be tied together, and the PNP transistor Q can be removed, provided that the system has only a few paralleled converters and the array voltage clamp error amplifier has sufficient current sinking capability. Otherwise, SB and PP pins are interfaced by transistor Q that provides a distributed current-sink to its respective voltage-error amplifier within each converter. When transistor Q becomes active during the MPT mode of operation, the driving impedance across the PP and return terminals is much lower as compared to that without the transistor, resulting in more effective noise attenuation. Separated from the power board, the multiplier and MPT control circuit was implemented on the MPT control board shown in Fig. 6. Included on the MPT control board are the solar-array voltage clamp error amplifier, the MPT analog and logic control circuit, the analog multiplier and scaler circuit, and the 250-Hz dither signal generator. The solararray current-sense and voltage signals are the inputs and the SB signal is output through the twenty-pin IDC connector. Fig. 6 Prototype of the MPT control board with the IDC cable interface. Fig. 5 Prototype of the power and MPT control boards. The MPT controller processes the array voltage and current feedback signals V in and I in. The controller, consisting of a simple combination of analog and logic circuits, is able to deliver the proper control signal, regulating one or more A house-keeping power supply, installed on the power board shown in Fig. 5, is a small COTS converter providing ±12 V bias voltages to the MPT control board through the IDC cable. The bias converter has its input voltage rating from 9 V to 36 V. As a result, the paralleled SASs supply electrical power only to the MPT power system prototype without requiring any external house-keeping power supply. During start-up, the SASs provide the input power to the internal house-keeping power supply through a linear regulator. Once the power system output voltage is sufficiently built up, the linear regulator is shut off, and the system output voltage feeds the input power to the power supply. Shown in Fig. 7 are the test waveforms of the array voltage and power, revealing that the frequency of the power signal is twice that of the array voltage at its maximum power

5 Fig. 7 Basic array voltage and power signals at a maximum power point. Figs. 10 and 11 illustrate the dynamic response of the array voltage, array current, and sensed array power signal. There are two characteristics that were changed one at a time: array peak-power current and array peak-power voltage. Fig. 10 reveals that the peak-power array voltage remains at or returns to its unchanged value (such as Vmp set at 35 V) despite step changes in array peak-power current between 6 A and 8 A. Later the array peak-power voltage was changed to 45 V and the array voltage was readjusted to 44 V within 600 ms. Fig. 11 illustrates a similar response for a change of array peak-power voltage from 45 V to 35 V and step changes in array peak-power current between 6 A and 8 A. The array power signal was derived mainly from the acdithered power signal extracted from the total power signal. Fig. 8 Steady-state response of array voltage, current, and power at 400-W maximum power point. Fig. 10 Array voltage, current, and power under a change in peak-power voltage from 35 V to 45 V. Fig. 9 Steady-state response of array voltage, current, and power at 288-W maximum power point. point. Obtained from the prototype set-up, Figs. 8 and 9 show steady-state response of the array voltage, current, and power at their maximum power voltages of 50 V and 36 V, respectively. The figures show the array voltage ripple that is kept constant at 2.8 V peak-peak at the dither frequency of 250 Hz despite different peak power points. Also note that, due to some phase delay existing in the produced power signal, the mean value of the array voltage may be slightly below the maximum power voltage (Vmp). Fig. 11 Array voltage, current, and power under a change in peak-power voltage from 45 V to 35 V. Figs. 12 and 13 show the array voltage and power signal responses, revealing transitions between the MPT and OVR modes of operation. From the figures, 600 W of array peak power is transferred to the power system during the MPT mode and 460 W of array power is transferred during the OVR mode in which the system output voltage is regulated

6 at 28 V. During the MPT mode, the output voltage loses its regulation and settles at V which is as close to 28 V for this particular load condition. Array voltage and power signal responses under repetitive pulsating load conditions are also recorded from the power system prototype, as shown in Figs. 14 and 15. Fig. 14 reveals that the array voltage remains stable at the peakpower level ( V), while the load is repetitively pulsated at 1 Hz between 1-ohm and 1.6-ohm resistance. As shown in Fig. 15, the array dc voltage is firmly regulated at the same peak-power voltage, while the output load is repetitively stepped between 306 W and 561 W at 1 khz. Consequently, testing results under repetitive loads of which the pulsating frequency is varied from 1 Hz to 1 khz showed that both the dc average and the ac ripple of the array voltage are very stable around the array peak-power operating point. Fig. 14 Array voltage, array power, and 1-Hz switching output voltage, showing robust MPT. Fig. 12 Array voltage and power response, showing a transition from MPT to OVR mode of operation. Fig. 15 Array voltage, array power, and 1-kHz switched load current, revealing reliable MPT. VII. Advantages of the MPT Approach Fig. 13 Array voltage and power response, showing a transition from OVR to MPT mode of operation. Advantages of the proposed system can be summarized as follows: Use of a control shared-bus and parallel-pin to meet an added-on control purpose such as maximum power tracking without internal circuit modifications of the parallel-connected COTS dc-dc converters. Near-uniform current sharing without conflicts in output voltage regulation among parallel-connected COTS dc-dc converters. A basic infrastructure of power processing management to use the maximum available power of the solar-array sources (or sources of similar characteristics).

7 VIII. Conclusion The improved MPT power system, developed for solararray-based power systems through computer simulation and an experimental prototype, was proposed and successfully validated for a system configuration consisting of multiple dc-dc converters connected in parallel. The simulation and prototype experimental results obtained from the proposed MPT scheme and system architecture showed satisfactory performance in both modes of operation: OVR and MPT. Despite step changes in array characteristics and load conditions, the developed MPT controller continues to track the array peak-power points with reliable stability. Combined with the proposed MPT scheme, the shared-bus current-sharing approach was successfully applied to the MPT power systems. This combined approach of current sharing and MPT further demonstrates the potential applicability of COTS converters. The MPT power system can be further applied: As an intermediate step to supply power to a 60-Hz utility grid for reduction of average and peak-load demand observed by the utility system. As a means to maximize the traveling distance of electric vehicles or spacecraft equipped with electric propulsion systems. As a means to maximize data rate and signal-to-noise ratio of the microwave or communication links. As a means to maximize battery life in remote-area facilities such as telecommunication stations. In summation, the following merits have been accomplished or recognized: MPT system design guidelines were developed for ease of system design and implementation to achieve robust system stability, and the overall MPT system performance was verified to be satisfactory through computer simulation. Feasibility of parallel-connected COTS converters for MPT applications was demonstrated by computer simulation and experimental prototype. A robust and expandable MPT concept that allows fixed amplitude and frequency of the solar-array voltage ripple was not only analyzed by simulation but also verified with prototype testing. Reproducible system performance, Nearly uniform current-sharing and stiff voltage regulation. Proper dither signal injection is required for reliable MPT. REFERENCES [1] B. H. Cho, Modeling and Analysis of Spacecraft Power Systems, Ph.D. Dissertation, VPI & SU, Blacksburg, VA, [2] B. H. Cho, F. C. Lee, Modeling and Analysis of Spacecraft Power Systems, IEEE PESC; [3] B. H. Cho, J. R. Lee, Design, Analysis and Simulation of the Main Bus Dynamics of Spacecraft Power System, 1988, IECEC. [4] S. Peck, R. Devaux, STC/DBS Power Subsystem Control Loop Stability Analysis, Proceedings, 19 th IECEC, 1984, Volume 1, pages [5] D. K. Decker, Method for Utilizing Maximum Power From a Solar Array, JPL Quarterly Technical review, Vol. 2, No. 1, pp , [6] P. Huynh, B.H. Cho, Design and Analysis of a Microprocessor Controlled Peak-Power Tracking System, IEEE Trans. On Aerospace and Electronic Systems, Vol. 32, No. 1, January 1996, pages [7] Kasemsan Siri, Vahe A. Caliskan and C.Q. Lee, Maximum power tracking in parallel-connected converter systems, IEEE Trans. on Aerospace and Electronics Systems, vol. 29, no. 3, pp , July [8] Kasemsan Siri and Calvin Truong, Performance Limitations of Random Current-Sharing Parallel- Connected Converter Systems & Their Solution, APEC 98, Anaheim, California, pp , Vol. 2, February 14-19, [9] Kasemsan Siri, Study of System Instability in Current- Mode Converter Power Systems Operating in Solar Array Voltage Regulation Mode, APEC 2000, New Orleans, Louisiana, pp , Vol. 1, February 6-10, [10] Kasemsan Siri, Shared-Bus Current Sharing Parallel Connected Current-Mode DC to DC Converters, U.S. Patent no. 6,009,000, December 28, [11] Kasemsan Siri and Kenneth A. Conner, Fault- Tolerant Scaleable Solar Power Bus Architectures with Maximum Power Tracking, APEC 2001, Anaheim, California, pp , Vol. 2, March 4-8, Simple paralleling of current-mode converters with a shared-bus allows: