High Voltage Dual-Gate Turn-off Thyristors

Transcription

1 Oscar Apeldoorn, ABB-Industrie AG CH-5 Turgi Peter Steimer Peter Streit, Eric Carroll, Andre Weber ABB-Semiconductors AG CH-5 Lenzburg Abstract The quest of the last ten years for high power snubberless semiconductor switches has resulted in IGCTs (Integrated Gate-Commutated Thyristors) and IGBTs (Insulated- Gate Bipolar Transistors) currently available up to. Both devices have inherently short switching times but are nevertheless frequency limited by their switching losses. IGCTs have been shown to be useable up to about 5.5 DC and Hz []. However market needs for PWM (pulse width modulation) at about khz cannot be satisfied above DC, due to the inherent turn-off losses of the aforementioned bipolar components. The fundamental barrier presented by the charge stored in the n-base of IGBTs and IGCTs must be reduced at turn-off without increasing conduction losses. The use of a second, anode-side gate (n-gate) to reduce the high plasma density at turn-off has already been described for conventional snubbered GTOs [,] but the technique has not yet been applied to a snubberless device such as the IGCT. This paper will show the turn-off loss reductions which can be obtained by "grafting" a second gate to the conventional IGCT and will compare these results to those of a new type designed specifically for "gateassisted turn-off". I. INTRODUCTION A. Performance Considerations The motivation for such high voltage devices lies in applications for 7 V RMS lines. Today such an equipment can be realized with two series-connected IGCTs which easily achieve khz PWM but require R-C snubbers for the series connection []. Though simple enough, the number of components required at the switch level increases nearly three-fold and becomes an obstacle to the widespread use of power electronics at this voltage level. Today s -level IGCT inverters for the V line can operate at up to Hz PWM [] or higher. At V RMS line, PWM frequencies of 5 Hz are typical [5]. To realize inverters on the 7 V RMS line would require two series connected IGCTs. Currently such devices use about % of their thermal budget in conduction loses and % in switching losses at 5 Hz. devices operating on the. 7. RMS line would exhibit a slightly higher dynamic loss ratio [] of about 75% at the same frequency. If these dynamic losses could be reduced by a factor two, a device could theoretically operate at khz on the 7. line with % of the power of a V design (using IGCTs of the same size wafer). B. Cost Considerations Within high power products the costs of the semiconductors together with that of its drivers, control and mechanics have a high impact on the final bill of material (BoM). A step towards a 7. application by using.5 GCTs would roughly imply a doubling of all semiconductors, drivers, control and mechanics. Although the size of the semiconductors decreases and also the mechanics could be simplified at certain places, the calculated impact for real equipment can still be a BoM increase of 5% - %. Even the volume of the product increases drastically. The use of HV dual-gate devices instead of series connection has only modest impact on the product mechanics, drivers and control. A redesign of standard.. products into. 7. products would entail some increase od semiconductors cost per switched but there would only be a few changes in mechanics, drivers and control and only a marginal variation in the total BoM and equipment size. C. Motivation Based on the above considerations, it is believed that the added complexity and cost of a dual-gate switch will be economically acceptable (compared to two series-connected IGCTs) if the losses per switched power of a device are equal or less than those of.5 devices D. Structures The structure of the Dual Gate-Turn-off Thyristor is shown in Fig.. This device can be processed in the same way as a conventional (single-gate) IGCT. G G K A G G Fig.. Semiconductor-structure of a "symmetrical" Dual Gate IGCT G K A G IAS page of 5 October

2 A. Gate Units II. TESTS Device testing is performed with a gate unit connected to gate G and with an additional gate unit connected to gate G. The timing of gate G with respect to gate G can be delayed from to µs. B. Test Circuit Fig.. shows the Device Under Test (DUT) in its test circuit. During commutation after GCT turn-on the inductance Lc controls the di/dt of the Free Wheel Diode (FWD). The capacitor Ccl clamps over-voltages at DUT turn-off. C. Gate Timing The DUT is turned-off by reverse-biasing the gate-cathode via the GU (V GK negative). At turn-off GU has an output voltage which is always positive (V GA = to +V). At a time t prior to G turn-off, GU is switched on. In this way, charge carriers in the anode side pn-junction are removed before switching off the complete device via GU. GU is kept in this state until at least 5µs before the next turn-on pulse. The values of t and V GA effect the turn-off losses. III. EXPERIMENTAL RESULTS Devices of both asymmetric and symmetric design were tested. A. Asymmetric Dual-Gate Figs. and 5 show the results on asymmetric dual gate IGCT devices. The identification "single" refers to DUT turnoff without G assist. Fig. shows turn-off waveforms as a function of t for V GA = +5 V. Synchronous triggering of both gates ( t = ) already resulted in a significant reduction in tail-current and losses. Progressive increases in t further reduced tail losses but provoked a small premature rise of the anode voltage increasing the losses during the voltage rise..mf Udc Lcl Ls Rs Ls Ccl Dcl FWD Fig.. Test circuit for measuring Dual-Gate IGCT behavior GU GU It Lload DUT V G,A V G,A - V No further loss reductions were obtained beyond t = µs as seen in Fig.. The measurements were repeated for a fixed value of t = µs but with V GA varied from to 5 V and the results are shown in Fig. 5. The greatest loss reduction is achieved with the highest voltage as this maximizes the speed at which the charge carriers are removed from the anode-side pn-junction. The above tests carried out on a Dual-Gate IGCT processed from a standard GCT revealed switching loss reductions of up to 5% at 5V/5A/5 C by pretriggering G µs ahead of G as compared to G operation alone. B. Symmetric Dual-Gate 5 µ t s 5 µ s t on Fig.. Timing of the dual gate signals Anode-gate Cathode-gate The tests were repeated with devices of symmetric design with both.5 and 5.5 ratings and compared with a standard.5 IGCT (type 5SHY 5L5). Fig. shows the turn-off at DC of a.5 symmetric dual-gate device with the two gates switched simultaneously ( t = µs) for a G voltage of V. In this experiment, the gateunit merely shorts out the pnp transistor but does not actively extract n-base charge. The anode current is varied from. to. It is noteworthy that the tail current varies little with anode current. Fig. 7 shows the results of the same test as for Fig. but with V GA = V. The anode gate unit is now able to eliminate the tail current reducing the turn-off loss from Ws at to. Ws, a % improvement (with respect to itself). The same device as tested in Figs. and 7 is successfully tested to. /. in Fig.. All the turn-off losses appear to be generated in the voltage-rise and current-fall phases, the tail losses having been virtually eliminated. The device generates a measured loss of.5 Ws. The voltagerise and current-fall times are both. and. µs respectively leading to calculated losses during these phases of. Ws and 7.7 Ws each. Thus the total rise and fall losses are a calculated. Ws which indeed indicates the absence of a tail current. IAS page of 5 October

3 Power (), Energy () Voltage (), Current () IA ( t= us) IA ( t= us) IA ( t= us) IA ( t= us) IA single E single E ( t= us) E ( t= us) E ( t= us) E ( t= us) Power (), Energy () Voltage (), Current () IA (VG = +5V) IA (VG = +V) IA (VG = 5V) IA (VG = V) IA single E single E (VG = V) E (VG = +5V) E (VG = +V) E (VG = +5V) Fig.. Asymmetric Dual-Gate IGCT Turn-off as a function of pre-triggering of G (VGA = 5 V) Fig. 5. Asymmetric Dual-Gate IGCT Turn-off as a function of pre-triggering of V GA ( t = µs) Power (), Energy () Voltage (), Current () Power (), Energy () Voltage (), Current () Fig.. Symmetric Dual-Gate-IGCT V DRM =.5, V TM =. /5 C V D =, T j = 5 C, V GA = V, t = µs I TGQ =.;.;. Fig. 7. Symmetric Dual-Gate-IGCT V DRM =.5, V TM =. /5 C V D =, T j = 5 C, V GA = V, t = µs I TGQ =.;.;. C. Comparison with Conventional IGCTs In Fig., the turn-off waveforms of two differently irradiated standard IGCTs of.5 rating are compared with those of a 5.5 dual-gate device when synchronously gated ( t = µs) and when pre-triggered with t =.5 µs. Although the 5.5 device has a % thicker n-base, the comparison is made because, as a symmetrically structured device, it has a similar on-state voltage to one of the two asymmetrically structured IGCTs (.55 and. I A =, T j =5 C for the 5.5 dual-gate and one of the.5 IGCTs respectively). Additionally, they have similar turn-off losses (about Ws) in the case of the synchronously triggered dual-gate. Pretriggering the dual-gate device by.5 µs reduces E OFF by % to 7 Ws. Further pre-triggering is not possible as the anode current falls faster than linearly and provokes a snapoff as it goes to zero resulting in a high peak voltage ( 5.5 ). Correcting the % loss improvement to allow for the thicker silicon used results in an effective improvement of % IAS page of 5 October

4 Power (), Energy () Voltage (), Current () Power (), Energy () Voltage (), Current () 5 Fig.. Symmetric Dual-Gate-IGCT V DRM =.5, V TM =. /5 C I TGQ V DC =.5 T j = 5 C, V GA = V, t = µs In a repetition of the experiment of Fig., the anode current was lowered from. to. and the pretrigger advanced to µs before the over-voltage also reached 5.5. This resulted in a % loss reduction or % corrected which was the best improvement, with respect to a conventional IGCT, obtained in the present series of experiments. In Fig., a low on-state IGCT is compared with a.5 Dual-Gate IGCT of similar on-state and silicon thickness. In this test, the on-set of snap occurred at t = µs for. and.. With the synchronous triggering used, only % loss reduction was achieved. The tail current was eliminated but the bulk of the losses were located in the rise and fall phases rendering the gate-assisted turn-off of little value. D. Discussion of the Measurement Results Figs. to illustrate that the symmetric design allows very low on-state devices to be realized. The turn-off losses are effectively reduced by pre-triggering where: the silicon is thicker: Fig. (% improvement) vs Fig. (% improvement) the current is lower: (. - % improvement) vs. (. - % improvement) maximum pre-triggering can be exploited without snap. Fig. shows that higher voltage devices (5.5 vs..5 ) can be made with the same on-state voltage (.55. V at /5 C) while still achieving a % loss reduction at. DC. Alternatively, the same turn-off losses and onstate voltages should be achieved at. DC (% voltage increase). Fig. shows the turn-off waveforms of conventional.5 IGCTs with three different irradiation levels []. Power (), Energy () Voltage (), Current () Fig.. Comparison of two IGCTs type 5SHY 5L5 (different irradiation doses) with a 5.5 Dual-Gate Tj = 5 C, V GA = V ) IGCT, V TM =. V ) IGCT, V TM =. V ) Dual-Gate IGCT, ) Dual-Gate IGCT VTM =.55 V, t = µs VTM =.55 V, t =.5 µs 5 Fig.. Comparison of two IGCTs, type 5SHY 5L5.5 standard IGCT with a.5 Dual-Gate C IGCT, V TM =. V@ (pronounced tail) Dual-Gate IGCT, V TM =. V@, t = µs, V GA = V (no tail) Lifetime control (by irradiation) effects all three phases of the snubberless turn-off process: Phase - rising voltage at constant current Phase - falling current at (approx.) constant voltage Phase - tail current at (approx.) constant voltage. The effect of de-saturating the anode pnp transistor prior to and during turn-off has been shown to completely eliminate the Phase tail current losses. Advancing pre-triggering also has an action on the Phase falling current at constant voltage, causing the anode current to fall so rapidly that overvoltage spikes are generated which ultimately exceed the device s blocking capability. This explains why the greatest 5 IAS page of 5 October

5 loss-reduction benefits are achieved with the longest lifetime devices as these have the largest tail currents. Pre-triggering is limited by the on-set of snap-off. Snap is aggravated by thin silicon and high currents indicating that this technology will be of benefit at the higher voltages and their correspondingly lower currents. The first measurements performed on transparent emitter devices (Figs and 5) showed no tendency to snap even with t of µs. Furthermore, the E OFF reduction resulting from reducing tail current with increasing pre-trigger was partly off-set by a prematurely rising anode voltage. This is clearly not the case with a high sensitivity to pre-triggering. The conventional IGCTs shown in Fig. exhibit peak values of dv/dt between and /µs and of di/dt between and /µs. These appear to be application-acceptable values for EMC considerations. Efforts should be made to achieve shorter rise and fall times through anode-gate control (while controlling snap-off) if the ambitious goal of a factor E OFF reduction is to be achieved. Otherwise, a factor improvement with current techniques is feasible. Simulations of conventional IGCTs [] have shown that allowing the turn-off loss of a mm device to double results in a 5% reduction of on-state voltage (see Fig. ). Realizing a dual-gate device with an on-state voltage of about. V at A instead of the simulated 5. V would correspond to a device having Ws loss switching. against 5. the same loss as currently achieved by.5 IGCTs switching against. and having on-state voltages of.7 V at A. IV. CONCLUSIONS The use of an anode gate can eliminate the tail current of the conventional IGCT. In this respect, it is even more effective than lifetime control, which only reduces tail-losses while increasing conduction losses. Anode-gate control also offers the possibility of reducing rise and fall times (which I A, V AK, [A, V] Fig.. t [µs] has now become the dominant switching loss). The symmetric structure is found to offer the greatest loss reductions and to allow even lower on-states than achieved by the transparent emitter of conventional IGCTs. REFERENCES V AK Turn-off waveforms of conventional IGCTs Type Type Type (Types, and ) showing the effect of varying degrees of lifetime control. The waveforms are synchronized to the fall of anode current.t = 5 C. 5SHY 5L5: V TM = V at /5 C 5SHY 5L5: V TM =.7V 5SHY 5L5: V TM =.5V [] S. Eicher, S. Bernet, P. Steimer, A. Weber, The IGCT A New Device for Medium Voltage Drives, IEEE- IAS [] Tsuneo Ogura, Akio Nakagawa, Masaki Atsuta, Yoshio Kamei, Katsuhiko Takigami; "High-Frequency V Double Gate GTOs", IEEE Transactions on Electron Devices, Vol. N. [] U. Wiesner, R Sittig; "Control of Plasma Dynamics within Double-Gate-Turn-Off Thyristors (D-GTO)", Simulation of Semiconductor Devices and Processes Vol., 5 [].P. Lyons. V. Vlatkovic, P.M. Espelage, F.H. Boettner, E. Larsen, (GE), Innovation IGCT Main Drives, IEEE IAS, [5].K.Steinke, R. Vuolle, H. Prenner,. ärvinnen, New Variable Speed Drive with Proven Motor Friendly Performance for Medium Voltage Motors, Int. Electric Machines and Drives Conf. (IEMDC), Seattle, Washington (USA), May -,, Conf. Proc. pp. 5- [] Th. Stiasny, B. Oedegard, E. Carroll Lifetime Engineering for the Next Generation of Application- Specific IGCTs, Drives & Controls, London, March I A Fig.. E OFF as a function of on-state voltage for 5.5 and IGCTs IAS page 5 of 5 October