MAX19700 Evaluation Kit/Evaluation System

Transcription

1 -; Rev 0; /0 MAX00 Evaluation Kit/Evaluation System General Description The MAX00 evaluation system (EV system) consists of a MAX00 evaluation kit (EV kit), a companion Maxim command module (CMOD) interface board, and software. Order the complete EV system (MAX00EVCMOD) for comprehensive evaluation of the MAX00 using a personal computer. Order the EV kit (MAX00EVKIT) if the command module has already been purchased with a previous Maxim EV system, or for custom use in other microcontroller-based (µc) systems. The MAX00 EV kit is a fully assembled and tested circuit board that contains all the components necessary to evaluate the performance of the MAX00 analog front-end (AFE). The MAX00 integrates a dual receive analog-to-digital converter (Rx ADC), a dual transmit digital-to-analog converter (Tx DAC), a.0v internal voltage reference, and three low-speed serial DACs. The EV kit board accepts AC- or DC-coupled, differential or single-ended analog inputs for the Rx ADC and includes circuitry that converts the Tx DAC differential output signals to single-ended analog outputs. The EV kit includes circuitry that generates a clock signal from an AC sine-wave input signal. The EV kit operates from a +.0V analog power supply, a +.V digital power supply, a +.0V clock power supply, and ±V bipolar power supplies. The Maxim command module interface board (CMOD) allows a PC to use its serial port to emulate an SPI -wire interface. Windows /000/XP -compatible software, which can be downloaded from provides a user-friendly interface to exercise the features of the MAX00. The program is menu driven and offers a graphical user interface (GUI) with control buttons and a status display. ADC/DAC Sampling Rate Up to.msps Low-Voltage and Power Operation Adjustable Gain Low-Speed DAC Buffers On-Board Clock-Shaping Circuitry On-Board Level-Translating I/O Drivers Assembled and Tested Include Windows /000/XP-Compatible Software PART MAX00EVKIT TEMP RANGE 0 C to +0 C IC PACKAGE Features SPI INTERFACE TYPE TQFN Not included 0 C to MAX00EVCMOD TQFN CMOD +0 C Note: The MAX00 EV kit software is provided with the MAX00EVKIT; however, the CMOD board is required to interface the EV kit to the computer when using the included software. PROGRAM DESCRIPTION INSTALL.EXE Installs the EV kit software MAX00.EXE Application program Ordering Information MAX00 EV Kit Files HELPFILE.HTM MAX00 EV kit help file UNINST.INI Uninstalls the EV kit software SPI is a trademark of Motorola, Inc. Windows is a registered trademark of Microsoft Corp. Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at ---, or visit Maxim s website at

2 MAX00 Evaluation Kit/Evaluation System DESIGNATION QTY DESCRIPTION C C, C, C, C, C, C, C, C C0, C C, C C, C, C0, C, C, C C C0 ±0%, 0V XR ceramic capacitors (00) TDK C00XRA0M pf ±%, 0V C0G ceramic capacitors (00) TDK C00C0GH0J C, C C 0 Not installed (00) C 0 Not installed (00) C, C, C C, C C, C, C0, C C C, C, C, C C0, C C, C, C C C0 C C C C 000pF ±%, 0V C0G ceramic capacitors (00) TDK C0C0GH0J 0.µF ±0%, 0V XR ceramic capacitors (00) TDK C0XRAK.0µF ±0%,.V XR ceramic capacitors (00) TDK C00XR0J0M ±0%,.V XR ceramic capacitors (00) TDK C00XR0J0M.µF ±0%,.V XR ceramic capacitors (00) TDK C0XR0JM 0µF ±0%,.V tantalum capacitors (C-case) AVX TPSCM00R00 0µF ±0%, 0V XR ceramic capacitors (0) TDK CXRA0M 0.0µF ±%, V C0G ceramic capacitor (00) TDK C0C0GE0J 0.µF ±0%,.V XR ceramic capacitor (00) TDK C00XR0JK Component List DESIGNATION QTY DESCRIPTION D Dual Schottky diode (SOT) Zetex BAS0-0 Central Semiconductor CMPDS Vishay BAS0-0 Diodes INC BAS0-0 J x 0 right-angle female connector J, J, J, J, J, J, J0, J, J SMA PC mount connectors J, J -pin headers J Dual-row, 0-pin header JU Jumper, dual-row, -pin header JU, JU, JU, JU Jumpers, -pin headers JU Jumper, -pin header R R, R, R, R R R, R R, R, R.Ω ± resistors (00) 0 Not installed (00) R R0.Ω ± resistors (00) R R, R R, R R, R, R 0 Not installed (00) R R 0kΩ ± resistors (00) R, R.0kΩ ± resistors (00) R.0kΩ ± resistor (00) R0.0kΩ ± resistor (00) R RA, RA kω potentiometer, -turn, /in Vishay TYB-K-0-D0 00Ω ±% resistor arrays Panasonic EXB-HV-0J RA, RA Ω ±% resistor arrays Panasonic EXB-HV-0J RA, RA Not installed (0) T, T : RF transformers Coilcraft TTWB00- TP TP Test points (black)

3 MAX00 Evaluation Kit/Evaluation System DESIGNATION QTY DESCRIPTION U U Maxim MAX00ETM (-pin thin QFN mm x mm) 0-bit dual-supply bus transceiver (-pin TSSOP) Texas Instruments SNAVCH0TGR U Maxim MAXESA (-pin SO) U, U Maxim MAX0ESA (-pin SO) U Maxim MAXAUD (-pin TSSOP) Component List (continued) DESIGNATION QTY DESCRIPTION U U Maxim MAX0EUD (-pin TSSOP) Maxim MAX0EUD (-pin TSSOP) Dual-supply -bit signal translator (-pin DQFN) Fairchild FXLT None Shunts None MAX00 PC board None MAX00 EV kit software (CD-ROM) SUPPLIER PHONE FAX WEBSITE AVX Central Semiconductor Coilcraft Diodes Inc Fairchild -- Panasonic TDK Texas Instruments Vishay/Vitramon Zetex USA Note: Indicate that you are using the MAX00 when contacting these component suppliers. Component Suppliers Quick Start Recommended Equipment DC power supplies: Analog () +.0V, 00mA Clock (C) +.0V, 00mA Digital (O) +.V, 00mA Buffers (BVCC) +.V, 00mA Op-Amp Positive (VOP) +.0V, 0mA Op-Amp Negative (VON) -.0V, 0mA Signal generator with low phase noise and low jitter for clock input signal (e.g., HP A, HP B) Two signal generators with low phase noise for analog signal inputs (e.g., HP A, HP B) Logic analyzer or data-acquisition system (e.g., HP 00C, TLA) Analog bandpass filters (e.g., Allen Avionics, K&L Microwave) for input signals and clock signal Two spectrum analyzers (e.g., HP 0E) One 0-bit digital pattern generator (e.g., Tektronix DG00A) Procedure The MAX00 EV kit is a fully assembled and tested surface-mount board. Follow the steps below to verify board operation. Do not turn on power supplies or enable signal/data generators until all connections are completed. Command Module Setup ) Set both switches at SW to the OFF position to disable the SDA/SCL pullup resistors. ) Place a shunt across pins - of the select jumper (command module working voltage set to +.V).

4 MAX00 Evaluation Kit/Evaluation System ) Connect a cable from the computer s serial port to the command module (CMOD) interface board. Use a straight-through -pin male-to-female cable. To avoid damaging the EV kit or computer, do not use a -pin null-modem cable or any other proprietary interface cable that is physically similar to the straight-through cable. ) Connect the provided wall-cube power supply to the CMOD board. EV Kit Software Setup ) The MAX00.EXE software program can be run from the CD-ROM or hard drive. Use the INSTALL.EXE program to copy the files and create icons in the Windows /000/XP Start menu. EV Kit Setup ) Verify that shunts are installed in the following locations: JU (-) CS Connected JU (-) SCLK Connected JU (-) DIN Connected JU (-) MAX00 Enabled JU (Installed) Internal Reference Enabled JU (-) Digital Bus Level Shifting Enabled JU (-) Reserved ) Connect a +.0V, 00mA power supply to. Connect the ground terminal of this supply to. ) Connect a +.0V, 00mA power supply to C. Connect the ground terminal of this supply to. ) Connect a +.V, 00mA power supply to O. Connect the ground terminal of this supply to D. 0) Connect a +.V, 00mA power supply to BVCC. Connect the ground terminal of this supply to D. ) Connect a +V, 0mA power supply to VOP. Connect the ground terminal of this supply to. ) Connect a -V, 0mA power supply to VON. Connect the ground terminal of this supply to. ) Carefully align the 0-pin connector of the MAX00 EV kit (J) with the 0-pin header of the CMOD interface board (P). Gently press them together. ) The MAX00 supports three modes of operation: a. To connect a logic analyzer to the EV kit and test the Rx ADCs, skip to step. b. To connect a spectrum analyzer to the EV kit and test the Tx DACs, skip to step. c. To connect an ASIC or FPGA to the EV kit, see the Configuring for ASIC/FPGA Connection section in this document. Rx ADC Setup ) Ensure that a shunt is placed across pins and of jumper JU. ) Connect the clock signal generator to the input of the clock bandpass filter. ) Connect the output of the clock bandpass filter to the EV kit SMA connector labeled J0. ) Connect the first analog signal generator to the input of the desired bandpass filter. ) Connect the output of the bandpass filter to the EV kit SMA connector labeled J (I channel). 0) Connect the second analog signal generator to the input of the desired bandpass filter. ) Connect the output of the bandpass filter to the EV kit SMA connector labeled J (Q channel). ) Ensure that all signal generators are phase-locked to a common reference frequency. ) Connect the logic analyzer to J. See the Digital Data Bit Locations section in this document for header connections. ) Set the logic analyzer to capture 0-bit CMOS data on the falling edge for the I channel (J) or the rising edge for the Q channel (J). ) Turn on the -V power supply. ) Turn on all remaining power supplies. ) Plug the CMOD wall cube into an electrical outlet. ) Enable the signal generators. ) Set the clock signal generator to output a.mhz signal. The amplitude of the generator should be sufficient to produce a.dbm signal at the SMA input of the EV kit. Insertion losses due to the seriesconnected filter (step ) and the interconnecting cables will decrease the amount of power seen at the EV kit input. Account for these losses when setting the signal-generator amplitude.

5 MAX00 Evaluation Kit/Evaluation System 0) Set the analog input signal generators to output the desired frequency. The amplitude of the generator should produce a signal that is no larger than.dbm as measured at the SMA input of the EV kit. Insertion losses due to the series-connected filter (steps and 0) and the interconnecting cables will decrease the amount of power seen at the EV kit input. Account for these losses when setting the signal generator amplitude. ) Start the MAX00 program by opening its icon in the Start menu. ) Normal device operation can be verified by the Status: Interface Board Operational text in the Interface box. ) Click the POR Reset button on the MAX00 EV kit software GUI. ) Enable the logic analyzer. ) Capture data using the logic analyzer. Tx DAC Setup ) Ensure that a shunt is placed across pins and of jumper JU. ) Connect the clock signal generator to the input of the clock bandpass filter. ) Connect the output of the clock bandpass filter to the EV kit SMA connector labeled J0. ) Connect the output of the clock signal generator to the data generator synchronization input. 0) Connect the first spectrum analyzer to the EV kit SMA connector labeled J (Q channel). ) Connect the second spectrum analyzer to the EV kit SMA connector labeled J (I channel). ) Connect the data generator to J. See the Digital Data Bit Locations section in this document for header connections. ) Turn on the -V power supply. ) Turn on all remaining power supplies. ) Plug the CMOD wall cube into an electrical outlet. ) Enable the signal generator. ) Set the clock signal generator to output a.mhz signal. The amplitude of the generator should be sufficient to produce a dbm signal at the SMA input of the EV kit. Insertion losses due to the seriesconnected filter (step ) and the interconnecting cables will decrease the amount of power seen at the EV kit input. Account for these losses when setting the signal generator amplitude. ) Load the desired test pattern into the data generator. Data clocked on the rising edge of the clock is transmitted to the Q channel. Data clocked on the falling edge of the clock is transmitted to the I channel. ) Start the MAX00 program by opening its icon in the Start menu. 0) Normal device operation can be verified by the Status: Interface Board Operational text in the Interface box. ) Click the POR Reset button on the MAX00 EV kit software GUI. ) Enable the pattern generator. ) Enable the spectrum analyzers. ) Analyze the data on the EV kit outputs (J and J) with the spectrum analyzers.

6 MAX00 Evaluation Kit/Evaluation System Detailed Description of Software User-Interface Panel The user interface (Figure ) is easy to operate: use the mouse, or a combination of the tab and arrow keys to manipulate the software. Each of the buttons corresponds to bits in the command and configuration bytes. By clicking on them, the correct SPI write operation is generated to update the internal registers of the MAX00. Note: Words in bold represent visible items on the graphical user interface (GUI). The software divides EV kit functions into logical blocks. The Interface box indicates the current Device, the Register Address Sent, and the Data Sent/Received for the last write operation. This data is used to confirm proper device operation. Adjust the SPI Clock Frequency through the pulldown box. The controls for the Tx DAC and Auxiliary DACs are accessed through tab sheets. Device Control is accessed at the right-hand side of the main window. Return the EV kit to its power-on-reset state by clicking the POR Reset button. The MAX00 EV kit software features additional functions to simplify operation. Automatic Diagnostics probes the command module board to make sure that a connection exists between the PC and the command module. Device Control Configure the operating mode of the device through the intuitive controls in the Device Control box. Select a mode as outlined in the MAX00 data sheet using the Operating Mode control. For a detailed description of the MAX00 operating modes and their specific names, refer to the Power-Management Modes table in the MAX00 data sheet. When using SPI Tx/Rx Control, ensure that jumper JU is set appropriately. See the Digital Data Direction section in this document for details regarding JU. Tx DAC Controls Adjust the Common-Mode Voltage and the DAC Full- Scale voltage by selecting the desired option from the pulldown box. The DAC I-Offset and Q-Offset voltages can be adjusted in 0.µV/.µV increments by adjusting the appropriate slider in the Tx DAC Offset Control box. The increment value is dependent on the DAC Full- Scale range. A full-scale range of 0mV P-P yields an 0.µV increment. A full-scale range of V P-P yields a.µv increment. Alternatively, a number (specified in millivolts) can be entered in the boxes below each slider. If a number not divisible by 0.0/0. is entered, the software automatically rounds the number to the nearest 0.µV/.µV increment and sends the appropriate data to the MAX00. Figure. MAX00 EV Kit Software Main Window Figure. MAX00 EV Kit Software Auxiliary DAC Control

7 MAX00 Evaluation Kit/Evaluation System Auxiliary DAC Controls Access the MAX00 auxiliary DACs through the Auxiliary DACs tab of the MAX00 EV kit software. Set the output voltage of the desired auxiliary DAC by adjusting the Aux-DAC, Aux-DAC, or Aux-DAC sliders. Enter a number in the edit box below the slider for precise adjustments. Enable each DAC by setting the checkbox below the slider. Simple SPI Commands There are two methods for communicating with the MAX00: through the normal user-interface panel or through the SPI commands available by selecting the -Wire Interface Diagnostic item from the Options pulldown menu. A window is displayed that executes an SPI read/write operation. The SPI (-wire interface) dialog box accepts numeric data in hexadecimal format. Hexadecimal numbers should be prefixed by a $ or 0x. Data entered in the Data bytes to be written: edit box will be sent to the device. Eight-bit hexadecimal numbers should be comma-delimited. Data appearing in the Data bytes received: box is data read from the device. As the MAX00 does not have an SPI read line, ignore any data appearing in this box. Clicking the Send Now button in Figure transmits the hexadecimal numbers 0xA and 0xC. 0x00 and 0x00 are the received values from the device. For a detailed description of SPI communications with the MAX00, refer to the MAX00 data sheet. Detailed Description of Hardware The MAX00 EV kit is a fully assembled and tested circuit board that contains all the components necessary to evaluate the performance of the MAX00 AFE IC. The MAX00 receive ADCs (Rx ADC) accept differential input signals; however, on-board transformers (T, T) convert a readily available single-ended source output to the required differential signal. The input signals of the MAX00 can be measured using a differential oscilloscope probe at headers J and J. The MAX00 transmit DACs (Tx DAC) are buffered with on-board, ultra-low-distortion, split-supply operational amplifiers. A bidirectional driver (U) buffers and level-translates the parallel data bus signals of the MAX00. The parallel data bus of the MAX00 EV kit is accessible at header J. The EV kit is designed as a four-layer PC board to optimize the performance of the MAX00. Separate analog, digital, clock, and buffer power planes minimize noise coupling between analog and digital signals. Differential 00Ω microstrip transmission lines are used for analog ADC inputs and analog DAC outputs, while 0Ω microstrip transmission lines are used for all digital outputs and the clock input. The trace lengths of the ADC input and DAC output paths are well matched to minimize layout-dependent input-signal skew. Power Supplies For optimal performance, the MAX00 EV kit requires separate analog, digital, clock, and buffer power supplies. Power supplies of +.0V and +.V are recommended to power the analog () and digital (O) portions of the MAX00. A separate +.V power supply (BVCC) is used to power the I/O level-translating buffer (U). The clock circuitry (C) is powered by a +.0V power supply. The DAC outputs of the MAX00 are buffered by split-supply op amps. Power the positive rail (VOP) with a +V supply. Power the negative rail (VON) with a -V supply. Figure. MAX00 EV Kit Software -Wire Interface Diagnostics

8 MAX00 Evaluation Kit/Evaluation System MAX00 Power-Down The MAX00 features a global device power-down pin. Jumper JU controls this feature. See Table for jumper configuration. Table. Power-Down Shunt Settings (JU) SHUNT POSITION PD PIN DESCRIPTION -* O Normal operation - D MAX00 powered down *Default configuration: JU (-). Measuring the O Supply Current The level-translating buffer (U) requires a voltage supply on each side of the device. By default, the MAX00 side of the device is connected to O. If the O current is measured at the O and pads of the EV kit, a measurement error will occur due to the extra current flowing into U. To accurately measure O current, connect the MAX00 side of U to BVCC by configuring jumper JU. See Table for jumper configuration. Ensure that BVCC is equal to O, when operating in this mode. Table. O Supply Connections (JU) SHUNT POSITION -* Normal operation - *Default configuration: JU (-). DESCRIPTION O measurement mode; note BVCC must equal O Clock An on-board clock-shaping circuit generates a clock signal from an AC sine-wave signal applied to the CLOCK SMA connector. The input signal should not exceed a magnitude of.v P-P. The frequency of the signal should not exceed.mhz for the MAX00. The frequency of the sinusoidal input signal determines the sampling frequency (f CLK ) of the MAX00. A differential line receiver (U) processes the input signal to generate the CMOS clock signal. The signal s duty cycle can be adjusted with potentiometer R. A clock signal with a 0% duty cycle (recommended) can be achieved by adjusting R until.v is produced across test points TP and TP when the clock voltage supply (C) is set to.0v. The clock signal is available at J- (CLK), which can be used to synchronize the output signal to the logic analyzer. Measure the clock signal with an oscilloscope at TP. Rx ADC Inputs Although the MAX00 accepts differential analog input signals, the EV kit only requires a single-ended analog input signal, with an amplitude of less than.dbm provided by the user. Connect the single-ended sources to J (I channel) and J (Q channel). Insertion losses due to a series-connected filter and the interconnecting cables will decrease the amount of power seen at the EV kit input. Account for these losses when setting the signal generator amplitude. On-board transformers (T-T) convert the single-ended analog input signals and generate differential analog signals at the ADCs differential input pins. The MAX00 also accepts single-ended input signals. See the Configuring for Single- Ended ADC Operation section in this document for details on how to modify the MAX00 EV kit to support this mode of operation. Configuring for Single-Ended ADC Operation The MAX00 can be configured to accept AC-coupled single-ended signals presented at the input. Configure the EV kit to support this mode of operation by completing the steps below: ) Cut the trace at locations R, R, R, and R. ) Install 0Ω resistors at locations R, R, R, R0, R, and R. ) Install kω ± resistors at locations R, R, R, and R. ) Connect the single-ended sources to J (I channel) and J (Q channel). Configure the EV kit for DC-coupled single-ended signals by removing capacitors C and C, removing resistors R and R0, and installing 0Ω resistors at locations R and R. Tx DAC Outputs By default, on-board ultra-low-distortion op amps (U and U) buffer the DAC outputs on the MAX00 EV kit. The op amps convert the differential signal from the MAX00 to a single-ended 0Ω signal. Measure the buffered output signals at J (Q channel) and J (I channel). Measure the differential output of the MAX00 at the IDN/IDP and QDN/QDP pads. Full-scale output, offset voltage, and common-mode voltage functions are controlled through the MAX00 EV kit software.

9 MAX00 Evaluation Kit/Evaluation System Reference The MAX00 features two reference operation modes. The EV kit can be configured to use either the MAX00 internal (.0V) reference or an external user-supplied reference applied at the REFIN pad. The MAX00 generates the REFP and REFN voltages from the selected reference voltage (refer to the MAX00 data sheet for more details). Measure the REFP and REFN voltages at TP and TP, respectively. Jumper JU controls the reference mode. See Table for jumper configuration. Table. Reference Shunt Settings (JU) SHUNT POSITION Installed* Not installed DESCRIPTION Internal reference mode *Default configuration: JU (installed). External reference mode apply an external reference voltage to the REFIN pad Digital Data Header The MAX00 features one 0-bit parallel, bidirectional data bus that transmits/receives the converted analog signals. Refer to the MAX00 data sheet for more details. Digital Data Direction The MAX00 EV kit features an on-board, bidirectional, level-translating buffer in the parallel digital data path. Jumper JU controls the direction of the data bus. See Table for jumper configuration. Table. Output Format Shunt Settings (JU) SHUNT POSITION - -* *Default configuration: JU (-). DESCRIPTION Transmit path enabled; D0 D are inputs Receive path enabled; D0 D are outputs Digital Data Bit Locations A driver (U) buffers the digital I/Os of the MAX00. This driver is able to drive large capacitive loads, which may be present at the logic analyzer connection. The outputs of the buffer are connected to a 0-pin header (J). See Table for bit locations on header J. Table. Digital Data Bit Locations SIGNAL LOCATION TYPE DESCRIPTION D0 J- I/O Data Bit 0 (LSB) D J- I/O Data Bit D J- I/O Data Bit D J- I/O Data Bit D J- I/O Data Bit D J- I/O Data Bit D J- I/O Data Bit D J- I/O Data Bit D J- I/O Data Bit D J- I/O Data Bit (MSB) SHDN J- I/O** Shutdown Status** Tx/Rx J- I/O** Transmit/Receive Status** DR J- Output Data-Ready Signal CLK J- Output Incoming Clock Signal **SHDN and Tx/Rx default to outputs, but can be configured to inputs. See the Configuring for ASIC/FPGA Connection section in this document. Note: All signal directions are with respect to the EV kit. Pins,,,,,, and 0 of J are open. All other pins are connected to D. Configuring for ASIC/FPGA Connection The MAX00 EV kit is designed to be connected to an ASIC or FPGA. To complete this connection, follow the list of instructions below: ) Remove the shunt from jumper JU. ) Remove the shunt from jumper JU. ) Connect ASIC/FPGA to header J (see the Digital Data Bit Locations section in this document for header connections). ) Ensure that the voltage at BVCC matches the ASIC/FPGA I/O voltage. The ASIC/FPGA must control all signals connected to the MAX00, including SHDN and Tx/Rx.

10 MAX00 Evaluation Kit/Evaluation System Jumper JU Jumper JU is reserved and should not be used. A shunt should always be placed across pins - of JU. See Table for jumper configuration. Table. Output Format Shunt Settings (JU) SHUNT POSITION Configuring the Low-Speed DAC Buffers The MAX00 EV kit features on-board configurable buffers. By default, these buffers are configured for unity gain. Measure the buffered voltage at the BDAC, BDAC, and BDAC pads. Measure the unbuffered voltage at the DAC, DAC, and DAC pads. Configure the on-board buffers for a positive (noninverting) gain by performing the following steps: ) Cut the trace at locations R, R, and R. ) Select a value of 0kΩ for resistors R, R, and R. ) Calculate resistors R, R, and R using the equations below. ) Install R, R, and R in their respective locations. where, - Reserved -* Normal operation *Default configuration: JU (-). DESCRIPTION R R x BDAC DAC = R R x BDAC = DAC R R x BDAC = DAC Driving Unbuffered Loads The low-speed buffers (U) on the MAX00 EV kit are optional and if desired can be disconnected from the DAC outputs of the MAX00. Disconnect the buffers from the MAX00 by cutting the trace at locations R, R, and R0. Connect the low-speed DAC loads to the DAC, DAC, and DAC pads on the EV kit. If the load capacitance is between pf and pf, cut the trace and install 0kΩ resistors at locations R, R, and R. Resistors are not required if the load is less than pf. Using an Alternative SPI Interface The MAX00 EV kit provides pads and jumpers that allow an alternative SPI interface to be used. Connect the interface to the CS, SCLK, DIN, and pads. Ensure that the SPI voltages are compatible with the MAX00 working voltages. Refer to the MAX00 data sheet for suitable SPI interface voltages. Remove the shunts from jumper JU. See Table for jumper configuration. Table. Alternative SPI Interface (JU) SHUNT POSITION Not installed DESCRIPTION Normal operation three shunts are installed across pins -, -, and - *Default configuration: JU (-, -, -). Alternative SPI interface no shunts are installed on JU, connect the SPI signals to the CS, SCLK, DIN, and pads BDACx DACx = Desired noninverting gain of buffer R = R = R = 0kΩ 0

11 MAX00 Evaluation Kit/Evaluation System MAX00 U MAX0 U C C C C.µF C C C C J- J- J- J- J- J- J- J- J- J- MOSI CSH MISO SCLKH VMOD VMOD J- J- J- J-0 J- J- J- J- J- J- J- J- J- J-0 J- J- J- J- J- J- J- J- J- J-0 J- J- J- J- J- J-0 C 0µF.V C 0µF.V C 0µF C.0µF C 0µF.V C0 0µF.V C 0µF C.0µF VOP VOP VDN C 0µF.V C 0µF.V C 0µF C.0µF VON C 0µF.V C 0µF.V O D O C 0µF C0.0µF CS CS SCLK SCLK DIN DIN D O D C0.µF C 0 DOUT CS SCLK DIN CSH SCLKH MOSI MISO I/OVCC I/OVCC I/OVCC I/OVCC 0 CS I/OVL EN I/OVL I/OVL I/OVL EN JU- JU- JU J SCLK JU- JU- DIN JU- JU- VMOD O VCC VL N.C. O C0.0µF C.0µF ADC_IN ADC_IN N.C. N.C. TX/RX T/R CLK CLK D0 D0 D D D D 0 D D D D D D D D D D D D D D DR DOUT DR R R REFIN JU C C.0µF REFIN SHDN SHDN COM C 000pF C 0.µF COM COM 0 O O DAC DAC BDAC MAX R R U-B + - DAC R R MAX UNUSED AMPLIFIER U-C DAC BDAC MAX R R U-D + - DAC R R0 VOP C BDAC MAX R R U-A + - DAC R R COM QAN QAP 0 R R0.Ω R R.Ω R J C T C0 pf C pf C R.Ω J R VR R0 R R.Ω J C VR TP TP VR REFP REFN R R R R C 0.µF C 0.µF C 000pF C 000pF C C COM IAP IAN R R.Ω R R.Ω R J C T C pf C pf C R.Ω J J J VR R R R R.Ω J C QDP QDN VON C C.µF VOP C.µF R.Ω R 0kΩ C C C MAX0 U + - QDP QDN C C C R R R R R 0kΩ J IDP IDN VON C C.µF VOP C.µF R.Ω R 0kΩ C C C0 MAX0 U + - IDP IDN C C C R0 R R R R 0kΩ J R 0kΩ R 0kΩ R 0kΩ R0 0kΩ Figure. MAX00 EV Kit Schematic (Sheet of )

12 MAX00 Evaluation Kit/Evaluation System OB VCCB VCCB 0 TX/RX D R L DR SHDN D D D D D D D D D D0 TX/RX DR D D D D D D D D D D U SNAVCH0T U FXLT U MAX B B B B B 0 B B B B B0 B B B B B B B B B B0 C C C C O BVCC O VCCA VCCA 0 DIR RA Ω RA Ω J DIR A CK D D D D D D D D D D0 A A A A A A A A A0 J- J- J- J- J- J- J- J- J- J- J-0 J- J- J- J- J- 0 A A A A A A A 0 0 A A A0 OE OE J- J- J- J- J- J- J- J- J- J-0 J- J- J- J- J-0 J- J- J- J- J- J- J- J- J-0 BVCC CLKO BVCC VCC0 VCC SHDN SHDNH TX/RXH TX/RXH TX/RXH SHDNH BVCC C.0µF C 0µF.V C 0µF.V BVCC BVCC RA 00Ω RA RA RA 00Ω C 0µF D C.0µF C0 0µF.V C 0µF.V C C C 0µF C C CLK CLK0 TP TP C0 C A0 A A A A OE 0 BVCC OB JU JU JU JU Y0 Y Y Y Y VCC J0 C.µF IN- IN- IN+ IN+ C C C C C 0.0µF OUT OUT R R R R0 kω R kω R.0kΩ R.0kΩ R.0kΩ R.Ω R TP Figure. MAX00 EV Kit Schematic (Sheet of )

13 MAX00 Evaluation Kit/Evaluation System Figure. MAX00 EV Kit Component Placement Guide Component Side

14 MAX00 Evaluation Kit/Evaluation System Figure. MAX00 EV Kit PC Board Layout Component Side

15 MAX00 Evaluation Kit/Evaluation System Figure. MAX00 EV Kit PC Board Layout (Inner Layer ) Ground Planes

16 MAX00 Evaluation Kit/Evaluation System Figure. MAX00 EV Kit PC Board Layout (Inner Layer ) Power Planes

17 MAX00 Evaluation Kit/Evaluation System Figure. MAX00 EV Kit PC Board Layout Solder Side

18 MAX00 Evaluation Kit/Evaluation System Figure 0. MAX00 EV Kit Component Placement Guide Solder Side Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 0 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.