MAX12527/MAX12528/MAX12529/ MAX12557/MAX12558/MAX12559 Evaluation Kits

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1 -0; Rev 0; /0 MAX/MAX/MAX/ MAX/MAX/MAX Evaluation Kits General Description The MAX/MAX/MAX/MAX/ MAX/MAX evaluation kits (EV kits) are fully assembled and tested circuit boards that contain all the components necessary to evaluate the performance of this family of -bit and -bit, dual analog-to-digital converters (ADCs). These ADCs accept differential analog input signals. The EV kits generate these signals from user-provided single-ended input sources. The digital outputs produced by the ADCs can be easily sampled with a user-provided high-speed logic analyzer or data-acquisition system. The EV kits operate from.0v and.v power supplies. PART Part Selection Table SAMPLING RATE (Msps) RESOLUTION (Bits) MAXETK MAXETK 0 MAXETK MAXETK MAXETK 0 MAXETK DESIGNATION QTY DESCRIPTION C C 0 Not installed (00) C, C, C, C, C, C, C, C C, C, C, C C0, C C C C0 ±0%, 0V XR ceramic capacitors (00) TDK C00XRA0M.pF ±0.pF, 0V C0G ceramic capacitors (00) TDK C00C0GHRD Low-Voltage and Low-Power Operation On-Board Clock-Shaping Circuitry Option On-Board Output Drivers Fully Assembled and Tested Features Ordering Information PART TEMP RANGE* IC PACKAGE MAXEVKIT 0 C to +0 C TQFN-EP** MAXEVKIT 0 C to +0 C TQFN-EP** MAXEVKIT 0 C to +0 C TQFN-EP** MAXEVKIT 0 C to +0 C TQFN-EP** MAXEVKIT 0 C to +0 C TQFN-EP** MAXEVKIT 0 C to +0 C TQFN-EP** *EV kit PC board temperature range only. **EP = Exposed paddle. Component List DESIGNATION QTY DESCRIPTION C C, C, C C, C0, C, C, C, C C, C, C, C 0µF ±0%,.V tantalum capacitors (C case) AVX TPSCM00R00 0µF ±0%,.V XR ceramic capacitors (00) TDK C0XR0J0M.0µF ±0%, 0V XR ceramic capacitors (00) TDK C0XRA0M Evaluate: MAX///// C, C C.µF ±0%,.V XR ceramic capacitors (00) TDK C0XR0JM C, C 0.0µF ±%, V C0G ceramic capacitors (00) TDK C0C0GE0J C, C C, C0 ±0%,.V XR ceramic capacitors (00) TDK C00XR0J0M C.0µF ±0%,.V XR ceramic capacitor (00) TDK C00XR0J0M Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at ---, or visit Maxim s website at

2 MAX/MAX/MAX/ MAX/MAX/MAX Evaluation Kits Evaluate: MAX///// DESIGNATION QTY DESCRIPTION D Dual Schottky diode (SOT) Central Semiconductor CMPDS Vishay BAS0-0 Diodes Inc. BAS0-0 J, J, J SMA PC mount connectors J, J, J -pin headers J, J Dual-row, 0-pin headers ( x 0) JU JU -pin headers L L R R, R R, R R, R, R0 R EV KIT PART NUMBER MAXEVKIT MAXEVKIT MAXEVKIT MAXEVKIT MAXEVKIT MAXEVKIT EMI filters Murata NFMPC0FHB 0 Not installed (00) R R Ω ±0.% resistors (00) R R0 0Ω ±0.% resistors (00) R R 0 Not installed (00) R, R.Ω ±% resistors (00) R, R 00Ω ±% resistors (00) R 0kΩ potentiometer R R.Ω ±0.% resistors (00) REFERENCE DESIGNATOR U Component List (continued) DESIGNATION QTY DESCRIPTION RA RA T T EV Kit Specific Component List DESCRIPTION 0Ω ±% resistor arrays Panasonic EXB-HV-J : RF transformers Mini-Circuits ADT-WT T : RF transformer Coilcraft TTWB--B TP TP Test points U U, U U See the EV Kit Specific Component List Low-voltage -bit registers (-pin TSSOP) Pericom PIALVTC or Texas Instruments SNAVCDGGR TinyLogic ULP-A buffer (SC0-) Fairchild NCSVP U Ti nylog i c U LP - A i nver ter ( S C 0- ) Fairchild NCWV0P None Shunts None MAX/MAX/MAX/ MAX/MAX/MAX PC board Maxim MAXETK (-pin thin QFN, 0mm x 0mm x 0.mm) Maxim MAXETK (-pin thin QFN, 0mm x 0mm x 0.mm) Maxim MAXETK (-pin thin QFN, 0mm x 0mm x 0.mm) Maxim MAXETK (-pin thin QFN, 0mm x 0mm x 0.mm) Maxim MAXETK (-pin thin QFN, 0mm x 0mm x 0.mm) Maxim MAXETK (-pin thin QFN, 0mm x 0mm x 0.mm)

3 MAX/MAX/MAX/ MAX/MAX/MAX Evaluation Kits Component Suppliers SUPPLIER PHONE FAX WEBSITE AVX Central Semiconductor Coilcraft Diodes Inc Fairchild -- Murata Panasonic Pericom TDK Texas Instruments Note: Indicate that you are using the MAX, MAX, MAX, MAX, MAX, and MAX when contacting these component suppliers. Quick Start Recommended Equipment DC power supplies: Analog ().V, 00mA Digital (O).0V, 0mA Buffers (VLOGIC).0V, 00mA Signal generator with low phase noise and low jitter for clock input signal (e.g., HP/Agilent B) Two signal generators with low phase noise for analog signal inputs (e.g., HP/Agilent B) Logic analyzer or data-acquisition system (e.g., HP/Agilent 00C) Narrow-band analog bandpass filters (e.g., Allen Avionics, K&L Microwave) for input signals and clock signal Digital multimeter Procedure The EV kit is a fully assembled and tested printed circuit (PC) board. Follow the steps below to verify board operation. Do not turn on power supplies or enable signal generators until all connections are completed. ) Verify that shunts are installed in the following locations: JU (-) Independent reference mode JU (-) ADC active (not in power-down mode) JU (-) Outputs in two s-complement format JU (-) Differential clock input JU (-) No clock division JU (-) No clock division ) Connect the clock signal generator to the input of the clock bandpass filter. ) Connect the output of the clock bandpass filter to the SMA connector labeled J. ) Connect the analog input signal generators to the inputs of the desired analog bandpass filters. For best results, connect the bandpass filter directly to the SMA connector and forego any cables in between. ) Connect the output of the analog bandpass filters to the SMA connectors labeled J and J. The analog input signals can be monitored at J and J. Eliminate cables between bandpass filter outputs and SMA connectors. If cables must be used, they should be as short as possible. Add a db to db attenuator between bandpass filter and SMA connectors to control undesired distortion components induced by the signal generator. ) Connect the logic analyzer to headers J and J to collect digitized data from channels A and B. See the Output Bit Locations section in this document for header connections. ) Connect a.v, 00mA power supply to and connect its ground terminal to the pad. ) Connect a.0v, 0mA power supply to O and connect its ground terminal to the pad. ) Connect a.0v, 00mA power supply to VLOGIC and connect its ground terminal to the pad. 0) Short the VCLK pad to the corresponding pad. Note: The VCLK supply is only required when the data converter is operating in single-ended clock mode. See the Configuring the EV Kit for Single-Ended Clock Operation section in this document for further details. Evaluate: MAX/////

4 MAX/MAX/MAX/ MAX/MAX/MAX Evaluation Kits Evaluate: MAX///// ) Turn on all the power supplies. ) Enable the signal generators. ) Set the clock signal generator to the desired clock frequency. See the Part Selection Table for the appropriate frequency settings for each EV kit. The amplitude of the generator should be sufficient to produce a dbm signal at the SMA input of the EV kit. Insertion losses due to the series-connected filter (step ) and the interconnecting cables decrease the amount of power seen at the EV kit input. Account for these losses when setting the signal generator amplitude. ) Set the analog input signal generators to output the desired test frequency. The amplitude of the generator should produce a signal that is no larger than.dbm as measured at the SMA input of the EV kit. Insertion losses due to the series-connected filter (step ) and the interconnecting cables decrease the amount of power seen at the EV kit input. Account for these losses when setting the signal generator amplitude. Also account for the attenuation from the db to db attenuator. ) All signal generators should be phase-locked to each other. ) Enable the logic analyzer. ) Collect data using the logic analyzer. Detailed Description The EV kit is a fully assembled and tested circuit board that contains all the components necessary to evaluate the performance of the MAX, MAX, MAX, MAX, MAX, or MAX. The ADCs accept differential input signals; however, onboard transformers (T T) convert a readily available single-ended source output to the required differential signal. The input signals of the ADC can be measured using a differential oscilloscope probe at headers J and J. Output drivers (U and U) buffer the output signals of the data converter. The digital outputs of the EV kit are accessible at headers J and J. The EV kits are designed as a four-layer PC board to optimize the performance of this family of ADCs. Separate analog, digital, clock, and buffer power planes minimize noise coupling between analog and digital signals. 00Ω differential microstrip transmission lines are used for analog and clock inputs. 0Ω microstrip transmission lines are used for all digital outputs. The trace lengths of the 00Ω differential input lines are matched to within a few thousandths of an inch to minimize layout-dependent input-signal skew. Power Supplies For best performance, the EV kits require separate analog, digital, clock, and buffer power-supply sources. Individual.V and.0v power supplies are recommended to power the analog () and digital (O) portions of the converter. A separate.0v power supply (VLOGIC) is used to power the output buffers (U, U) of the EV kit. The on-board clock circuitry (VCLK) is powered by a.v power supply. The VCLK supply is only required when the ADC is operating in single-ended clock mode. See the Configuring the EV Kit for Single-Ended Clock Operation section for further details. Converter Power-Down The MAX, MAX, MAX, MAX, MAX, and MAX each feature an active-high global device power-down pin. Jumper JU controls this feature. See Table for shunt positions. Table. Power-Down Shunt Settings (JU) SHUNT POSITION PD PIN DESCRIPTION - O ADC powered down -* ADC active (normal operation) *Default configuration: JU (-). Clock Additionally, the data converter allows for either differential or single-ended signals to drive the clock inputs. The MAX/MAX/MAX/MAX/ MAX/MAX EV kits support both methods. In single-ended operation, the clock signal is applied to the ADC through a buffer (U). In differential mode, an on-board transformer converts a user-provided singleended analog input and generates a differential analog signal, which is then applied to the ADC s input pins. Jumper JU controls the ADC clock input. See Table for jumper configuration. Table. Clock Selection Shunt Settings (JU) SHUNT POSITION DIFFCLK/ SECLK PIN DESCRIPTION -* O Differential clock mode. - *Default configuration: JU (-). Single-ended clock mode. S ee the C onfi g ur i ng the E V Ki t for S i ng l e- E nd ed C l ock Op er ati on secti on for fur ther d etai l s.

5 MAX/MAX/MAX/ MAX/MAX/MAX Evaluation Kits Configuring the EV Kits for Single-Ended Clock Operation To configure the MAX/MAX/MAX/ MAX/MAX/MAX EV kits for singleended clock operation, the following modifications must be made to the clock circuit: ) Cut the trace at locations R, R, and R. ) Install 0Ω resistors at locations R0, R, and R. ) Install a.ω ±% resistor at location R. ) Connect a.v power supply to VCLK (needs to be capable of sourcing up to 0mA output current). Connect the ground terminal of this supply to. In single-ended clock configuration, potentiometer R can be utilized to control the duty cycle of the clock input signal. Measure the clock input at J and adjust R until the desired duty cycle is achieved. Clock-Divider Control The MAX, MAX, MAX, MAX, MAX, and MAX each feature internal divide-by-/divide-by- clock-divider circuitry (DIV, DIV). Jumpers JU and JU control this circuitry. Refer to the individual ADC data sheets for a detailed explanation of the internal clock divider. See Table for jumper configuration. Table. Clock-Divider Shunt Settings (JU, JU) SHUNT POSITION PIN CONNECTION DESCRIPTION JU JU DIV DIV -* -* Normal clock mode - - O Divide-by- clock mode (DIV) - - O Divide-by- clock mode (DIV) - - O O INVALID *Default configuration: JU (-), JU (-). Input Signal Although this family of ADCs accepts differential analog input signals, the EV kit only requires single-ended analog input signals, with amplitudes less than.dbm. Insertion losses due to a series-connected filter and the interconnecting cables decrease the amount of power seen at the EV kit input. Account for these losses when setting the signal generator amplitude. On-board transformers (T T) convert the single-ended analog input signals and generate the recommended differential analog signals at the ADCs differential input pins. Optimizing the Analog Input Network for Different Input Frequencies The EV kits are designed for excellent AC performance across a broad MHz to 00MHz input frequency range. The design can be further optimized by adjusting components C C0 and R R. See Table for the appropriate component values for specific input frequency ranges. Table. Component Selection for Optimized AC Performance INPUT FREQUENCY RANGE (MHz) C C0 COMPONENT VALUES (pf) to 00*. < 0 to 0 0 to to 0 >. to 0 *Default EV kit configuration. Reference The MAX, MAX, MAX, MAX, MAX, and MAX feature numerous reference operation modes. The default EV kit configuration connects the ADC s internal.0v reference output to the reference input. In this case, the converter generates the REFN, REFP, and COM voltages from this input (refer to the individual ADC s data sheet for a more detailed explanation). To apply a user-supplied reference, cut the trace at location R and connect the desired external reference to the REFIN pad. Alternatively, the EV kit can be configured to use a divided internal reference value. If the desired reference voltage is less than.0v, cut the trace at location R and install resistors in locations R and R. Calculate the resistor values from the equations below: V R = REF RT VREFOUT R R COMPONENT VALUES (Ω) R = R T - R where: V REF = desired reference voltage V REFOUT = ADC s internal reference voltage of.0v R T = ADC s minimum reference resistance 0kΩ Evaluate: MAX/////

6 MAX/MAX/MAX/ MAX/MAX/MAX Evaluation Kits Evaluate: MAX///// Shared Reference Mode To maximize isolation between the two input channels, the MAX, MAX, MAX, MAX, MAX, and MAX feature two independent references. To improve channel matching this family of ADCs provides a mode where both input channels share the same reference. Jumper JU controls this shared reference feature. See Table for the desired jumper configuration. Table. Shared Reference Shunt Settings (JU) SHUNT POSITION SHREF PIN - O -* *Default configuration: JU (-). DESCRIPTION Shared reference mode. Install 0Ω resistors at locations R and R. Independent reference mode. Remove any component at locations R and R. Alternative Reference Mode The MAX, MAX, MAX, MAX, MAX, and MAX derive their REFP, REFN, and COM voltages from the REFIN input. To override these derived voltages, follow the board modifications given below. ) Cut the trace at location R. ) Remove resistor R (not installed by default). ) Connect the REFIN pad to. ) Apply the desired voltages to test points TP TP. See Table for a detailed description of test point connections. Table. Reference Test Point Connections TEST POINT CONNECTION DESCRIPTION TP COMA Common-mode voltage for channel A. TP COMB Common-mode voltage for channel B. TP REFPA Positive voltage reference terminal for channel A. TP REFNA Negative voltage reference terminal for channel A. TP REFPB Positive voltage reference terminal for channel B. TP REFNB Negative voltage reference terminal for channel B. Note: Refer to the respective ADC data sheet for REFP, REFN, and COM voltage ranges. Output Signal The MAX, MAX, and MAX feature two -bit, parallel, CMOS-compatible digital outputs that transmit the converted analog input signals. The higherresolution MAX, MAX, and MAX feature two -bit, parallel, CMOS-compatible digital outputs that transmit the converted analog input signals. Each set of -bit or -bit digital outputs also includes a clock (CLK) bit and overrange (DORA/B) bit to accommodate data synchronization and error detection. See the Output Bit Locations section for more details on how to configure these -bit and -bit converter outputs. Output Format Set the digital output coding to either two s-complement or Gray code, by configuring jumper JU. See Table for the jumper configuration. Table. Output Format Shunt Settings (JU) SHUNT POSITION G/T Pin - O -* *Default configuration: JU (-). DESCRIPTION Gray code selected. Digital output format is Gray code. Two s complement selected. Digital output format is two s complement.

7 MAX/MAX/MAX/ MAX/MAX/MAX Evaluation Kits Output Bit Locations Two drivers (U and U) buffer the digital outputs of the individual ADCs. These drivers can drive large capacitive loads, which may be present at the logic analyzer connection. The outputs of the buffers are connected to 0-pin headers J and J. See Table (-bit ADCs) and Table (-bit ADCs) for bit locations of headers J and J. Table. Output Bit Locations (MAX, MAX, MAX -Bit, Dual ADCs) SIGNAL A CHANNEL B DESCRIPTION D0 J- J- Data Bit 0 (LSB) D J- J- Data Bit D J- J- Data Bit D J- J- Data Bit D J- J- Data Bit D J- J- Data Bit D J- J- Data Bit D J- J- Data Bit D J- J- Data Bit D J- J- Data Bit D0 J- J- Data Bit 0 D J- J- Data Bit D J- J- Data Bit D J- J- Data Bit (MSB) DOR J- J- Over Range Bit CLK J- J- Clock Bit Note: Pins,,,,, and 0 of J and pins,,,,,, and 0 of J are open. All other pins that are not listed in Table are connected to. Note: Silkscreen markings on the EV kit PC board indicate pin markings for the MAX, MAX, and MAX. These pin markings are not valid for the MAX, MAX, or MAX. Use the connections outlined in Table. Table. Output Bit Locations (MAX, MAX, MAX -Bit, Dual ADCs) SIGNAL A CHANNEL B DESCRIPTION J- J- J- J- D0 J- J- Data Bit 0 (LSB) D J- J- Data Bit D J- J- Data Bit D J- J- Data Bit D J- J- Data Bit D J- J- Data Bit D J- J- Data Bit D J- J- Data Bit D J- J- Data Bit D J- J- Data Bit D0 J- J- Data Bit 0 D J- J- Data Bit (MSB) DOR J- J- Over Range Bit CLK J- J- Clock Bit Note: Pins,,,,, and 0 of J and pins,,,,,, and 0 of J are open. All other pins that are not listed in Table are connected to. Evaluate: MAX/////

8 MAX/MAX/MAX/ MAX/MAX/MAX Evaluation Kits J C R R R T R C R Ω 0.% R0 Ω 0.% R Evaluate: MAX///// O R 0Ω 0.% R C.pF R0.Ω 0.% 0 O O O TP R R R0 R O O O DORA DA DA DA DA0 DA DA DA DA DA DA DA DA DA DA0 DAV DORB DB DB DB DB0 DB DB DB DB DB DB DB DB DB DB0 0 DIV DIV DIFFCLK/SECLK O 0 0 DORA DA DA DA DA0 DA DA DA DA DA DA DA DA DA DA0 LATCH DORB DB DB DB DB0 DB DB DB DB DB DB DB DB DB DB0 O O J R C R R T R C R Ω 0.% R Ω 0.% REFIN R T R T R C.µF COMA R C C R 0Ω 0.% R 0Ω 0.% R R0 0Ω 0.% R R R TP R R C0 C C C C C C.µF C.µF C0.pF COMB R.Ω 0.% R C C C.pF R.Ω 0.% R C.pF R.Ω 0.% R R J J CLKN CLKP TP TP COMA COMB C TP TP 0 0 INAP COMA INAN INBN COMB INBP REFOUT REFIN CLKN CLKP REFPA REFNA REFNB REFPB SHREF PD G/T U MAX MAX MAX JU JU JU JU JU JU Figure. MAX/MAX/MAX EV Kit Schematic (Sheet of )

9 Evaluate: MAX///// MAX/MAX/MAX/ MAX/MAX/MAX Evaluation Kits O C 0µF.V C 0µF.V C0 0µF C.0µF C.µF C.µF C.µF C0 C C O L C 0µF.V C 0µF.V C 0µF C.0µF C C C.µF C.µF J- J 0-PIN HEADER J- J- J- J-0 J- J- J- J- J-0 J- J- J- 0 D D D D D D D D Q Q Q Q Q Q Q Q D D D D D D D D DA DA DA DA DA DA DA DA0 DORA DA DA DA DA0 DA DA 0 OE Q Q Q Q Q Q Q Q CLK CLK U PIALVTC 0 0 RA 0Ω RA 0Ω RA 0Ω RA 0Ω J- J- J- J- J- J- J- J- J- J- J- J- J- J- J-0 J- J- J- J- J- J- J- J- J- J-0 CLK LATCH LATCH VLOGIC J- J- L OE Figure. MAX/MAX/MAX EV Kit Schematic (Sheet of )

10 Evaluate: MAX///// MAX/MAX/MAX/ MAX/MAX/MAX Evaluation Kits 0 J- J 0-PIN HEADER J- J- J- J- J- J- 0 D D D D D D D D Q Q Q Q Q Q Q Q D D D D D D D D DB DB DB DB DB DB DB0 DB DB DB DB0 DB DB DB 0 OE Q Q Q Q Q Q Q Q CLK CLK U PIALVTC 0 0 RA 0Ω RA 0Ω RA 0Ω RA 0Ω J- J- J- J- J- J- J- J-0 J- J- J- J- J-0 J- J- J- J- J- J-0 J- J- J- J- J- J- J- J- J- J-0 J- CLK LATCH LATCH VLOGIC A Y OE U NCSV C.0µF VLOGIC J- J- J- DORB OE VLOGIC C 0µF.V C 0µF.V C 0µF C 0µF C.0µF C C C C0 C 0µF C C C C VLOGIC L Figure. MAX/MAX/MAX EV Kit Schematic (Sheet of )

11 MAX/MAX/MAX/ MAX/MAX/MAX Evaluation Kits Evaluate: MAX///// J C R R R T R C R Ω 0.% R0 Ω 0.% R O R 0Ω 0.% R C.pF R0.Ω 0.% 0 O O O TP R R R0 R O O O DORA DA DA0 DA DA DA DA DA DA DA DA DA DA0 DAV DORB DB DB0 DB DB DB DB DB DB DB DB DB DB0 0 DIV DIV DIFFCLK/SECLK O 0 0 DORA DA DA0 DA DA DA DA DA DA DA DA DA DA0 LATCH DORB DB DB0 DB DB DB DB DB DB DB DB DB DB0 O O J R C R R T R C R Ω 0.% R Ω 0.% REFIN R T R T R C.µF COMA R C C R 0Ω 0.% R R 0Ω 0.% R R0 0Ω 0.% R R TP R C0 C C C C0 R.pF R.Ω 0.% C C C.µF C.µF COMB R C C C.pF R.Ω 0.% R C.pF R.Ω 0.% R R J J CLKN CLKP TP TP COMA COMB C TP TP 0 0 INAP COMA INAN INBN COMB INBP REFOUT REFIN CLKN CLKP REFPA REFNA REFNB REFPB SHREF PD G/T U MAX MAX MAX JU JU JU JU JU JU Figure. MAX/MAX/MAX EV Kit Schematic (Sheet of )

12 Evaluate: MAX///// MAX/MAX/MAX/ MAX/MAX/MAX Evaluation Kits O C 0µF.V C 0µF.V C0 0µF C.0µF C.µF C.µF C.µF C0 C C O L C 0µF.V C 0µF.V C 0µF C.0µF C C C.µF C.µF J- J 0-PIN HEADER J- J- J- J-0 J- J- J- J- J-0 J- J- J- 0 D D D D D D D D Q Q Q Q Q Q Q Q D D D D D D D D DA DA DA DA DA DA0 DORA DA DA0 DA DA DA DA 0 OE Q Q Q Q Q Q Q Q CLK CLK U PIALVTC 0 0 RA 0Ω RA 0Ω RA 0Ω RA 0Ω J- J- J- J- J- J- J- J- J- J- J- J- J- J- J-0 J- J- J- J- J- J- J- J- J- J-0 CLK LATCH LATCH VLOGIC J- J- L OE Figure. MAX/MAX/MAX EV Kit Schematic (Sheet of )

13 Evaluate: MAX///// MAX/MAX/MAX/ MAX/MAX/MAX Evaluation Kits J- J 0-PIN HEADER J- J- J- J- J- J- 0 D D D D D D D D Q Q Q Q Q Q Q Q D D D D D D D D DB DB DB DB DB0 DB DB0 DB DB DB DB DB 0 OE Q Q Q Q Q Q Q Q CLK CLK U PIALVTC 0 0 RA 0Ω RA 0Ω RA 0Ω RA 0Ω J- J- J- J- J- J- J- J-0 J- J- J- J- J-0 J- J- J- J- J- J-0 J- J- J- J- J- J- J- J- J- J-0 J- CLK LATCH LATCH VLOGIC A Y OE U NCSVP C.0µF VLOGIC J- J- J- DORB OE VLOGIC C 0µF.V C 0µF.V C 0µF C 0µF C.0µF C C C C0 C 0µF C C C C VLOGIC L Figure. MAX/MAX/MAX EV Kit Schematic (Sheet of )

14 MAX/MAX/MAX/ MAX/MAX/MAX Evaluation Kits Evaluate: MAX///// J R C R R 00Ω % R 0kΩ R 00Ω % R0 VCLK T VCLK U A U B C 0.0µF R.Ω % D R.Ω % C 0.0µF C 0.0µF R R R J R CLKN CLKP VCLK VCLK L C 0µF.V C 0µF.V C 0µF C µf Figure. MAX/MAX/MAX/MAX/MAX/MAX EV Kit Schematic (Sheet of )

15 MAX/MAX/MAX/ MAX/MAX/MAX Evaluation Kits Evaluate: MAX///// Figure. MAX/MAX/MAX/MAX/MAX/MAX EV Kit Component Placement Guide Component Side

16 MAX/MAX/MAX/ MAX/MAX/MAX Evaluation Kits Evaluate: MAX///// Figure. MAX/MAX/MAX/MAX/MAX/MAX EV Kit PC Board Layout Component Side

17 MAX/MAX/MAX/ MAX/MAX/MAX Evaluation Kits Evaluate: MAX///// Figure 0. MAX/MAX/MAX/MAX/MAX/MAX EV Kit PC Board Layout (Inner Layer ) Ground Planes

18 MAX/MAX/MAX/ MAX/MAX/MAX Evaluation Kits Evaluate: MAX///// Figure. MAX/MAX/MAX/MAX/MAX/MAX EV Kit PC Board Layout (Inner Layer ) Power Planes

19 MAX/MAX/MAX/ MAX/MAX/MAX Evaluation Kits Evaluate: MAX///// Figure. MAX/MAX/MAX/MAX/MAX/MAX EV Kit PC Board Layout Solder Side

20 MAX/MAX/MAX/ MAX/MAX/MAX Evaluation Kits Evaluate: MAX///// Figure. MAX/MAX/MAX/MAX/MAX/MAX EV Kit PC Board Component Placement Guide Solder Side Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 0 Maxim Integrated Products, 0 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.