MAX1434/MAX1436/MAX1437/MAX1438 Evaluation Kits

Transcription

1 9-7; Rev ; 8/0 MAX/MAX/MAX7/MAX8 General Description The MAX/MAX/MAX7/MAX8 evaluation kits (EV kits) are fully assembled and tested circuit boards that contain all the components necessary to evaluate the performance of this family of octal 0-/- bit analog-to-digital converters (ADCs). These ADCs accept differential analog input signals. The EV kits generate these signals from user-provided singleended input sources. The EV kits digital outputs can be easily sampled with a user-provided high-speed logic analyzer or data-acquisition system. The EV kits also feature an on-board deserializer to simplify integration with standard logic analysis systems. The EV kits operate from.8v and.v (plus.v if the FPGA is used) power supplies and include circuitry that generates a clock signal from an AC signal provided by the user. DESIGNATION QTY DESCRIPTION C C8, C0, C, C, C7 C, C8 C8, C9, C0, C7 C C9, C9 C, C, C77, C78, C80, C9, C9, C C7, C C C0, C C7 C C8, C C 8 0 Part Selection Table PART NUMBER BITS SPEED (Msps) MAXECQ+D 0 0 MAXECQ+D 0 MAX7ECQ+D 0 MAX8ECQ+D +Denotes lead(pb)-free and RoHS compliant. D = Dry Pack. ±0%, 0V XR ceramic capacitors (00) TDK C00XRA0K ±0%,.V XR ceramic capacitors (00) TDK C00XR0J0K Not installed, ceramic capacitors (00) 9pF ±%, 0V C0G ceramic capacitors (00) TDK C00C0GH90J Features Low-Voltage and Low-Power Operation Optional On-Board Clock-Shaping Circuitry Serial Scalable Low-Voltage Signaling (SLVS)/Low-Voltage Differential Signaling (LVDS) Outputs On-Board L Differential Output Drivers On-Board Deserializer LVDS Test Mode Fully Assembled and Tested PART MAXEVKIT MAXEVKIT MAX7EVKIT MAX8EVKIT Ordering Information TYPE EV Kit EV Kit EV Kit EV Kit Component List DESIGNATION QTY DESCRIPTION C, C, C7, C8 C89, C C8, C9, C0, C C, C, C, C90, C9, C 8 0µF ±0%,.V tantalum capacitors (C-case) AVX TPSC7M00R00 0 Not installed, capacitors (C-case) C C, C7 C7 C7 C7, C C 0 0µF ±0%, 0V XR ceramic capacitors (0) TDK CXRA0K.µF ±0%,.V XR ceramic capacitor (00) TDK C08XR0JM 0.0µF ±0%, V X7R ceramic capacitors (00) TDK C00X7RE0K Not installed, ceramic capacitors (00) Evaluate: MAX/MAX/MAX7/MAX8 Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim s website at

2 MAX/MAX/MAX7/MAX8 Evaluate: MAX/MAX/MAX7/MAX8 DESIGNATION QTY DESCRIPTION C79, C8, C C9 C 8 C D 0µF ±0%, V XR ceramic capacitors (00) TDK C08XR0G0K ±0%,.V XR ceramic capacitors (00) TDK C00XR0J0M 00µF ±0%,.V XR ceramic capacitor (0) TDK CXR0J07M Dual Schottky diode (SOT) Central Semi CMPDS or Diodes Inc. BAS70-0 D, D Green surface-mount LEDs (00) 0 7, CLOCK 9 SMA PC-mount vertical connectors J J8, JU 9 -pin headers J9 J, J Dual-row, 0-pin ( x 0) headers J 9-pin header JU JU, JU -pin headers JU Dual-row, 8-pin ( x ) header N R R8, R R, R R7 R9 R, R R, R77 R8, R87 R9, R98 R7 R, R8 R R, R0 R R7 R, R7, R7, R7, R8 R8 Digital logic n-channel MOSFET (SOT) Central Semi N700 0 Not installed, resistors (00) 0 Not installed, resistors (00) 9 ± resistors (00) 0 ± resistors (00) 0Ω ± resistors (080) Component List (continued) DESIGNATION QTY DESCRIPTION R R0, R00 R0 0 00Ω ± resistors (00) R 00kΩ potentiometer, 9-turn, /8in R, R, R.0kΩ ± resistors (00) R kω potentiometer, 9-turn, /8in R kω ± resistor (00) R7.0kΩ ± resistor (00) R9, R9.7kΩ ±% resistors (00) R9, R97 0Ω ±% resistors (0) R99 Ω ± resistor (00) R0 0kΩ ±% resistor (00) SW Momentary contact switch T T8 8 TP TP8, TP, TP, TP : 800MHz RF transformers Mini-Circuits ADT-WT 0 Test points, not installed TP9 TP PC test points (red) TP PC test point (black) U See EV kit specific component list U U U U U Single LVDS line receivers (8 SO) Maxim MAX9ESA Low-noise, low-distortion op amp ( SOT) Maxim MAX0EUK TinyLogic UHS dual inverter ( SC70) Fairchild NC7WZ0PX Virtex II platform FPGA ( FGBGA) Xilinx XCV80-FGC or Xilinx XCV80-FGI PROM (SO-0) Xilinx XC8V0SO0C U7 U 0 LVDS/anything-to-L translators (8 µmax ) Maxim MAX97EUA None Shunts (JU JU) None PCB: MAX//7/8 EVALUATION KIT µmax is a registered trademark of Maxim Integrated Products, Inc.

3 MAX/MAX/MAX7/MAX8 EV KIT PART NUMBER DESIGNATION DESCRIPTION MAXEVKIT MAXEVKIT MAX7EVKIT MAX8EVKIT Quick Start Recommended Equipment DC power supplies: Clock (CVDD).V, 00mA Analog ().8V, 00mA Digital ().8V, 0mA Optional Buffers ().V, 00mA Deserializer Core (VD.).V, 00mA Deserializer I/O (VD.).V, 00mA Signal generator with low phase noise and low jitter for clock input signal (e.g., HP 8A, HP 8B) Signal generator for analog signal inputs (e.g., HP 8A, HP 8B) Logic analyzer or data-acquisition system (e.g., HP 00C, TLA7) Analog bandpass filters (e.g., Allen Avionics, K&L Microwave) for input signal and clock signal Digital voltmeter U EV Kit Component List MAXECQ+D (00 TQFP-EP mm x mm x mm) MAXECQ+D (00 TQFP-EP mm x mm x mm) MAX7ECQ+D (00 TQFP-EP mm x mm x mm) MAX8ECQ+D (00 TQFP-EP mm x mm x mm) Component Suppliers SUPPLIER PHONE WEBSITE AVX Corporation Central Semiconductor Corp Diodes Incorporated Fairchild Semiconductor Corp Mini-Circuits TDK Corp Note: Indicate that you are using the MAX, MAX, MAX7, or MAX8 when contacting these component suppliers. Procedure The EV kit is a fully assembled and tested surfacemount board. Follow the steps below to verify board operation. Do not turn on power supplies or enable signal generators until all connections are completed. ) Verify that shunts are installed in the following locations: JU (pins -) single termination JU (pins -) LVDS outputs JU (pins -) normal operation JU (pins -) ADC enabled JU7 (pins -) two s-complement output JU8 (pins -) FPGA enabled JU9, JU0, JU (pins -) channels 0 output from FPGA JU (pins -) internal reference enabled JU (not installed) disconnect external reference buffer ) Verify that shunts are installed in the following locations for configuring the specific EV kit: a) JU (pins -), JU (pins -), JU (pins -) 9MHz to 0MHz clock frequency range for the MAX EV kit. Evaluate: MAX/MAX/MAX7/MAX8

4 MAX/MAX/MAX7/MAX8 Evaluate: MAX/MAX/MAX7/MAX8 b) JU (pins -), JU (pins -), JU (pins -).MHz to 0MHz clock frequency range for the MAX EV kit. c) JU, JU, JU (pins -) MHz to 0MHz clock frequency range for the MAX7 EV kit. d) JU, JU, JU (pins -) MHz to MHz clock frequency range for the MAX8 EV kit. ) Connect the clock signal generator to the input of the clock bandpass filter. ) Connect the output of the clock bandpass filter to the clock SMA connector. ) Connect the analog input signal generator to the input of the analog bandpass filter. ) Connect the output of the analog bandpass filter to either one of the SMA connectors labeled 0 7. The analog input signals can also be monitored at the -pin headers J J8. Note: All eight channels can be operated independently or simultaneously. 7) Connect the logic analyzer to either header J9 (SLVS- or LVDS-compatible signals) or J0 J (deserialized.v CMOS-compatible signals). See the Output Bit Locations section in this document for header connections. 8) Connect the.8v, 00mA power supply to. Connect the ground terminal of this supply to. 9) Connect the.8v, 0mA power supply to. Connect the ground terminal of this supply to. 0) Connect the.v, 00mA power supply to CVDD. Connect the ground terminal of this supply to. ) Connect the.v, 00mA power supply to. Connect the ground terminal of this supply to. ) Connect the.v, 00mA power supply to VD_. Connect the ground terminal of this supply to. ) Connect the.v, 00mA power supply to VD_. Connect the ground terminal of this supply to. ) Turn on the VD_ power supply. ) Turn on the VD_ power supply. ) Verify that the PROGRAMMG LED (D) and the LOCKED LED (D) are off. 7) Turn on the remaining power supplies. 8) Enable the signal generators. Set the clock signal generator to output as specified to configuration signal, with a.v P-P amplitude or higher. Set the analog input signal generators to output the desired frequency with an amplitude.v P-P. All signal generators should be phase-locked. 9) Verify that the PROGRAMMG LED (D) is off. 0) Momentarily press switch SW and verify that the LOCKED LED (D) is on. ) Enable the logic analyzer. ) Collect data using the logic analyzer. Detailed Description of Hardware The EV kit is a fully assembled and tested circuit board that contains all the components necessary to evaluate the performance of the MAX8, MAX7, MAX, or MAX. The ADCs accept differential input signals; however, on-board transformers (T T8) convert the singleended signals applied to the 0 7 SMA connectors, to the required differential signal. The input signals of the ADC can be measured using a differential oscilloscope probe at headers J J8. Output level translators (U7 U) buffer and convert the SLVS or LVDS output signals of the ADC to higher voltage L signals, which can be captured by a wide variety of logic analyzers. The SLVS/LVDS output signals are accessible at header J9 and the L output signals are accessible at header J. The EV kit PC board is designed as a six-layer board to optimize performance of the ADC. Separate analog, digital, clock, and buffer power planes minimize noise coupling between analog and digital signals. 0Ω coplanar transmission lines are used for analog and clock inputs. 00Ω differential coplanar transmission lines are used for all digital LVDS outputs. All differential outputs are terminated with 00Ω termination resistors between the true and complementary digital outputs. The trace lengths of the 00Ω differential SLVS/LVDS lines are matched to within a few thousands of an inch to minimize layout-dependent data skew. Power Supplies For best performance, the EV kit requires separate analog, digital, clock, and buffer power supplies. Two.8V power supplies are used to power the analog () and digital () portion of the ADC. The clock circuitry (CVDD) is powered by a.v power supply. A separate.v power supply () is used to power the output buffers (U7 U) of the EV kit..v (VD_) and.v (VD_) power supplies are required to power the deserializer circuit.

5 MAX/MAX/MAX7/MAX8 Power-Down Jumper JU controls the power-management feature of data converter U. See Table for jumper JU shunt positions. Table. Power-Down Jumper Settings (JU) SHUNT POSITION POWER-DOWN CONNECTIONS - ADC disabled -* ADC enabled *Default configuration: JU (-). EV KIT FUNCTION Clock By default, the user-provided AC-coupled clock signal applied to the EV kit CLOCK SMA connector is buffered on board with two inverters (U). In this mode, diode D limits the amplitude of the clock signal. Overdriving the clock input can increase the slew rate of the differential signal, thereby reducing clock jitter. The frequency of the signal should not exceed the maximum sampling rate of the ADC. The sinusoidal input signal frequency (f CLK ) determines the sampling rate of the ADC. The clock signal applied to the ADC can be observed at test point TP0. Optional Clock-Shaping Circuit The EV kit also features an optional on-board clockshaping circuit that generates a clock signal with variable duty cycle from the AC-coupled sine-wave signal applied to the CLOCK SMA connector. The MAX9 differential line receiver (U) processes the clock input signal and generates the required CMOS clock signal. To use this circuitry, cut the trace on the printed circuit (PC) board at R78 and install 0Ω resistors at R and R77. The signal s duty cycle can be adjusted with potentiometer R. With a.v clock supply voltage (CVDD), a clock signal with a 0% duty cycle (recommended) can be achieved by adjusting R until a voltage of.v is produced across test points TP and TP. PLL Frequency Mode Selection When driving the EV kit with clock signals lower than the maximum specified sampling rate of the ADC, the phased-locked-loop (PLL) circuit of the ADC must be set accordingly. Refer to the PLL Inputs (PLL0 PLL) section in the ADC data sheet for further details about the operation of the internal PLL. Jumpers JU, JU, and JU control the PLL mode of the ADC. See Tables,,, or for shunt positions. Configure jumpers JU, JU, and JU accordingly and ensure that the clock signal frequency falls between the minimum and maximum limits listed in Table through Table. Table. MAX PLL Jumper Settings (JU, JU, JU) SHUNT POSITION JU (PLL) JUMPER JU (PLL) JU (PLL) CLOCK PUT RANGE (MHz) M MAX Unused -* -* -* *Default configuration: JU, JU (-), JU (-). Table. MAX PLL Jumper Settings (JU, JU, JU) SHUNT POSITION JU (PLL) JUMPER JU (PLL) JU (PLL) CLOCK PUT RANGE (MHz) M MAX Unused -* -* -* *Default configuration: JU, JU (-), JU (-). Evaluate: MAX/MAX/MAX7/MAX8

6 MAX/MAX/MAX7/MAX8 Evaluate: MAX/MAX/MAX7/MAX8 Table. MAX7 PLL Jumper Settings (JU, JU, JU) SHUNT POSITION SHUNT POSITION JU (PLL) JU (PLL) JUMPER JU (PLL) Table. MAX8 PLL Jumper Settings (JU, JU, JU) JUMPER JU (PLL) JU (PLL) JU (PLL) CLOCK PUT RANGE (MHz) M MAX -* -* -* *Default configuration: JU, JU, JU (-). CLOCK PUT RANGE (MHz) M MAX -* -* -* *Default configuration: JU, JU, JU (-). Input Signal Although the ADC accepts differential analog input signals, the EV kit only requires a single-ended analog input signal with an amplitude of less than.v P-P provided by the user. On-board transformers (T T8) convert the single-ended analog input signal and generate differential analog signals at the ADCs differential input pins. Connect the single-ended analog input signals to SMA connectors 0 7 for channel 0 to channel 7, respectively. Table. Reference Jumper Settings (JU) SHUNT POSITION REFADJ P CONNECTION Reference Voltage The EV kit can be configured to use the ADC s.v internal reference, or a stable, low-noise, external reference. Use the x header JU to configure the desired reference mode. See Table for the appropriate shunt settings. Output Signal The ADC features eight serial LVDS-compatible digital outputs. Each output transmits the converted analog input signals of channels 0 through 7. Two additional outputs (CLK and FRAME) are provided for data synchronization. Refer to the MAX, MAX, MAX7, or MAX8 data sheet for more details. Output Format The digital output coding can be chosen to be two s complement or straight offset binary by configuring jumper JU7. See Table 7 for the appropriate jumper configuration. - -* -** 7-8** Connected to Connected to Connected to REFIO through R7 and R Connected to through R7 and R EV KIT FUNCTION Internal reference disabled. Apply an external reference voltage at the REFIO pad. Verify that a shunt is installed on jumper JU. Internal reference enabled. Verify that a shunt is not installed on jumper JU. Increase full-scale range by adjusting potentiometer R. C om p ensate for g ai n er r or s b y ad j usti ng p otenti om eter R. *Default configuration: JU (-). **Refer to the Full-Scale Range Adjustments using the Internal Reference section in the MAX, MAX, MAX7, or MAX8 IC data sheet. Table 7. Output Format Jumper Settings (JU7) SHUNT POSITION T/B P CONNECTION - -* *Default configuration: JU7 (-). DESCRIPTION St ra ig ht O f f s e t B ina r y Se lec t e d. D i gi tal outp ut i n str aig ht offset b i nar y for mat. T w o s C o m p le m e n t Se l e c t e d. D i g i tal outp ut i n tw o s- com p l em ent for m at.

7 MAX/MAX/MAX7/MAX8 Double-Termination Settings The ADC features trimmed, internal 00Ω termination resistors between the positive (true) and negative (complementary) line of each output (D0 D7, CLK, and FRAME). The EV kit circuit also features 00Ω termination resistors located at the far end of each differential output pair. Activating the internal termination helps eliminate unwanted reflections on the signal traces. Use jumper JU to activate either single or double-termination. See Table 8 for appropriate shunt positions that select the termination architecture. Table 8. Double-Termination Jumper Settings (JU) SHUNT POSITION DT P CONNECTION - -* *Default configuration: JU (-). EV KIT FUNCTION D o u b le T e r m in a t io n Se le c t e d. Outp uts ar e d oub l e- ter m i nated. Sin g l e T e r m i n a t io n Se l e c t e d. O utp uts ar e si ng l e- ter m i nated. SLVS/LVDS Outputs The ADC is capable of generating SLVS or LVDS signals at its outputs. Jumper JU controls this feature of the ADC. See Table 9 for shunt positions. Regardless of which output signal type is selected, the output buffers (U7 U) will convert the data to L logic levels. When operating in SLVS output mode, JU must be configured for double-termination (shunt across pins and ). Table 9. SLVS/LVDS Jumper Settings (JU7) SHUNT POSITION SLVS/LVDS P CONNECTION - SLVS -* LVDS *Default configuration: JU7 (-). ADC PUT LVDS Test Pattern To debug signal integrity problems, the ADC can generate a factory-set test pattern on all of the output channels. Jumper JU controls this feature. See Table 0 for the appropriate shunt positions. The test pattern for the MAX, MAX7, and MAX8 is The test pattern for the MAX is (MSB to LSB). Table 0. LVDS Test Pattern Jumper Settings (JU) SHUNT POSITION LVDSTEST P CONNECTION EV KIT FUNCTION - Test pattern transmitted, LSB first, on all SLVS/LVDS outputs -* Normal operation *Default configuration: JU (-). Output Bit Locations The digital outputs of the ADC are connected to the 0- pin header J9. All PC board trace lengths are matched to minimize data skew and improve the overall dynamic performance of the device. Additionally, 0 drivers (U7 U) buffer and level-translate the digital outputs to L-compatible signals. The drivers increase the differential voltage swing, and are capable of driving large capacitive loads, which may be present at the logic analyzer connection. The outputs of the buffers are connected with 0-pin header J. See Table for bit locations of headers J9 and J. Table. Output Bit Locations SIGNAL CH0 CH CH CH U N BU F F ER ED ( L VD S or SLVS) BUFFERED (L) P J9- J- N J9- J- P J9- J- N J9- J- P J9-9 J-9 N J9-0 J-0 P J9- J- N J9- J- DESCRIPTION Channel 0 Channel Channel Channel P J9-7 J-7 CLK N J9-8 J-8 Clock FRAME CH CH CH CH7 P = True (+). N = Complementary (-). P J9- J- N J9- J- P J9- J- N J9- J- P J9-9 J-9 N J9-0 J-0 P J9- J- N J9- J- P J9-7 J-7 N J9-8 J-8 Frame Channel Channel Channel Channel 7 7 Evaluate: MAX/MAX/MAX7/MAX8

8 MAX/MAX/MAX7/MAX8 Evaluate: MAX/MAX/MAX7/MAX8 On-Board Deserializer The EV kit features an on-board deserializer that converts the serial outputs of the ADC to a parallel data stream. The deserializer uses a delay-locked loop (DLL) to synchronize itself with the incoming serial data stream. After every change in ADC clock frequency, reset this DLL by pressing switch SW. If the LOCKED LED D is not lit, the serial data stream is not synchronized and the outputs of the deserializer are not valid. Channel 0 through channel 7 data is captured on headers J0 J. Only four channels can be captured at one time on the EV kit. Configure jumpers JU9, JU0, and JU to select the location of the channels. See Table for jumper JU9, JU0, JU configuration. See Table for bit locations. Table. Output Channel Locations (JU9, JU0, JU) JU9 (S) SHUNT POSITION JU0 (S) SHUNT POSITION JU (S0) SHUNT POSITION J0 J J J CH0 CH CH CH CH CH CH CH CH0 CH CH CH CH0 CH CH CH CH CH CH CH CH CH CH CH7 Table. Output Bit Locations (J0 J) BIT POSITION CLK J0-8 J-8 J-8 J-8 D J0- J- J- J- D0 J0- J- J- J- D9 J0- J- J- J- D8 J0-0 J-0 J-0 J-0 D7 J0-8 J-8 J-8 J-8 D J0- J- J- J- D J0- J- J- J- D J0- J- J- J- D J0-0 J-0 J-0 J-0 D J0-8 J-8 J-8 J-8 D J0- J- J- J- D0 J0- J- J- J- Note: Odd numbered pins are connected to ground. Remaining pins are no connects. Deserializer Output Enabled Jumper JU8 controls the output enabled of the deserializer. See Table for jumper JU8 configuration. Table. Deserializer Output Enables (JU8) SHUNT POSITION EV KIT FUNCTION - Deserializer output disabled -* Deserializer output enabled *Default configuration: JU8 (-). 8

9 MAX/MAX/MAX7/MAX8 CVDD CVDD R R7 0Ω C C 0 97 R 0P 0P 0P R 00Ω C 9pF C T C C C C C C C0 C9 TP 78 R7 0N 0N J R9 C7 PLACE CAPACITORS NEXT TO PS /,,, 7/8, 9/0, /, 8/87, 88 OF U. 7 P P CVDD R 00Ω R7 R8 0Ω C R R 0N 98 7 N N C 9pF C C C C C0 C9 C8 C7 9 P P R7 00Ω R8 R9 0Ω C R C 8 P N N C7 C 8 9 C C C 9pF T P P C TP R8 R8 00Ω J R0 C7 PLACE CAPACITORS NEXT TO PS,, 9,, 7, 0, /, 7, 7, 7, 77 OF U. N N R9 R0 0Ω C R R CLKP CLKP R9 00Ω CLKN CLKN 9 U MAX ADC FOR MAX EVKIT MAX ADC FOR MAX EVKIT MAX7 ADC FOR MAX7 EVKIT MAX8 ADC FOR MAX8 EVKIT N C 9pF FRAMEP FRAMEP R0 R 0Ω C7 R C CVDD T/B R0 00Ω P C 9pF T CVDD 8 FRAMEN JU7 FRAMEN C7 TP R9 C7 0µF.V J P P R C7 C78 C 0µF C9 PLL JU R00 00Ω R R 0Ω C8 R R N N N Figure. MAX/MAX/MAX7/MAX8 EV Kit Schematic ADC (Sheet of ) PLL P P C 9pF JU C80 C 0µF C0 C 0µF.V R0 00Ω PLL R N R 0Ω C9 C N R7 P JU 8 P P C7 9pF T PD R0 00Ω C8 TP R0 J 7 R C7 JU N N C77 C 0µF C8 C 0µF.V 7P 7P LVDSTEST R R 0Ω C0 R8 R JU R0 00Ω N C8 9pF 7N SLVS/LVDS 7N C 0µF.V JU R87 R7 0Ω C C7 C C 0µF C 7 R DT 8 P T/B T/B 8 C 9pF T JU PLL PLL C TP 8 R8 PLL PLL J R C 8 PLL PLL 8 PD PD R88 R7 0Ω C R7 R 80 N 8 LVDSTEST SLVS/LVDS LVDSTEST SLVS/LVDS C7 9pF DT DT R89 R7 0Ω C7 C8 TP9 0 R8 CLK CLK P 9 CM C8 9pF T C 9 REFIO REFIO C TP R9 C9 9 J REFADJ REFADJ R C R90 R8 0Ω C8 R9 R N C9 9pF R9 R8 0Ω C9 C9 R70 P C0 9pF C T7 TP7 R0 J7 R C R9 R8 0Ω C70 R7 R N C 9pF REFP REFN A A A A A A A A A A A A A A A A A 7N 7P C 0µF R9 R8 0Ω C7 C0 7 8 R7 C C 9pF C79 C8 TP8 0µF 0µF C R J8 R8 R7 C7 0Ω R98 9 T8 R R C 9pF Evaluate: MAX/MAX/MAX7/MAX8 9

10 MAX/MAX/MAX7/MAX8 Evaluate: MAX/MAX/MAX7/MAX8 CVDD C.µF CVDD CVDD D C0 C 0.0µF L R R.0kΩ TP 8 R R kω 7 CVDD N TP0 A U NC7WZ0 Y CVDD CLK Y A C R.0kΩ R kω C TP U CLOCK MAX9 P C0 R R.0kΩ R77 R78 R99 Ω R REFIO JU TP JU REFADJ - JU- JU- U C 00µF REFADJ Figure. MAX/MAX/MAX7/MAX8 EV Kit Schematic Clock, Voltage Reference (Sheet of ) JU- JU- MAX0 VSS CVDD JU- JU- REF VDD + JU-7 JU-8 C9 R7.0kΩ R 00kΩ J J9 BD0N J- J- J- J- BD0P 0N J9- J9- J9- J9-0P J- BDN J-8 J- J-7 BDP J9- N J9-8 J9- J9-7 P J-0 BDN J-9 BDP J9-0 N J9-9 P J- J- J9- J9- J- BDN J- BDP J9- N J9- P J- J- J9- J9- J-8 BCKN J-7 BCKP J9-8 CLKN J9-7 CLKP J-0 J-9 J9-0 J9-9 J- BFMN J- BFMP J9- FRAMEN J9- FRAMEP J- J- J9- J9- J- BDN J- BDP J9- N J9- P J-8 J-7 J9-8 J9-7 J-0 BDN J-9 BDP J9-0 N J9-9 P J- J- J9- J9- J- BDN J- J- J- J9- N BDP J9- P J9- J9- J-8 BD7N J-0 J-7 J-9 J9-8 7N BD7P J9-0 7P J9-7 J9-9 0

11 MAX/MAX/MAX7/MAX8 U7 MAX97 Evaluate: MAX/MAX/MAX7/MAX8 OP ON 8 BDOP 8 BDP 8 BDP C7 C7 0.0µF P N 7 R0 R0 R07 C8 0.0µF BDON BDN BDN 8 BDP 8 BCKP 8 BFMP U0 MAX97 C8 C9 C9 0.0µF C 0.0µF P U8 7 R08 N MAX97 R09 R0 C0 0.0µF C0 C 0.0µF P U9 7 N MAX97 C C C 0.0µF C7 0.0µF 7 R CLKP U 7 R7 R R C 0.0µF CLKN MAX97 R8 R9 C 0.0µF FRAMEP U 7 R0 FRAMEN MAX97 R R C8 0.0µF R R R C 0.0µF BDN BCKN BFMN Figure. MAX/MAX/MAX7/MAX8 EV Kit Schematic L Level Translators (Sheet of )

12 MAX/MAX/MAX7/MAX8 Evaluate: MAX/MAX/MAX7/MAX8 C C C7 0.0µF C9 0.0µF BDP 8 BDP 8 R 7 P 7 P R U U MAX97 MAX97 C7 0.0µF R8 R7 N C70 0.0µF R R N Figure. MAX/MAX/MAX7/MAX8 EV Kit Schematic L Level Translators (Sheet of ) BDN BDN C C C7 0.0µF C7 0.0µF BD7P 8 BDP 8 R 7 7P R9 7 P U U MAX97 MAX97 C7 0.0µF R R 7N C7 0.0µF R R0 N BD7N BDN

13 MAX/MAX/MAX7/MAX8 VD. VD. VD. VD. JU8 JU9 JU0 JU J0 J J J J0- J0- J0- J0- J0- J0- J0-7 J0-8 J0-9 J0-0 J0- J0- J0- J0- J0- J0- J0-7 J0-8 J0-9 J0-0 J0- J0- J0- J0- J0- J0- J0-7 J0-8 J0-9 J0-0 J0- J0- J0- J0- J0- J0- J0-7 J0-8 J0-9 J0-0 T0 P N M C0 C J- J- U-B J- J- K L9N_/VREF_ LOP_7/VRN_7 J- J- M L0P_ LOP_/VREF_ J-7 J8 N LON_/VRP_ LON_ J-9 J-0 R LON_/D J- J- R7 L9P_/VREF_ J- J- R8 L9P_/GCLKP J- J- R9 L9N_/GCLKS J-7 J-8 R0 L9N_/VREF_ LOP_/VRN_ J-9 J-0 R LOP_/D LON_/VRP_ J- J- N LON_/VRP_ LOP_ J- J- M LOP_ L9P_/GCLK0S J- J- K L9N_/VREF_ L9N_O/GCLK7P J-7 J-8 D0 J-9 J-0 E0 J- J- E J- J- G L9N_7 J- J- J-7 J-8 CLKDES J-9 J-0 XCV80 FGC J- J- J- J- J- J- J-7 J-8 J-9 J-0 J- J- J- J- J- J- J-7 J-8 J-9 J-0 J- J- J- J- J- J- J-7 J-8 J-9 J-0 J- J- J- J- J- J- J-7 J-8 J-9 J-0 J K L M N N8 N9 N M L K J C C7 L9N_ L9P_ LON_ LOP_ LOP_/D/AVN L9P_/GCLKP L9N_/GCLKS LON_/D/AVP LOP_ LON_ L9P_ L9N_ D G L9P_7 U-C CLKDES XCV80 FGC LON_0 L9P_/GCLKP L9N_ LON_ L9N_ L9P_ L9N_ L9P_7/VREF_7 LOP_ LON_ J- J- J- J- J- J- J-7 J-8 J-9 J-0 J- J- J- J- J- J- J-7 J-8 J-9 J-0 J- J- J- J- J- J- J-7 J-8 J-9 J-0 J- J- J- J- J- J- J-7 J-8 J-9 J-0 K L L K J H H H D7 E G H H H J M N P T T T7 T8 T9 LON_ LON_ LOP_ LOP_/CS LON_/RDWR L9N_ L9N_/GCLK7S L9P_/GCLKOP L9P_ LOP_ LON_ LON_ D G L9P_/VREF_ U-A CLKDES XCV80 FGC LON_7/VRP_7 L9P_ L9N_ LON_ L9N_/GCLKP L9P_0/GCLKS LOP_/D/AVN LOP_0 D C C9 C8 P C B A B A G F F F J J D E E P7 P0 T T D D D D9 D8 K L L L D P9 H E G G G G F F N7 N0 K L L L L9P_7 L9N_7 L9P_7 L9P_ L9P_ LOP_ LOP_ L9P_ L9P_ L9P_ L9N_ L9P_ E7 L9N_7 U-D CLKDES XCV80 FGC L9N_7 L9N_/GCLKS LON_/D/AVP LOP_/D7 LOP_/VRN_ LOP_/VRN_ LON_/VREF_ LON_/VREF_ L9N_ L9N_ L9P_ L9N_ H P8 P P N N M M K K J J G F F F BDP BDN BDP BDN BDP BDN BFMP BFMN BCKP BCKN BDP BDN BDP BDN BDP BDN B C A B A7 B7 A8 B8 B9 A9 B0 A0 B A C B U-H LOP_0 LON_0 LOP_0/VRN_0 LON_0/VRP_0 L9P_0 L9N_0/VREF_0 L9P_0/GLCKS L9N_0/GLCKP L9P_/GLCKS L9N_/GCLKP L9P_/VREF_ L9N_ LOP_/VRN_ LON_/VRP_ LOP_ LON_ LON_7 LOP_7 LON_ LOP_ C D T T R R R R P P N N M M C D BD7N BD7P BD0N BD0P XCV80-FGC Evaluate: MAX/MAX/MAX7/MAX8 Figure. MAX/MAX/MAX7/MAX8 EV Kit Schematic Deserializer Input and Outputs (Sheet of )

14 MAX/MAX/MAX7/MAX8 Evaluate: MAX/MAX/MAX7/MAX8 VD. J J- J- J- TCK J- J- TDO J- TDI J-7 J-8 TMS J-9 VD. R U-G XCV80-FGC VD. R AUX AUX LON_/DO/D P D TCK A TCK B AUX AUX B DONE R DONE PROG A PROGRAM LOP_ E CCLK P CCLK LON_7 F TMS B TMS LOP_7 F TDO TDI D0 D TMS D VD. D D VD. VD. D U-F XCV80-FGC D T T E R97 0Ω T T E D T M N C VD. TDO LON_7 E TP TDI C TDI-FPGA VD. TP TP E LOP_7/ VREF_7 LOP_/IT T IT O_7 G 0_0 0_0 0_0 0_ 0_ 0_ 0_ 0_ 0_ F8 A U-E XCV80-FGC T F7 A E8 T F0 B B R R F9 C P T M E9 C P T N H F L H T N F G SW LON_7 E LON_/BY/ D T O_7 H 0_ J G7 G8 L K0 K9 LOP_7 E RSVD A O_7 H 0_ J G9 K8 M0 RSVD A R0 0kΩ J O_ 0_ K G0 D/CF 7 D CLK CE 0 CEO OE/RESET TDO 8 VD. VD. TDI U XC8V0S TMS PROGRAM CCLK TDI-FPGA TCK TCK O R9.7kΩ VD. D 9 VD. R9 0Ω D7 R9.7kΩ D DONE IT M7 T PWRDOWN B HSWAP_EN VBATT A RSVD M0 M M A J O_ 0_ K7 H7 J0 T K H8 O_ P R L7 O_ O_ L8 0_ 0_ 0_ M9 L0 L9 M8 H9 H0 Figure. MAX/MAX/MAX7/MAX8 EV Kit Schematic PROM and FPGA (Sheet of ) J9 J8 J7 R79 R80 R8 VD. VD. VD. VD. VD_ C8 C8 C8 C8 C8 C7 C C C C C C C0 C C0 C9 C8 C9 C90 0µF C87 0µF.V C8 0µF.V VD. VD. VD_ C09 C08 C07 C0 C0 C0 C0 C0 C0 C00 C99 C98 C97 C9 C9 C9 C9 C9 0µF C89 0µF.V C88 0µF.V

15 MAX/MAX/MAX7/MAX8 Evaluate: MAX/MAX/MAX7/MAX8 Figure 7. MAX/MAX/MAX7/MAX8 EV Kit Component Placement Guide Component Side

16 MAX/MAX/MAX7/MAX8 Evaluate: MAX/MAX/MAX7/MAX8 Figure 8. MAX/MAX/MAX7/MAX8 EV Kit PC Board Layout Component Side

17 MAX/MAX/MAX7/MAX8 Evaluate: MAX/MAX/MAX7/MAX8 Figure 9. MAX/MAX/MAX7/MAX8 EV Kit PC Board Layout (Inner Layer ) Ground Planes 7

18 MAX/MAX/MAX7/MAX8 Evaluate: MAX/MAX/MAX7/MAX8 Figure 0. MAX/MAX/MAX7/MAX8 EV Kit PC Board Layout (Inner Layer ) Power Planes 8

19 MAX/MAX/MAX7/MAX8 Evaluate: MAX/MAX/MAX7/MAX8 Figure. MAX/MAX/MAX7/MAX8 EV Kit PC Board Layout (Inner Layer ) Signal Layer 9

20 MAX/MAX/MAX7/MAX8 Evaluate: MAX/MAX/MAX7/MAX8 Figure. MAX/MAX/MAX7/MAX8 EV Kit PC Board Layout (Inner Layer ) Signal Layer 0

21 MAX/MAX/MAX7/MAX8 Evaluate: MAX/MAX/MAX7/MAX8 Figure. MAX/MAX/MAX7/MAX8 EV Kit PC Board Layout Solder Side

22 MAX/MAX/MAX7/MAX8 Evaluate: MAX/MAX/MAX7/MAX8 Figure. MAX/MAX/MAX7/MAX8 EV Kit Component Placement Guide Solder Side

23 MAX/MAX/MAX7/MAX8 REVISION NUMBER REVISION DATE DESCRIPTION Revision History PAGES CHANGED 0 /0 Initial release 8/0 Added lead-free parts to Part Selection Table and EV Kit Component List and updated Component Suppliers, Evaluate: MAX/MAX/MAX7/MAX8 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 0 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.