External Peripherals: Interfacing

Transcription

1 CTRICA AND COMPUTR NGINRING DPARTMNT, OAKAND UNIVRSITY C-37: Computer Hardware Design Winter 27 SRIA COMMUNICATION SRIA DATA TRANSMISSION WITH UART xternal Peripherals: Interfacing UART INTRFAC This interface transfers data asynchrously (clock is t transmitted, transmitter and receiver use their own clocks). Data communication: RXD (receive pin), TXD transmit pin). The FT2232 chip inside the Nexys-4 board handles the USB communication with a computer. Format of a Frame: Start bit ( ), to 9 data bits (SB transmitted first), optional parity bit, and a stop bit ( ). Micro USB FT2232 Transmitter: Simple design that transmit the data frame at the Baud rate (or bit rate in bps). Receiver: It uses a clock signal whose frequency is a multiple (usually 6) of the incoming data rate. TXD RXD Artix-7 FPGA C4 (RXD) D4 (TXD) Baud rate clock TXD DO D D2 D3 D4 D5 D6 D7 stop DIGITA SYSTM: UART TRANSMITTR (FSM + Datapath circuit) For a baud rate of 96 bps, the Baud rate clock is 96 Hz. N = 96 = 46. This number changes according to the ns desired baud rate. Counters: = Q Q+. =sclr= Q. Note that the way the counters are designed, once the maximum count is reached, asserting the enable to resets the count to. C Q FSM TXD R R so s_ SW RIGHT SHIFT RGISTR din resetn= S TXD TXD R, R TXD resetn clock Q sclr zc counter to 7 Q 3 C sclr Q counter to N- n zc zc C (C ) TXD so C (C C+) If max count is reached, C= makes C= START bit zc C (C C+) C (C ), R DATA bits Q (Q Q+) Q (Q ) TXD If max count is reached, Q= makes Q= C (C ) zc C (C C+) STOP bit Instructor: Daniel lamocca

2 ODATA_RG CTRICA AND COMPUTR NGINRING DPARTMNT, OAKAND UNIVRSITY C-37: Computer Hardware Design Winter 27 SPI (ACCROMTR) SPI INTRFAC Simple 4-wired synchrous (clock is transmitted) serial interface. SPI logic signals: SCK: Serial clock. Generated by Master. MOSI: Master Output, Slave Input. Generated by Master. MISO: Master Input, Slave Output. Generated by Slave. /CS: Chip select (or Slave Select). Generated by Master. Messages are supported that are multiple of bits. Clock polarity (CPO) and Phase (CPHA): /CS ADX362 MOSI MISO /CS SCK Slave Artix-7 FPGA Nexys-4 DDR F4 5 D5 F5 Master SCK (CPO=) SCK (CPO=) MOSI/MISO (CPHA=) MOSI/MISO (CPHA=) MSB or SB CPO = : Base value of SCK is. CPHA=: Data is captured on rising edge, data is output on falling edge. CPHA=: Data is captured on falling edge, data is output on rising edge. CPO = : Base value of SCK is. CPHA=: Data is captured on falling edge, data is output on rising edge. CPHA=: Data is captured on rising edge, data is output on falling edge. SB or MSB It is commonly used for short distance communications within embedded systems. Microcontrollers and FPGA designs use SPI to communicate with internal/external peripherals. arge variety of SPI-capable peripherals available: sensors (e.g.: temperature, pressure), ADCs, DACs, touchscreens, memories, CDs, SD cards. ACCROMTR ADX362 This 3-axis MMS device operates as a SPI slave device. We read/write data via a register-based interface: we can write/read a byte or many bytes per bus transaction. ADX362 parameters (range, resolution, ODR are selectable): Range: 2g (default at reset), 4g, g. Resolution: mg/sb (default at reset), 2 mg/sb, 4 mg/sb Output data rate (ODR): Hz. Default at reset: Hz. Output resolution: 2 bits. Representation: signed. CPO =, CPHA =. Many SPI devices work very similarly, although we need to comply with specific timing parameters. Accelerometer: Basic Controller (code available here) Operation: We first configure the appropriate ADX362 registers and then proceed to read -bit registers. A simple operation mode is listed here. Refer to the ADX362 datasheet for a complete list of registers and operation modes. Reset the ADX362. Write x52 on SOFT_RST (xf) register. Activate measurement mode. Write x2 on POWR_CT (x2d) register. Read any -bit register (one per bus transaction). See ADX362 datasheet for complete list. The basic controller is depicted on the right. The block wr_reg_adxl362 is the most important: it handles the SPI communication based on address, data and write/read decision. Asserting the signal initiates a transaction. When the operation is completed, the signal is asserted for one clock cycle. If reading data, it appears on odata. A new transaction can be ed on the next cycle after =. resetn clock sel 2 FSM _odata SCK_T wr_reg_adxl362 wr_rd odata address data /CS MOSI MISO SCK D _odata Q 2 Instructor: Daniel lamocca

3 sclrq Q sclrt T CTRICA AND COMPUTR NGINRING DPARTMNT, OAKAND UNIVRSITY C-37: Computer Hardware Design Winter 27 FSM: It issues commands to configure the 2 ADX362 registers and then read (cyclically) from one of four -bit ADX362 registers (selected by the sel input). Data is fetched on the output register. Here, we can read the low-precision -bit X, Y, Z measurements (x, x9, xa) and the Status Register (xb). wr_reg_adxl362: This circuit handles the SPI communication with the ADX362. The user provides address, data, and read/write. Then, a read/write SPI transaction is executed. At every transaction, we write or retrieve bits of data. When writing to the ADX362, 3 bytes are transmitted: command address data. When reading from the ADX362, 2 bytes are transmitted command address, and byte is read (data) and placed on odata. Circuit Design: It involves implementing the SPI protocol and complying with the ADX362 timing parameters (see datasheet): C SS (/CS Setup Time): ns t CSH (/CS Hold Time): 2 ns t CSD (/CS Disable Time): 2 ns t SU (Data Setup Time) = t HD (Data Hold Time): 2 ns f SCK: 2.4 (only when using FIFO) KHz. t HIGH (SCK High Time) = t OW (SCK ow Time) = 5 ns. Note that these times only constrain the duty cycle when using large frequencies. The maximum frequency is MHz. SCK: t defined by the standard (usually a few MHz). This is specified by the Slave Device (ADX362: f SCK KHz). This design uses a free running SCK. To comply with the timing parameters: T SCK-(t CSD+t CSH) C SS T SCK 2 ns (f SCK 3.57 MHz). For T SCK=2 ns, we have SCK_T = 2 (at clock= MHz) as the minimum possible value. To display data on Ds or 7-segment displays, you need an appropriate refreshment rate. We can choose T SCK= ms (f SCK= KHz) SCK_T= 6. Since there are 24 SCK periods in a reading transaction, data is refreshed at 24 ms per sample. FSM_SCK: It generates a free running clock of period SCK_T and 5% DC along with rising and falling edge detectors. _odata address x resetn= S address xf data x52 wr_rd, address x2d data x2 wr_rd, data xxx wr_rd, address x9 S6 sel address xa address xb wr_rd address data i a d xa xb write read command FT FT FT i d a o FSM_MAIN 2 2 s o FSM_SCK Q FT counter to SCK_T/2- din MISO odata MOSI SCK /CS FSM_SCK S resetn= T, sclrt SCK T, sclrt SCK (T ) T (T T+) (T ) T Q T, sclrt (T T+) (T ) counter to 7 wr_reg_adxl362 3 Instructor: Daniel lamocca

4 CTRICA AND COMPUTR NGINRING DPARTMNT, OAKAND UNIVRSITY C-37: Computer Hardware Design Winter 27 FSM_MAIN: handles the SPI communication and complies with the ADX362 timing parameters. Command, address, data (MSB is sent first), same when reading. Note that T CSD = T CSH = 2 (2 ns). To comply with the timing parameters, we always wait until the last falling edge in a reading or writing cycle, then wait for T CSH cycles, set /CS= for T CSD cycles and then we are back in State S for a new transaction. Note how we embed the counters for qt CSD and qt CSH inside the FSM. Other approaches do t have a free running SCK, but instead they only activate it when /CS=. This approach might make the controlling of the timing parameters simpler (depending on the timing parameters). S /CS resetn= s 2 s i, a, d i d Q Q, sclrq o Q Q, sclrq S6 Q S7 Q, sclrq s qt CSH =T CSH - qt CSH qt CSH + qt CSH a S /CS Q Q, sclrq qt CSD =T CSD - qt CSD qt CSD + qt CSD S 4 Instructor: Daniel lamocca

5 CTRICA AND COMPUTR NGINRING DPARTMNT, OAKAND UNIVRSITY C-37: Computer Hardware Design Winter 27 I 2 C (TMPRATUR SNSOR) I 2 C (Inter-Integrated Circuit) INTRFAC Simple 2-wired synchrous (clock is transmitted) serial interface. I 2 C logic signals: SC: Serial clock. Generated by Master, defined by the Slave device. The standard specifies a Fast Mode (up to 4 KHz), a High Speed Mode (up to 3.4 MHz), and an Ultra-Fast Mode (up to 5 MHz). SDA: Bi-directional serial data. In general, SC and SDA are open-drain. There can be one Master and many Slaves. The Master device puts the slave address on the bus, and the slave device with the matching address ackwledges the Mater. Slave Address: Unique identifier of a device. 7-bits wide. Communication on the I 2 C bus: SC It s when the master puts the START condition (S) on the bus (a high-to-low transition on SDA while SC is high). The bus is considered to be busy until the Master puts a STOP condition (P) on the bus (a low-to-high transition on SDA while SC is high). I 2 C data: Transfed in -bit packets. There is restriction to the number of bytes transmitted per data transfer. ach byte transfed must be followed by an ackwledge signal (ACK). ACK () is generated by the Slave. After a START condition (S), the Master writes the 7-bit Slave Address followed by a Read/Write bit, then ACK. Then, the Master writes/reads bytes of data, each byte followed by an ACK. When writing, after the last written byte (followed by ACK), data transmission is terminated by the Master with a STOP condition (P). When reading, only on the last byte, the Master must generate a NACK (Not ackwledge) bit, and then a STOP condition (P). The Master can also generate a repeated START condition (Sr) without first generating a STOP condition (P) to signal that the bus is still busy. Data bits are read on the SC rising edge. We must comply with the Slave device timing parameters: t SU:DAT, t HD:DAT, t SU:STA, t HD:STA, t SU:STO. Unlike a flip flop, t HD:DAT (hold time) is defined as the time the data bit should be on the bus after SC is high (i.e., after the falling edge). S ADT742 Slave SC SDA 3.3v Artix-7 FPGA Nexys-4 DDR C4 C5 Master P SDA A6 A5 A4 A3 A2 A A R/W ACK D7 D6 D5 D4 D3 D2 D D ACK SDA A6 A5 A4 A3 A2 A A R/W ACK D7 D6 D5 D4 D3 D2 D D NACK SC SDA t HD:STA t HD:DAT t SU:DAT A3 A2 A A R/W ACK D7 D6 D5 D4 D3 D2 D I 2 C is commonly used for attaching lower-speed devices to processors and microcontrollers in short-distance, intra-board communication. arge variety of I 2 C-capable peripherals available: sensors (e.g.: temperature, acceleration, pressure), ADCs, DACs, touchscreens, memories, CDs, SD cards. TMPRATUR SNSOR ADT742 This high accuracy digital temperature sensor operates as an I 2 C slave device. We read/write data via a register-based interface: we can write/read a byte or two bytes per bus transaction. ADT742 parameters (resolution is selectable): Output resolution: 3 bits (default at reset), 6 bits. Representation: FX signed. Resolution:.625 C per SB (3-bit mode, default at reset),.725 C per SB (6-bit mode). 6-bit mode: FX Format [6 7]. Temperature ( C): 25 b i= b i 2 i 3-bit mode: FX Format [3 4]. This is just the 3 MSBs of the 6-bit result. Temperature ( C): 22 b 2 + i= b i 2 i According to the formulas, the temperature range is [ 256 C, 256 C). However, in practice the ADT742 is guaranteed to measure temperature between -4 C and 5 C. Slave Address: A A. A A bits are configurable. Nexys-4 DDR-Board: A A = Slave Address: x4b. Temperature Sensor: Basic Controller (code available here) Operation: We first configure the appropriate ADT742 registers and then proceed to read -bit registers. A simple operation mode is listed here. Refer to the ADT742 datasheet for a complete list of registers and operation modes. Configure the 6-bit mode. Write x on CONFIG (x3) register. Read any -bit register (one per bus transaction). 2 7 D ACK t SU:STA Sr A6 2 4 A5 t SU:STO A4 5 Instructor: Daniel lamocca

6 ODATA_ ODATA_H CTRICA AND COMPUTR NGINRING DPARTMNT, OAKAND UNIVRSITY C-37: Computer Hardware Design Winter 27 The Basic Controller interacts with the following registers: (refer to the ADT742 datasheet for a complete list of registers). Reg. Address Name Reg. Address Name x TMP_H x3 CONFIG x TMP_ x2 STATUS xb ID 3-bit mode: This requires to write x on CONFIG register. The 3-bit data will be located in the 3 MSBs of the 6- bit sequence: TMP_H TMP_. Reading from the ID register results in xcb (manufacturer s setting) Communication Protocol: This protocol runs on top of I 2 C. Writing/reading here refer to the process of writing/reading to/from a register. This is a bit different from writing/reading data onto the I 2 C bus (what the I 2 C protocol specifies). RA: ADT742 internal Register Address of ADT742. AD: Slave (ADT742) I 2 C Address (x4b). NACK: Not Ackwledge (), set by Master, ACK: Ackwledge (). W: Write bit (). R: Read bit (). For AD, RA, DATA, MSB is sent first. Single-byte Write Sequence: Master S AD (7-bit) W RA (-bit) DATA (-bit) P Slave ACK ACK ACK Single-byte Read Sequence: Master S AD (7-bit) W RA (-bit) Sr AD (7-bit) R NACK P Slave ACK ACK ACK DATA (-bit) The basic controller is depicted on the right. The block wr_reg_adt742 is the most important: it handles the I 2 C communication based on address, data and write/read decision. Asserting the signal initiates a transaction. When the operation is completed, the signal is asserted for one clock cycle. If reading data, it appears on odata. A new transaction can be ed on the next cycle after =. resetn clock sel FSM _h _l SC_T wr_reg_adt742 wr_rd odata address data _h _l FSM: It issues commands to configure one ADT742 register (CONFIG) and then read (cyclically) from two of four - bit ADT742 registers (selected by the sel input). Data is fetched on the output registers. Here, we can read the STATUS and ID registers (x2, xb), or TMP_H and TMP_ (x, x). wr_reg_adt742: This circuit handles the I 2 C communication with the ADT742. The user provides address, data, and read/write. Then, a read/write SPI transaction is executed. At every transaction, we write or retrieve bits of data. Circuit Design: It involves implementing the I 2 C protocol and satisfying the ADT742 timing parameters (see datasheet): t SU:DAT (Data Setup Time):.2 us. t HD:DAT (Data Hold Time):.3 us. f SCK 4 KHz. t HD:STA (Hold Time Start Condition):.6 us. Time SC must be after SDA falling edge. t SU:STA (Setup Time Start Condition):.6 us. Time SC must be before SDA falling edge. t SU:STO (Setup Time Stop Condition):.6 us. Time SC must be before SDA rising edge. t BUF (Bus-Free Time Start and Stop Condition):.3 us. For f SC 4 KHz (T SC 2.5 us), we have SC_T 25 (at clock = MHz). To display data on Ds or 7-segment displays, you need an proper refreshment rate. We pick T SCK= ms (f SCK= KHz) SCK_T=5 3. There are about 35 SC periods in a reading transaction, thus data is refreshed at 35 ms per sample. FSM_SC: It generates a clock of period SC_T and 5% DC along with rising and falling edge detectors. It also issued a delayed falling edge detection signal : This is to allow data to be kept for t HD:DAT after the falling edge. The clock stops after the STOP condition (P) is issued. er address x2 _l SC SDA resetn= S address x3 data x wr_rd, data xxx wr_rd, address xb _h sel data xxx wr_rd, S6 sel er er address x er er address x er er 6 Instructor: Daniel lamocca

7 sclrq Q swr sclrt T CTRICA AND COMPUTR NGINRING DPARTMNT, OAKAND UNIVRSITY C-37: Computer Hardware Design Winter 27 wr_rd address data swr i a d wr x4b FT FT FT i d a o 2 2 s FSM_MAIN Q counter to 7 _scl stop_scl wr so o so _scl stop_scl SDAo SDAoe st dn counter to SC_T/2- Q FSM_SC FSM_ACK T FT din SDAi wr_reg_adt742 SC odata SDA FSM_SC S resetn= SC T, sclrt _scl SC T, sclrt stop_scl SC T T T, sclrt (T ) (T T+) (T ) T=T HD - (T T+) (T ) FSM_ACK: It handles the detection of the Ackwledge bit (ACK), which is generated by the Slave. This operation is repeated at many points in the design, thus we decided to have a separate FSM. FSM_ACK S resetn= st SDAi ACK dn 7 Instructor: Daniel lamocca

8 CTRICA AND COMPUTR NGINRING DPARTMNT, OAKAND UNIVRSITY C-37: Computer Hardware Design Winter 27 FSM_MAIN: It handles the I 2 C communication and complies with the ADT742 timing parameters. Note that T BUF = 3 (3 ns). Also, data is kept for t HD:DAT after the falling edge of SC (that is why we have the signal z Fhd, which is issued after t HD:DAT). Note that when the Slave is writing data, SDAoe=. S S START condition and 7-bit Slave Address R/W= Write Register Address resetn= S stop_scl, SDAo SDAo so, s i _scl,i, a, d, wr Q Q, sclrq a a Q Q, sclrq, st SDAo st SDAoe dn SDAo so, s SDAoe dn S S6 ACK ACK S Write Data S STOP condition if = SC will stay at '' because stop_scl='' right when ='' Wait t BUF before a new transfer can be ed S6 S9 SDAoe so, s 2 d Q Q, sclrq, st S7 S SDAoe dn SDAo t() stop_scl SDAo SDAo qt BUF =T BUF - qt BUF SDAo, _scl, i, S ACK S qt BUF qt BUF + Slave Address x4b R/W= Read Data Wait until falling edge NACK is forced S to '' so we can exit S SDAoe so, s i Q Q, sclrq S SDAo st SDAoe dn SDAoe o Q Q, sclrq SDAoe SDAo wr, swr ACK Instructor: Daniel lamocca

9 ndc AUD_PWM ndc ndc ndc sclrq Q ndc ndc CTRICA AND COMPUTR NGINRING DPARTMNT, OAKAND UNIVRSITY C-37: Computer Hardware Design Winter 27 PUS-WIDTH MODUATION (PWM) DFINITION We generate a square wave where we control the Duty Cycle. Duty Cycle is specified as a percentage: from to %. PWM can be used to vary the average voltage on an output pin. This can be useful (in lieu of a DAC) to control the brightness of an D, speed of a DC motor, volume of a tone in a speaker, etc. DIGITA SYSTM FOR PWM (code available here) TPWM (Period of PWM signal in units of T clock ): This is a parameter in the VHD code. TPWM > 2 T PWM = TPWM. TPWM f clock S DC DCq _DC FSM Q sclr counter to TPWM- opwm _DC = resetn= Q, sclrq _DC opwm DCq TPWM [,TPWM-] (Q ) opwm, Q (Q Q+) _DC, opwm DCq= For f clock = MHz: TPWM = 5 f PWM = 2 KHz TPWM = 5 f PWM = 2 KHz opwm, Q (Q Q+) DC (Duty Cycle): Input signal with ndc bits. ndc = log 2 [TPWM + ] DC [, TPWM]. Note that DC is t specified from to %, but rather from to TPWM. Note that the step of the DC depends on f clock. An external circuit can retrieve the Duty Cycle in standard terms (-%) and convert it to to TPWM. (Q ) Q, sclrq _DC Q=DCq- opwm (Q Q+) Q=TPWM- Q TRI-COOR DS RGB color can be controlled by varying (via PWM) the brightness of a Red, Green, and TPWM TPWM Blue Ds. We want to control the DC of each color component using NB=4 bits. So, 4 we need to map a signal from to 2 NB R - to a signal from to TPWM. Mapping formula: PWM RD DC( TWPM) = TPWM 2 NB DC( 2NB ) TPWM DC( 2NB ) 2 NB 4 G PWM GD DIGITA CIRCUIT (code available here) Mapping circuit: The approx. formula optimizes hardware: we multiply and then drop NB SBs. DC (-TPWM) never reaches TPWM, but the approx. is good eugh. 4 PWM frequency: 2 KHz (TPWM=5, f clock = MHz) provides a good color B PWM BD variation. A high frequency breaks the linearity between the brightness and the DC. We can use more bits per color component, but we need more input signals. For NB=4, refer to hex tables (higher nibble). MONO AUDIO OUTPUT Nexys-4 (DDR) Board: An analog low pass filter (connected after AUD_PWM) turns a PWM signal with varying DC (DC goes from to % and back) into a sinusoid. Use NB= bits. DIGITA CIRCUIT (code available here) CT Shaded circuit: It generates a square wave and it can be CT 2 frq+6 - UT connected to a buzzer or speaker, though we can only vary TPWM 3 2 DC ( volume). Only frequency can change the tone, i.e., we 3 TM - need a new circuit where TWPM is an input signal. PWM P P TM Q sclr CT: It produces a varying -bit DC ( 255, ). This SD TPWM AUD_SD 255 allows the integrator to generate a sinusoidal wave. The variation rate is controlled by frq, i.e., we can pick from sinusoidal frequencies. AUD_PWM: Open-drain output. AUD_SD: Analog filter shutdown input (via the AD592 opamps). TPWM = ( KHz). frq 3 frq 3 9 Instructor: Daniel lamocca

10 CTRICA AND COMPUTR NGINRING DPARTMNT, OAKAND UNIVRSITY C-37: Computer Hardware Design Winter 27 PUS DNSITY MODUATION (PDM) DFINITION Popular in mobile devices, only bit is required. -bit signal is oversampled. The amplitude of a signal is represented by the relative density of the pulses: the closer the pulses are, the larger the amplitude. Unlike PWM, the frequency of the pulses is t fixed. A PDM signal can be generated from an analog signal by using a sigma-delta modulator. Once PDM data is obtained, the analog signal can be recovered by passing the signal through an analog low-pass filter: + PDM signal Analog owpass Filter Reconstruction filter If we want to get the PCM (pulse-code modulation)-coded signal to apply digital signal processing operations, we require a digital decimation filter. The figure depicts a PDM signal oversampled by a factor of N (over the Nyquist rate). The decimation filter outputs a signal x[n] (6 bits per sample) sampled at the Nyquist rate. To recover the analog signal from x[n], a DAC (digital-to-analog converter) is required. + PDM signal Digital Decimation 6 Filter F PDM / N F PDM oversampled signal by a factor of N N=64,2 MICROPHON ADMP42: MMS Microphone with PDM output CK: 3 MHz. Recommended: 2.4 MHz. DATA: PDM signal (oversampled data) /R: eft right stereo input control. /R=: Data captured on CK rising edge. /R=: Data captured on CK falling edge. Many MMS microphones (e.g.: ADMP52, MP34DT2) feature a similar synchrous interface. ADMP42: Synchrous interface. Make sure to comply with the timing parameters (see ADMP42 datasheet). CK /R S= DATA pulse pulse /R S= DATA pulse pulse Once PDM data is obtained, the audio signal can be played back by passing the signal through an analog low-pass filter. AUDIO OUT Nexys-4/Nexys-4 DDR: The on-board audio jack is driven by an analog low-pass filter. The input then can be a PDM or PWM signal. The cut-off frequency is about 2 KHz. Stereo output is t supported. AUD_PWM: Open-drain output. AUD_SD: Analog filter shutdown input (via the AD592 opamps). AUDIO CAPTUR AND PAYBACK ON TH NXYS-4 DDR BOARD The figure depicts the connection between the MMS microphone, the Artix-7 FPGA, and the mo audio output. DIGITA CIRCUIT As stereo output is t supported, we only retrieve a mo audio input from the ADMP42 microphone (e.g. /R = ). Main frequency (Nexys-4 DDR Board): f clock = MHz, T clock = ns. ADMP42 CK DATA /R S Artix-7 FPGA Nexys-4 DDR SCK PDM_IN J5 H5 A R F5 D2 AUD_PWM AUD_SD Instructor: Daniel lamocca

11 sclrt T sclrt T RAM_address RAM_we sclrt T CTRICA AND COMPUTR NGINRING DPARTMNT, OAKAND UNIVRSITY C-37: Computer Hardware Design Winter 27 Basic approach The figure depicts a simple circuit that reads data in a shift register and immediately outputs the data. The rate at which data is shifted in and out is given by SCK. Be aware of feedback when using this circuit. FSM_SCK: It generates a free running clock of period SCK_T and 5% DC along with rising and falling edge detectors. With an input clock of MHz, we have that: For SCK = MHz SCK_T = 6 9 =. For SCK = 3 MHz SCK_T = For SCK = 2.4 MHz SCK_T = PDM_IN on '' din 6 6 FT FSM_SCK Q AUD_PWM AUD_SD R SCK counter to SCK_T/2- Memory-based approach Here, data is read into the shift register and then stored it in memory. We can then control when we shift data out. We might also store several audio sequences and select when to play them. Data is shifted in and out at the rate given by SCK. Memory: It can store up to ND 6-bit words. Address size: NA = log 2 ND. Total number of bits: ND 6 bits. Duration of the stored sequence: ND 6 SCK_T T clock. For example if ND = 2 and SCK_T=42 we have.766s. To increase the duration, we can increase SCK_T (SCK_T ), or we can increase the memory size. The main control circuit (FSM_MM) varies according to the type of memory used. The memory might t operate at the same frequency or might have different input/output ports than the ones shown. For example: On-chip memory (BlockRAMs inside Artix-7 FPGAs): asy to use. They operate at the same frequency ( MHz), include the I/O ports as in the figure, and behave as a bunch of registers: data requested/written is available on the next clock cycle. But the capacity is limited (~.5 MB in the XCAT Artix-7 FPGA). xternal memories (e.g.: DDR2 RAM, Flash, SRAM): They require a different I/O interface and operating frequency; however, they can hold much more data. The circuit requires a 6-bit shift register, a memory, and two state machines. The FSM_SCK is also depicted. PDM_IN din 6 6 FT in_ramgen ND words 6 6 in out NA address '' en we AUD_PWM AUD_SD FSM_SCK resetn= S T, sclrt (T ) SCK si p p FSM_MM T counter to 5 FSM_SCK Q R ready_out SCK T, sclrt SCK T T (T T+) (T ) (T T+) counter to SCK_T/2- T, sclrt (T ) Instructor: Daniel lamocca

12 CTRICA AND COMPUTR NGINRING DPARTMNT, OAKAND UNIVRSITY C-37: Computer Hardware Design Winter 27 FSM_MM (using BlockRAMs inside Artix-7 FPGAs): Note how we embed the counter for RAM_address inside the FSM. S si resetn= ready_out, AUD_SD si p T (T T+) p T, sc;rt, p (T ) T T, sc;rt si, RAM_we (T T+) (T ) RAM_address= RAM_address=ND- RAM_address RAM_address RAM_address+ RAM_address=ND- RAM_address RAM_address RAM_address+ si p, p RAM_address RAM_address+ 2 Instructor: Daniel lamocca