Design and Analysis of Full Adder using Different Logic Techniques

Transcription

1 Design and Analysis of Full Adder using Different Logic Techniques B.Yesvanthukumar, V.Sushil Kirubakaran Scholar, ME VLSI Design Birla Institute of Technology and Science - [BITS] Goa Campus, South Goa ABSTRACT Nowadays, the key role for all the functional units of microprocessor and DSP processors is the Adders. In the emerging trend in the Nano technology, it has been very essential to improve approaches proficiently decrease the range and power consumption. They are the coreconstituents in digital strategies which are not only used for addition but also used for multiplication and division processes. Simultaneously, high speed calculation has turn intosignificantquantity of any digital claimsdue its power consumption. In VLSI technology, Power dissipation is an aggregating concern. Many different logic circuits have been established to encounter these power necessities. In this paper, Power dissipation can be reduced by using different logic circuits. The delay taking place and power deliberations along with the transistor computation have been considered and it has been found that in different circuits, power and delay time is better. Keywords:Adders, power consumption, logic circuits, DSP processors. 1. INTRODUCTION Adders are the most significant logic modules used in the strategy of digital VLSI circuits. The logical Addition is the basic arithmetic operation in the processing systems. It practices the basis for nearly all calculationssuch as multiplying, counting and sifting. In addition to carrying out the responsibilities of addition which is its basic function, the precedes the source for many difficult circuits like the multipliers, subtractors, RAMs, report calculations and much more. The promptrise in the number of transistors on chips has allowed anintensegrowth in the enactment of computing systems. There are two types of s: Half Adder and Full Adder. The half is the modestkind of which is proficient of carrying out the unpretentious type of addition logic while producing a carry. It precedes two inputs and makes two outputs Sum and Carry. The Full Adder is the complex type of addition circuit. It is a combinational logic unit that implements all the calculations. There are definiteissues that can merely slow down the growth of small complex IC chips. These features are intentionprice, design efficiency and IC fabrication technology. The aggregating demand for High Speed VLSI can be acquired at design levels such as architectural, circuit and designlevel. This paper agrees in the study of most broadly used which is full. The full is a humble, practical digital circuit constructed from two logic gates. The logic gates used for the strategy of the full are the XOR, AND and OR gates. A full can be raised using two half s. For A, B and Cin, where A and B are operands to be added, and Cin is the carry that is the bit carried forward form the minimumsubstantial bit of last intention. In CMOS expertise, even if we plan high speed full, power dissipation is the main concern taken into account. It is one of the precariousaspects which is of two types and is classified into dynamic power and static power. Dynamic power dissipation comes into depiction when the circuit is functioning and static power dissipation is reflectedonly when the circuit is inactive. Fig.1: Full ISSN: Page 29

2 Table.1: Truth table of full A number of logic techniques have been suggestedfor highlighting the energy repossessionsource. Two different techniques used in this proposed system are Cascade voltage switch logic (CVSL) and adiabatic logic. CVSL is a type of logic circuit whereby both true and complement of the same inputs are essential. It has two stowage nodes for each gate in its place of one;bring about in higher easiness of pulses than CMOS. In adiabatic circuits power dissipation is considerably less than that of CMOS circuits. Therefore, adiabatic circuits are capableaspirant for low-power circuits which can be activated in the frequency range in which signals are numericallytreated. 2. CASCADE VOLTAGE SWITCH LOGIC Cascade Voltage Switch Logic is a type of circuit whereby mutual true and complement of its inputs are essential. Two complementary NMOS switch configurations are created and then associated to a pair of cross-coupled pull-up PMOS transistors. The pulsed CVSL circuit is two domino gates functioning on true and complement inputs. The CVSL has two stowage nodes for each gate in its place of one, ensuing in higher acceptance of SET pulses than CMOS. Static and clocked CVSL test circuits are fictitiousemploying two complementary NMOS switch arrangements are created and then associated to a pair of cross-coupled pull-up PMOS transistors. The basic design of the CVSL is as shown in figure 2. Fig.2a: Basic CVSL Circuit with single input Fig.2b: Basic CVSL Circuit with two inputs In the above figure pull down transistors are the dual of each other and the P pull up strategies are annoyed combined to the latch output. The pull down network f tools the logic as in a static CMOS gate while uses reversed inputs provide for transistors prescribed in the counterpart. The true input is smeared to right pull-down leg below and complement input is smeared to left leg of the N pull down network. The elementaryfunctioning principle is as described below: Intended forcertain input configuration, one of the pull down networks will be ON and the other one is in OFF. The pull down network that is ON will pull that output low. This low output turns ON the pmos transistor to pull the opposite output high. When the contrary output increases, the other pmos transistor turns OFF so no static power dissipation happens 3. ADIABATIC LOGIC The bases of dissipation in a CMOS-based adiabatic circuit can be endorsed to either adiabatic ISSN: Page 30

3 or non-adiabatic deposits. Though it is potential to decrease the adiabatic residues by aggregating the ramp-up time T, the non-adiabatic damages are not certainlyorganized, and be determined by the device considerations. The term adiabatic changing is used to reduce energy loss during alleging and quitting. It is used to describe the thermodynamics process in which no alteration of energy occurs between the system and the outsidesurroundings. As a result of the use of a time fluctuating voltage source, the rate of the swappingchangeover in adiabatic circuit is reduced. The energy degenerated in a complete charge-discharge clock cycle, comprising the mean non-adiabatic losses, is given by the following equation: where R and C take the meanings defined previously and V dd is the voltage of the hold phase Adiabatic logicbased full s has been suggested and then this can be associated with the ECRL and the EEAL based full s. The gratitude can be appraised for the reprocessingof the powerinside the circuit to evade the power dissipation in the all level circuits. The reprocessed thermal drive can be accepted for the assessment of the adiabatic logics from the energy competent logics. 3.1 EEAL (ENERGY EFFICIENT ADIABATIC LOGIC) The EEAL logic circuits comprises of the pmoscombination and the Distributed Concurrent Versions System network. Each phase of the transistor and the network could be pairing to practice the gated and the s such as sum and the carry block. The regulated power supply could be specified into the full s for the energy reclamation of the signal from the inputs. The out a and the out b is the output which might be coupling from the input loading for the buffer and the inverters. Fig.3: Schematic representation of a CMOS implementation of an adiabatic logic function The main leakage current component in a MOSFET is due to the sub-threshold leakage current I leakage given by: where I 0 is a function of the transistor size and parameters; V t is the thermal voltage and V DS is the source-drain voltage which is assumed to perfectly follow the power clock. Fig 4: EEAL logic based Inverter Circuit An adiabatic period is subservient degree approach to cut back power dissipation within the digital logic at value of slower speed of operation. It allows the energy storage on the circuit capacitance to urge recovered rather than degenerated as heat. It affords the charge on the output with full strike and it cares the load capacitance with the constant agreement that is absolutelytemporary of the signal. 3.2 EFFICIENT CHARGE RECOVERY LOGIC (ECRL) Efficient Charge Recovery Logic is a type of adiabatic logic and it uses PMOS transistors. It has ISSN: Page 31

4 the structure which is closely matching with the Cascade Voltage Switch Logic with differential sign. An AC power offers PWR is working for ECRL gates, as a result on improve and reprocess the furnished energy. Each out and I out square amountproduced in order that the capability clock generator will everlastingly drive a enduring load capacitance irregular of the input. Full production swing is acquired as a result of the cross-coupled PMOS transistors in each pre-charge and improvesstages. That is ECRL continuouslydrivestrust on the output with a full swing. Nevertheless, because the voltage on the running clock slants to Vtp, the PMOS electronic transistor gets rotated off. Fig.6: Schematic diagram of CVSL based full Fig 5: ECRL logic based Inverter Circuit The ECRL design area unit functioned during a pipelining style with the four stagesdelivers clocks. Formerly the output is straightlyassociated to the input of subsequent stage; unbiased onepart is enough for a logic price to broadcast. On the other hand, once the yield of a gate is fed back to the input, the provision clocks should be in portion. A latch is one in all the best circumstances that have a feedback path. A major drawback of this circuit is that the presence of the coupling effects, as a result of 2 outputs area unit associated by the PMOS latch and also the two balancing outputs will inhibit one another. Fig.7: Schematic diagram of adiabatic based full 4. SIMULATION RESULTS The suggested and the improved circuits are considered and confirmed by using the TANNER EDA tools. The circuit approach could be shared with the difference forms of the all level observation for the transistor level application. Fig 8: Schematic diagram of EEAL based full ISSN: Page 32

5 s, compared with many intermittently distributedrecognitions. In the prospect, some effort is completed for the planning of high speed low power full s, allowing for adiabatic logic structure and run new recognitions for the essential logic blocks. REFERENCES [1] R. Singh, R. Mehra, Low power TG full design using CMOS Nano technology, 2nd IEEE International Conference on Parallel Distributed and Grid Computing, Vol. 2, pp , Dec [2] Hiroshi Hatano, Single Event Effects on Static and Clocked Cascade Voltage Switch Logic (CVSL) Circuits, IEEE Transactions on Nuclear Science, Vol. 56, Issue. 4, pp , Aug Fig 9: Schematic diagram of ECRL based full [3] DaeWoon Kang, Yong Bin Kim, Design of Enhanced Differential Cascade Voltage Switch Logic (EDCVSL) Circuits for High fan In Gate, IEEE, pp , [4] K. Roy, S. Mukhopadhyay and H. Mahmoodi-Meimand, A leakage current mechanism and leakage reduction techniques in deep sub micrometer CMOS circuits, Proc. IEEE, vol.91, no.2, pp ,Feb [5] S. Kim, C.H. Ziesler, and M.C. Papaefthymiou, Chargerecovery computing on silicon, IEEE Trans. Computers, vol.54, no.6, pp , June [6] M.J. Marjonen, and M. Aberg, A single clocked adiabatic static logic a proposal for digital low power applications, J. VLSI Signal Processing, vol.27, no.27, pp , Feb Fig.10: Waveform of the different logic circuits of full CONCLUSION In this proposed system, we have aimed to design and simulate different logic circuit methods of full such as cascade voltage switch logic and adiabatic logic circuits. The simulation result demonstrates that power consumption of the suggested design is significantly less than that of previously proposed techniques. From this exploration it is perfect that the recommended design is very power efficient system in low power VLSI system. The elegance of high speed low power full cells mainly based upon Subordinate in numerous logic methods has been assumed and which effects in great development on concerns of power delay metric for the intended [7] A. Sharma, R. Mehra, Area and Power efficient CMOS Adder design by hybridizing PTL and GDI technique, International Journal of Computer Applications, Vol. 6, Issue 5, pp [8] Pradeep Kumar, Existing Full Adders and Their Comparison on The Basis of Simulation Result And to design an improved LPFA (Low Power Full Adder), International Journal of Engineering Research and Applications, Vol. 2, Issue 6, pp , Nov-Dec [9] Y. Takahashi, Y. Fukuta, T. Sekine and M. Yokoyama, 2PADCL: Two phase drive adiabatic dynamic CMOS logic, Proc. IEEE APCCAS, pp: , Dec [10] N. Anuar, Y. Takahashi and T. Sekine, Two phase clocked adiabatic static CMOS logic and its logic J. Semiconductor Technology and Science, vol. 10, no. 1, pp. 1 10, Mar [11] VandanaChoudhary, Rajesh Mehra, 2- Bit Comparator Using Different Logic Style of Full Adder, International Journal of Soft Computing and Engineering (IJSCE), Vol. 3, Issue 2, pp , May ISSN: Page 33

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