A MICROPROCESSOR BASED FIRING SCHEME FOR THREE-PHASE CONVERTERS WORKING UNDER A VARIABLE FREQUENCY SUPPLY

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1 A MICROPROCESSOR BASED FIRING SCHEME FOR THREE-PHASE CONVERTERS WORKING UNDER A VARIABLE FREQUENCY SUPPLY G. Bhuvaneswari Department of EE I.I.T., Delhi New Delhi G. Suresh Department of EE Texas A&M University USA. V.V.Sastry Department of EE I.I.T., Madras Chennai ABSTRACT In a weak power system like ours, power supply faces a lot of voltage swells and sags. Apart from this, the supply frequency also deviates upto +5% of its rated value in accordance with the variations in the load. This can cause malfunctioning of digitally controlled converters as it is required that timings of the control signals fed to such converters should be accurate. In this paper, a genralised microprocessor based firing scheme for converters working under a three-phase variable frequency supply is presented. The scheme is built using the Intel processor 8086 along with a timer 8253 and a peripherial interface The firing scheme uses the concept of hardware interrupt to generate the firing signals so that the CPU time of the processor can be used for other useful purposes. The truncation error involved in the calculation of delay corresponding to the delay angle of the converter is also minimised by incorporating an algorithm for correction. This scheme allows the firing angle of the converter to be varied as and when required. The firing scheme enables the converter to be operated over a wide range of frequencies so that the converter could be employed in the rotor side of a static Kramer drive. The firing shone responds to any variation in the supply frequency within one cycle duration. In general, this robust firing scheme can be used for any three-phase converter such as an AC chopper for switching PF correction capacitors or a rectifier in a HVDC transmission system. INTRODUCTION Digitally controlled power converters with their increased reliability and flexibility are commonly used for various applications in the area of power and drives. In such digital systems, the control operations are so accurately timed that even a little deviation in the timing controls can cause malfunctioning of the entire system. For example, in a weak power system like ours, the supply frequency varies from its rated value very often in accordance with the variation in the load. As such, it is essential to measure the supply 273 frequency and fire the power devices in the converter accordingly. There are also certain applications wherein the supply frequency to the converter varies to a large extent as in the case of a controlled rectifier employed in the rotor side of a static Kramer drive. The proposed scheme provides solutions to the above mentioned problems by way of measuring the frequency during every cycle and generating the firing signals for the power devices accordingly. The setup presented in this paper utilises minimum amount of hardware and software. The firing scheme allows the firing angle of the converter to be varied as and when required. The firing scheme presented in this paper has similarities to the one suggested by Dewan et.al. [1], but with the advantage that even wide variations in the supply frequency are taken care of in the present scheme. The firing scheme presented by El-Bolok (2j uses software delay for acheiving the necessary delay angle. As a result, the processor is tied up completely. The present scheme utilises the concept of hardware interrupt and hence the CPU is available most of the times for other useful jobs. HARDWARE DESCRIPTION An 8086 processor with a clock frequency of 2.5 MHz, an 8253 timer with a clock frequency of 307 khz, a programmable interrupt controller 8259 and a programmable peripheral interface (PPI) 8255 are used for implementing this firing scheme as shown in Fig.l (a). The same scheme is implemented with an 8-bit processor 8085 also in which case instead of 8259, two of its built in interrupts (i.e., 6.5 and 7.5 interrupts) are used. The zero crossing of the R-phase to neutral voltage is detected using a comparator with hysteresis and a monostable multivibrator in cascade (referred to as voltage ZCD hereafter). This is fed as the gate input to counter '0' of 8253 timer [3] that is used for the calculation of supply frequency. Counter '1' of 8253 is used for generating the actual firing signals for the power devices. The gate.of Counter 1 is connected to

2 the output of a two input AND gate which has OUT 1 and voltage ZCD as its inputs. The ZCD signal is fed as the Lower Priority (LP) interrupt (for example, 6.5 interrupt in the case of 8085 processor). OUT 1 is fed as the higher priority (HP) interrupt (i.e., 7.5 interrupt in the case of 8085 processor). The LP and HP interrupts are used for frequency measurement and firing the devices respectively. SOFTWARE ASPECTS The entire software is segregated into three portions: (i) Main programme (ii) LP interrupt routine for measuring the supply frequency and (iii) HP interrupt routine for delivering the firing signals to the power devices. In the main programme, the stack, ports, interrupts and timer are initialised. Counter 0 of 8253 timer is initialised in mode '0'. The counter is loaded with 'FFFF H' when the voltage zero crossing occurs for the first time i.e., inside the LP interrupt routine. When the zero crossing occurs for the second time, the processor is interrupted again and the contents of counter '0' are read inside the LP interrupt routine. The difference between the present contents of the counter of FFFF H gives the count corresponding to one cycle or 360 degrees. From this the count corresponding to 60, 1 and the firing angle of the converter are calculated. While calcualting these counts from the 360 count, the remainder available during each and every division is stored separately and processed further to minimise the truncation error. The loading of the count corresponding to the firing angle ex and 60 is done at suitable times so that the output of counter T interrupts the CPU six times in a cycle and hence the thyristors are fired in the correct sequence. The flowcharts for the main programme and the interrupt service routines are shown in Fig. 1 (b). There is a limitation on the maximum and minimum operating frequency of this scheme in accordance with the clock frequency of the 8253 timer. The maximum and minimum frequency at which this scheme can successfully function can be deduced to be 852 Hz and 4.68 Hz respectively for a clock frequency of 307 khz. In other words, it can be said that a suitable clock frequency for the timer can be chosen according to the desired range of operating frequency of the converter. RESULTS To test relaiblity of the scheme, the firing pulses are generated for the frequency range of 5 Hz to 800 Hz using a function generator output as the sinusoidal source. The waveforms at various test points are shown in Fig.2. The scheme is also tested by firing thyristors in a three-phase AC chopper fed by a variable frequency sinusoidal supply that is generated using an alternator coupled to a variable speed primemover. The osciilograms of the alternator output voltage (R phase to neutral) and the R phase current at different speeds are shown in Fig.3. These experimental results validate the proposed hardware and the associated software approach described through the flowcharts. The software is written in assembly language and occupies less than 1 kilobyte of memory space. CONCLUSIONS A microprocessor based firing scheme for a line commutated converter working under a three-phase variable frequency supply is designed, fabricated and tested using Intel 8086 as well as 8085 microprocessors individually. The range of frequencies over which the scheme has to function can be altered by adjusting the clock frequency of the timer suitably. The truncation error involved in the calculation of the frequency is minimised by processing the remainders obtained during each division and hence the accuracy of the shceme is improved. The hardware used is minimum and software is very simple. The processor is available for any useful function as the concept of hardware is used for firing. The response time of this scheme for any variation in the supply frequency is just one cycle time. Thus the proposed scheme proves to be more efficient than any of the currently available firing schemes for three phase converters. REFERENCES 1. S.B. Dewan and W.G. Dunford, 'A microprocessor based controller for a three-phase controlled rectifier bridge', IEEE Transactions on Industry Applications, Vol. IA-19, pp , H.M.El-Bolok, 'A microprocessor based firing circuit for thyristors working under a three phase variable frequency supply', IEEE Transactions on Industrial Electronics, Vol.37, pp , April Intel Microprocessors and Peripherals Handbook, Vol II, pp , Intel literature sales, S

3 Address Bus 16 Data Bus Memory 16 Counter 0 GateO Counter 1 Voltage Zero Crossing Detector R Phase Voltage 8259 PIC IR6 IR5 1 Outl Gate PIT AND IR5 -Higher Priority Interrupt IR6 - Lower Priority Interrupt Fig. 1 (a) Hardware schematic of the proposed firing scheme 275

4 Yes No Load <K degree count in Counter 1 Yes No Load preloaded firing pattern from memory and output it. Derive the firing pattern from the previous one and output it. Store the firing pattern that was just outputted in a memory location Higher Priority Interrupt Routine C^7 R eturn Fig. l(b) Software Structure coutd. Initialise stack, ports, 8253counter '0' in mode 0 and counter' 1' in mode 5 Enable lower priority interrupt only. Set pointers PI, P2, P3=0 No Operation No -y^ Is ~\^P1-2? Yes Make P2=1;P 1=0. Load cc degree count into counter 1. Enable lower priority interrupt only. Floyy Chart for the Main Programme No Operation Fig. l(b) Software Structure 276 contd.

5 Load FFFFH into counter 0 of 8253 Read Counter '0' Register No Enable higher priority interrupt and load 60 degree count into counter 1. Enable higher priority interrupt and load 60 degree count into counter 1. Set PI =4) Calculate 60 degree, 1 degree andocdegree counts. Depending on the range in which* lies, store the firing pattern in memory Ml PriQrity Interrupt Routine Fig. l(b) Software Structure 277

6 sine wave Lower priority GATED ox intr. pulse OUT1 a) Speed of prime mover=1250 rpm x axis 5 msec/div freq.»41.66 Hz. b) Speed of prime mover*1600 rpra x axis 5msec/div. frsq.»53.33 Hz GATE! 03 Higher priority intr. pulse 0P 0UT1 c) Speed of priaw Bov«r-650 rprn d) d f mov e r=790 rpn. x axis 10 msec/div. Freq Hz x axis u\ Mcfii^ Freq Hz Fig.2. Waveforms at various testpoints for a frequency of 30 Hz and «30 degrees Pig.3. waveforms of R phase to neutral voltage and R phase current for «- 100 d«fr««s.