4G B Die DDRIII SDRAM Specification

Transcription

1 G B Die DDRIII SDRAM Specification PPGBL Deutron Electronics Corp. 8, 68, Sec., NanKing E. RD., Taipei, Taiwan, R.O.C. TEL: (886) AX: (886)

2 G bits DDRL SDRAM DATA SHEET (M words x bits) (5M words x 8 bits) (56M words x 6 bits) Specificatio Deity: G bits Organization 8M word x bits x 8 banks 6M word x8 bits x 8 banks M word x6 bits x 8 banks Package 78-ball BGA(X/X8) 96-ball BGA(X6) Lead-free (RoHS compliant) and Halogen-free Power supply:.5v (typ) =.8V to.5v Backward compatible for, Q =.5V ±.75V Data rate 6/ Mbps (.5V) 866/6/Mbps(.5V) KB page size Row address: A to A5(X/X8) Column address: A to A9,A(X) KB page size A to A9(X8) Row address: A to A(X6) Column address: A to A9(X6) Eight internal banks for concurrent operation Burst length (BL): 8 and with Burst Chop (BC) Burst type (BT): Sequential (8, with BC) Interleave (8, with BC) /CAS Latency (CL): 5, 6, 7, 8, 9,,,(866) /CAS Latency (CL): 5, 6, 7, 8, 9,, (6/) /CAS Write Latency (CWL): 5, 6, 7, 8,9(866) /CAS Write Latency (CWL): 5, 6, 7, 8(6/) eatures Double-data-rate architecture: two data trafers per clock cycle The high-speed data trafer is realized by the 8 bits prefetch pipelined architecture Bi-directional differential data strobe (DQS and /DQS) is tramitted/received with data for capturing data at the receiver DQS is edge-aligned with data for READs; centeraligned with data for WRITEs Differential clock inputs (CK and /CK) DLL alig DQ and DQS traitio with CK traitio Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS Data mask (DM) for write data Posted /CAS by programmable additive latency for better command and data bus efficiency On-Die Termination (ODT) for better signal quality Synchronous ODT Dynamic ODT Asynchronous ODT Multi Purpose Register (MPR) for pre-defined pattern read out ZQ calibration for DQ drive and ODT Programmable Partial Array Self-Refresh (PASR) /RESET pin for Power-up sequence and reset function SRT range: Normal/extended Programmable Output driver impedance control Precharge: auto precharge option for each burst access Driver strength: RZQ/7, RZQ/6 (RZQ = Ω) Refresh: auto-refresh, self-refresh Refresh cycles Average refresh period 7.8μs at C TC +85 C.9μs at +85 C < TC +95 C Operating case temperature range TC = C to +95 C

3 G Bits DDRL SDRAM Part Number P P G B L GJS Detailed Information or detailed electrical specification and further information, please refer to the DDRL SDRAM General unctionality and Electrical Condition data sheet.

4 G Bits DDRL SDRAM Pin Configuratio Pin Configuratio ( / 8 configuration) /xxx indicates active low signal. 78-ball BGA ( configuration) 78-ball BGA ( 8 configuration) A NC NC A NC NU/(/TDQS) B B Q DQ DM Q Q Q DQ DM/TDQS Q Q C Q DQ DQS DQ DQ Q C Q DQ DQS DQ DQ Q D Q NC /DQS Q D Q DQ6 /DQS Q E VREDQ Q NC NC NC Q E VREDQ Q DQ DQ7 DQ5 Q NC /RAS CK NC NC /RAS CK NC G ODT /CAS /CK CKE G ODT /CAS /CK CKE H NC /CS /WE A(AP) ZQ NC H NC /CS /WE A(AP) ZQ NC J BA BA A5 VRECA J BA BA A5 VRECA K A A A(/BC) BA K A A A(/BC) BA L A5 A A A L A5 A A A M A7 A9 A A6 M A7 A9 A A6 N /RESET A A A8 N /RESET A A A8 (Top view) (Top view) Pin name unction Pin name unction A to A5* Address inputs A(AP): Auto precharge RESET* Active low asynchronous reset A(/BC): Burst chop BA to BA* Bank select Supply voltage for internal circuit DQ to DQ7 Data input/output Ground for internal circuit DQS, /DQS Differential data strobe Q Supply voltage for DQ circuit TDQS, /TDQS /CS* /RAS, /CAS, /WE* CKE* CK, /CK Termination data strobe Chip select Command input Clock enable Differential clock input DM Write data mask ODT* Notes:. ODT control Not internally connected with die... Don't connect. Internally connected. Q VREDQ VRECA ZQ NC* NU* Input only pi (address, command, CKE, ODT and /RESET) do not supply termination. Ground for DQ circuit Reference voltage for DQ Reference voltage for CA Reference pin for ZQ calibration No connection Not usable

5 G Bits DDRL SDRAM Pin Configuratio ( 6 configuration) /xxx indicates active low signal. 96-ball BGA A B C D Q Q Q Q DQU5 DQU7 DQU Q /DQSU DQU6 Q DQU DQU DQSU DQU Q Q DMU DQU Q E Q DQL DML Q Q G H J K L M N P R T Q DQL DQSL DQL DQL Q Q DQL6 /DQSL Q VREDQ NC ODT NC Q DQL DQL7 DQL5 Q /RAS CK NC /CAS /CK CKE /CS /WE A(AP) ZQ NC BA BA NC VRECA A A A(/BC) BA A5 A A A A7 A9 A A6 /RESET A A A8 (Top view) Pin name unction Pin name unction Address inputs A to A* /RESET* A(AP): Auto precharge BA to BA* DQU to DQU7 DQL to DQL7 DQSU, /DQSU DQSL, /DQSL /CS* /RAS, /CAS, /WE* CKE* CK, /CK DMU, DML ODT* Notes:.. A(/BC): Burst chop Bank select Data input/output Differential data strobe Chip select Command input Clock enable Differential clock input Write data mask ODT control Not internally connected with die. Q Q VREDQ VRECA ZQ NC* Input only pi (address, command, CKE, ODT and /RESET) do not supply termination. Active low asynchronous reset Supply voltage for internal circuit Ground for internal circuit Supply voltage for DQ circuit Ground for DQ circuit Reference voltage for DQ Reference voltage for CA Reference pin for ZQ calibration No connection

6 G Bits DDRL SDRAM CONTENTS Specificatio... eatures... Ordering Information.... Part Number.. Detailed Information.... Pin Configuratio(x/x8). Pin Configuratio(x6)..... Electrical Conditio Absolute Maximum Ratings Operating Temperature Condition Recommended DC Operating Conditio IDD and IDDQ Measurement Conditio 8 8. Electrical Specificatio DC Characteristics(x/x8/x6) Pin Capacitance..... Standard Speed Bi Package Drawing ball BGA ball BGA Recommended Soldering Conditio

7 G Bits DDRL SDRAM. Electrical Conditio All voltages are referenced to (GND) Execute power-up and Initialization sequence before proper device operation is achieved.. Absolute Maximum Ratings Table : Absolute Maximum Ratings Parameter Symbol Rating Unit Notes Power supply voltage -. to V, Power supply voltage for output Q -. to V, Input voltage VIN -. to V Output voltage VOUT -. to V Reference voltage VRECA -. to x.6 x V Reference voltage for DQ VREDQ -. to x.6 x Q V Storage temperature Tstg -55 to + C, Power dissipation PD. W Short circuit output current IOUT 5 ma Notes:... Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect reliability. Storage temperature is the case surface temperature on the center/top side of the DRAM. and Q must be within mv of each other at all times; and VRE must be no greater than.6 x Q, When and Q are less than 5mV; VRE may be equal to or less than mv. Caution: Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditio outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditio for extended periods may affect device reliability.. Operating Temperature Condition Table : Operating Temperature Condition Parameter Symbol Rating Unit Notes Operating case temperature TC to +95 C,, Notes:... Operating temperature is the case surface temperature on the center/top side of the DRAM. The Normal Temperature Range specifies the temperatures where all DRAM specificatio will be supported. During operation, the DRAM case temperature must be maintained between C to +85 C under all operating conditio. Some applicatio require operation of the DRAM in the Extended Temperature Range between +85 C and +95 C case temperature. ull specificatio are guaranteed in this range, but the following additional conditio apply: a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval trei to.9μs. (This double refresh requirement may not apply for some devices.) b) If Self-refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR bit [A6, A7] = [, ]) or enable the optional Auto Self-Refresh mode (MR bit [A6, A7] = [, ]). 6

8 G Bits DDRL SDRAM. Recommended DC Operating Conditio Table : Recommended DC Operating Conditio (TC = C to +85 C), DDRL Operation Parameter Symbol min. typ. max. Unit Notes Supply voltage V,,, Supply voltage for DQ Q V,,, Notes : Maximum DC value may not be greater than.5v. The DC value is the linear average of /Q(t) over a very long period of time (e.g. sec). If maximum limit is exceeded, input levels shall be governed by DDR specificatio. Under these supply voltages, the device operates to this DDRL specifcation. Once initialized for DDRL operation, DDR operation may only be used if the device is in reset while and Q are changed for DDR operation shown as following timing wave form. Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk CK, /CK, Q (DDR) T(min) = tcksrx, Q (DDRL) T(min) = T(min) = μs T = 5μs /RESET tis CKE T(min) = Valid tdllk tis txpr tmrd tmrd tmrd tmod tzqinit Command * MRS MRS MRS MRS ZQCL * Valid BA tis MR MR MR MR Valid tis ODT Static low in case RTTNore is enabled at time Tg, otherwise static high or low Valid RTT : VIH or VIL Note:. rom time point Td until Tk, NOP or DES commands must be applied between MRS and ZQCL commands. igure : /Q Voltage Switch between DDRL and DDR 7

9 G Bits DDRL SDRAM. IDD and IDDQ Measurement Conditio In this chapter, IDD and IDDQ measurement conditio such as test load and patter are defined. The figure Measurement Setup and Test Load for IDD and IDDQ Measurements shows the setup and test load for IDD and IDDQ measurements. IDD currents (such as IDD, IDD, IDDN, IDDNT, IDDP, IDDP, IDDQ, IDDN, IDDP, IDDR, IDDW, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all balls of the DDR SDRAM under test tied together. Any IDDQ current is not included in IDD currents. IDDQ currents (such as IDDQNT and IDDQR) are measured as time-averaged currents with all Q balls of the DDR SDRAM under test tied together. Any IDD current is not included in IDDQ currents. Note:IDDQ values cannot be directly used to calculate I/O power of the DDR SDRAM. They can be used to support correlation of simulated I/O power to actual I/O power as outlined in correlation from simulated channel I/O power to actual channel I/O power supported by IDDQ measurement. or IDD and IDDQ measurements, the following definitio apply: L and : VIN H and : VIN VIL(AC)max VIH(AC)min MID-LEVEL: defined as inputs are VRE = Q / LOATING: don't care or floating around VRE. Timings used for IDD and IDDQ measurement-loop patter are provided in Timings used for IDD and IDDQ Measurement-Loop Patter table. Basic IDD and IDDQ measurement conditio are described in Basic IDD and IDDQ Measurement Conditio table. Note:The IDD and IDDQ measurement-loop patter need to be executed at least one time before actual IDD or IDDQ measurement is started. Detailed IDD and IDDQ measurement-loop patter are described in IDD Measurement-Loop Pattern table through IDD7 Measurement-Loop Pattern table. IDD Measurements are done after properly initializing the DDR SDRAM. This includes but is not limited to setting. RON = RZQ/7 (Ω in MR); Qoff = B (Output Buffer enabled in MR); RTTNom = RZQ/6 (Ω in MR); RTTWR = RZQ/ (Ω in MR); TDQS eature disabled in MR Define D = {/CS, /RAS, /CAS, /WE} : = {H, L, L, L} Define /D = {/CS, /RAS, /CAS, /WE} : = {H, H, H, H} 8

10 G Bits DDRL SDRAM IDD IDDQ Q /RESET CK, /CK CKE /CS /RAS, /CAS, /WE DDR SDRAM DQS, /DQS, DQ, DM, TDQS, /TDQS RTT = 5Ω Q/ Address, BA ODT ZQ Q igure : Measurement Setup and Test Load for IDD and IDDQ Measurements Application specific memory channel environment IDDQ Test load Channel I/O power simulation IDDQ simulation IDDQ measurement Correlation Correction Channel I/O power number igure : Correlation from Simulated Channel I/O Power to Actual Channel I/O Power Supported by IDDQ Measurement 9

11 G Bits DDRL SDRAM.. Timings Used for IDD and IDDQ Measurement-Loop Patter Table : Timings Used for IDD and IDDQ Measurement-Loop Patter DDR-866 DDR-6 DDR- Parameter Unit CL tck(min) nrcd(min) 9 nrc(min) 5 9 nras(min) 8 nrp(min) 9 naw (KB) 6 naw (KB, KB) nrrd (KB) 5 5 nrrd (KB, KB) nrc (Gb) 88 7 nrc (Gb) nrc (Gb) 8 7

12 G Bits DDRL SDRAM.. Basic IDD and IDDQ Measurement Conditio Table 5: Basic IDD and IDDQ Measurement Conditio Parameter Symbol Description Operating one bank active precharge current Operating one bank active-read-precharge current IDD IDD CKE: H; External clock: on; tck, nrc, nras, CL: see Table 5; BL: 8* ; AL: ; /CS: H between ACT and PRE; Command, address, bank address inputs: partially toggling according to Table 7; Data I/O: MID-LEVEL; DM: stable at ; Bank activity: cycling with one bank active at a time:,,,,,,... (see Table 7); Output buffer and RTT: enabled in MR* ; ODT signal: stable at ; Pattern details: see Table 7 6 CKE: H; External clock: On; tck, nrc, nras, nrcd, CL: see Table 5; BL: 8*, * ; AL: ; /CS: H between ACT, RD and PRE; Command, address, bank address inputs, data I/O: partially toggling according to Table 8; DM: stable at ; Bank activity: cycling with one bank active at a time:,,,,,,... (see Table 8); Output buffer and RTT: enabled in MR* ; ODT Signal: stable at ; Pattern details: see Table 8 Precharge standby current CKE: H; External clock: on; tck, CL: see Table 5 BL: 8* ; AL: ; /CS: stable at ; IDDN Command, address, bank address Inputs: partially toggling according to Table 9; data I/O: MID-LEVEL; DM: stable at ; bank activity: all banks closed; output buffer and RTT: enabled in mode registers* ; ODT signal: stable at ; pattern details: see Table 9 Precharge standby ODT current Precharge standby ODT IDDQ current Precharge power-down current slow exit Precharge power-down current fast exit Precharge quiet standby current IDDNT IDDQNT IDDP IDDP IDDQ CKE: H; External clock: on; tck, CL: see Table 5; BL: 8* ; AL: ; /CS: stable at ; Command, address, bank address Inputs: partially toggling according to Table ; data I/O: MID-LEVEL; DM: stable at ; bank activity: all banks closed; output buffer and RTT: enabled in MR* ; ODT signal: toggling according to Table ; pattern details: see Table Same definition like for IDDNT, however measuring IDDQ current itead of IDD current CKE: L; External clock: on; tck, CL: see Table 5; BL: 8* ; AL: ; /CS: stable at ; Command, address, bank address inputs: stable at ; data I/O: MID-LEVEL; DM: stable at ; bank activity: all banks closed; output buffer and RTT: EMR* ; ODT signal: stable at ; precharge power down mode: slow exit* CKE: L; External clock: on; tck, CL: see Table 6; BL: 8* ; AL: ; /CS: stable at ; Command, address, bank address Inputs: stable at ; data I/O: MID-LEVEL; DM:stable at ; bank activity: all banks closed; output buffer and RTT: enabled in MR* ; ODT signal: stable at ; precharge power down mode: fast exit* CKE: H; External clock: On; tck, CL: see Table 5; BL: 8* ; AL: ; /CS: stable at ; Command, address, bank address Inputs: stable at ; data I/O: MID-LEVEL; DM: stable at ;bank activity: all banks closed; output buffer and RTT: enabled in MR*; ODT signal: stable at CKE: H; External clock: on; tck, CL: see Table 5; BL: 8* ; AL: ; /CS: stable at ; Active standby current IDDN Command, address, bank address Inputs: partially toggling according to Table 9; data I/O: MID-LEVEL; DM: stable at ; bank activity: all banks open; output buffer and RTT: enabled in MR* ; ODT signal: stable at ; pattern details: see Table 9 Active power-down current Operating burst read current Operating burst read IDDQ current IDDP IDDR IDDQR CKE: L; External clock: on; tck, CL: see Table 5; BL: 8* ; AL: ; /CS: stable at ; Command, address, bank address inputs: stable at ; data I/O: MID-LEVEL; DM:stable at ; bank activity: all banks open; output buffer and RTT: enabled in MR* ; ODT signal: stable at 6 CKE: H; External clock: on; tck, CL: see Table 5; BL: 8*, * ; AL: ; /CS: H between RD; Command, address, bank address Inputs: partially toggling according to Table ; data I/O: seamless read data burst with different data between one burst and the next one according to Table ; DM: stable at ; bank activity: all banks open, RD commands cycling through banks:,,,,,,... (see Table ); Output buffer and RTT: enabled in MR* ; ODT signal: stable at ; pattern details: see Table Same definition like for IDDR, however measuring IDDQ current itead of IDD current

13 G Bits DDRL SDRAM Table 6: Basic IDD and IDDQ Measurement Conditio (cont d) Parameter Symbol Description CKE: H; External clock: on; tck, CL: see Table 5; BL: 8* ; AL: ; /CS: H between WR; Operating burst write current IDDW command, address, bank address inputs: partially toggling according to Table ; data I/O: seamless write data burst with different data between one burst and the next one according to IDDW Measurement-Loop Pattern table; DM: stable at ; bank activity: all banks open, WR commands cycling through banks:,,,,,,.. (see Table ); Output buffer and RTT: enabled in MR* ; ODT signal: stable at H; pattern details: see Table Burst refresh current Self-refresh current: normal temperature range Self-refresh current: extended temperature range Auto self-refresh current (Optional) Operating bank interleave read current RESET low current IDD5B IDD6 IDD6ET IDD6TC IDD7 IDD8 CKE: H; External clock: on; tck, CL, nrc: see Table 5; BL: 8* ; AL: ; /CS: H between RE; Command, address, bank address Inputs: partially toggling according to Table ; data I/O: MID-LEVEL; DM: stable at ; bank activity: RE command every nrc (Table ); output buffer and RTT: enabled in MR* ; ODT signal: stable at ; pattern details: see Table TC: to 85 C; ASR: disabled* ; SRT: 5 Normal* ; CKE: L; External clock: off; CK and /CK: L; CL: see Table 5; BL: 8* ; AL: ; /CS, command, address, bank address, data I/O: MID-LEVEL; DM: stable at ; bank activity: Self-refresh operation; output buffer and RTT: enabled in MR* ; ODT signal: MID-LEVEL 5 TC: to 95 C; ASR: Disabled* ; SRT: Extended* ; CKE: L; External clock: off; CK and /CK: L; CL: Table 5; BL: 8* ; AL: ; /CS, command, address, bank address, data I/O: MID-LEVEL; DM: stable at ; bank activity: Extended temperature self-refresh operation; output buffer and RTT: enabled in MR* ; ODT signal: MID-LEVEL 5 TC: to 95 C; ASR: Enabled* ; SRT: Normal* ; CKE: L; External clock: off; CK and /CK: L; CL: Table 5; BL: 8* ; AL: ; /CS, command, address, bank address, data I/O: MID-LEVEL; DM: stable at ; bank activity: Auto self-refresh operation; output buffer and RTT: enabled in MR* ; ODT signal: MID-LEVEL CKE: H; External clock: on; tck, nrc, nras, nrcd, nrrd, naw, CL: see Table 5; 6 BL: 8*, * ; AL: CL-; /CS: H between ACT and RDA; Command, address, bank address Inputs: partially toggling according to Table ; data I/O: read data bursts with different data between one burst and the next one according to Table ; DM: stable at ; bank activity: two times interleaved cycling through banks (,, 7) with different addressing, see Table ; output buffer and RTT: enabled in MR*; ODT signal: stable at ; pattern details: see Table /RESET: low; External clock: off; CK and /CK: low; CKE: LOATING; /CS, command, address, bank address, Data IO: LOATING; ODT signal: LOATING RESET low current reading is valid once power is stable and /RESET has been low for at least ms. Notes: Burst Length: BL8 fixed by MRS: MR bits [,] = [,]. MR: Mode Register Output buffer enable: set MR bit A = and MR bits [5, ] = [,]; RTTNom enable: set MR bits [9, 6, ] = [,, ]; RTTWR enable: set MR bits [, 9] = [,]. Precharge power down mode: set MR bit A= for Slow Exit or MR bit A = for fast exit. Auto self-refresh (ASR): set MR bit A6 = to disable or to enable feature. Self-refresh temperature range (SRT): set MR bit A7= for normal or for extended temperature range. Read burst type: nibble sequential, set MR bit A =

14 G Bits DDRL SDRAM Table 7: IDD Measurement-Loop Pattern CK, /CK CKE Sub -Loop Cycle number Com- Mand /CS /RAS /CAS /WE ODT BA* A -Am A A7 -A9 A -A6 A -A Data* ACT, D, D, /D, /D Repeat pattern until nras -, truncate if necessary nras PRE Repeat pattern... until nrc -, truncate if necessary X nrc ACT + X nrc D, D +, X nrc /D, /D Toggling Static H +, Repeat pattern nrc +,..., until x nrc + Nras -, truncate if necessary X nrc PRE + nras Repeat nrc +,..., until x nrc -, truncate if necessary nrc Repeat Sub-Loop, use BA= itead nrc Repeat Sub-Loop, use BA= itead 6 nrc Repeat Sub-Loop, use BA= itead 8 nrc Repeat Sub-Loop, use BA= itead 5 nrc Repeat Sub-Loop, use BA= 5 itead 6 nrc Repeat Sub-Loop, use BA= 6 itead 7 nrc Repeat Sub-Loop, use BA= 7 itead Notes:.... DM must be driven low all the time. DQS, /DQS are MID-LEVEL. DQ signals are MID-LEVEL. BA: BA to BA. Am: m mea Most Significant Bit (MSB) of Row address.

15 G Bits DDRL SDRAM Table 8: IDD Measurement-Loop Pattern CK, /CK CKE Sub -Loop Cycle number Com- mand /CS /RAS /CAS /WE ODT BA* A -Am A A7 - A A A9 -A6 -A Data* ACT, D, D, /D, /D Repeat pattern... until nrcd -, truncate if necessary nrcd RD Repeat pattern... until nras -, truncate if necessary Toggling Static H nras PRE Repeat pattern... until nrc -, truncate if necessary x nrc ACT + x nrc D, D +, x nrc /D, /D +, Repeat pattern nrc +,..., until nrc + nrcd -, truncate if necessary x nrc RD + nrcd Repeat pattern nrc +,..., until nrc +nras -, truncate if necessary x nrc PRE + nras Repeat pattern nrc +,..., until x nrc -, truncate if necessary nrc Repeat Sub-Loop, use BA= itead nrc Repeat Sub-Loop, use BA= itead 6 nrc Repeat Sub-Loop, use BA= itead 8 nrc Repeat Sub-Loop, use BA= itead 5 nrc Repeat Sub-Loop, use BA= 5 itead 6 nrc Repeat Sub-Loop, use BA= 6 itead 7 nrc Repeat Sub-Loop, use BA= 7 itead Notes:.... DM must be driven low all the time. DQS, /DQS are used according to read commands, otherwise MID-LEVEL. Burst sequence driven on each DQ signal by read command. Outside burst operation, DQ signals are MID-LEVEL. BA: BA to BA. Am: m mea Most Significant Bit (MSB) of Row address.

16 G Bits DDRL SDRAM Table 9: IDDN and IDDN Measurement-Loop Pattern CK, /CK CKE Sub -Loop Cycle number Com- Mand /CS /RAS /CAS /WE ODT BA* A -Am A A7 -A9 A -A6 A -A Data* D D /D /D Toggling Static H to 7 8 to to 5 6 to 9 to to 7 8 to Repeat Sub-Loop, use BA= itead Repeat Sub-Loop, use BA= itead Repeat Sub-Loop, use BA= itead Repeat Sub-Loop, use BA= itead Repeat Sub-Loop, use BA= 5 itead Repeat Sub-Loop, use BA= 6 itead Repeat Sub-Loop, use BA= 7 itead Notes:.... DM must be driven low all the time. DQS, /DQS are MID-LEVEL. DQ signals are MID-LEVEL. BA: BA to BA. Am: m mea Most Significant Bit (MSB) of Row address. Table : IDDNT and IDDQNT Measurement-Loop Pattern CK, /CK CKE Sub -Loop Cycle number Com- Mand /CS /RAS /CAS /WE ODT BA* A -Am A A7 -A9 A -A6 A -A Data* D D /D /D Toggling Static H to 7 8 to to 5 6 to 9 to to 7 8 to Repeat Sub-Loop, but ODT = and BA= Repeat Sub-Loop, but ODT = and BA= Repeat Sub-Loop, but ODT = and BA= Repeat Sub-Loop, but ODT = and BA= Repeat Sub-Loop, but ODT = and BA= 5 Repeat Sub-Loop, but ODT = and BA= 6 Repeat Sub-Loop, but ODT = and BA= 7 Notes:.... DM must be driven low all the time. DQS, /DQS are MID-LEVEL. DQ signals are MID-LEVEL. BA: BA to BA. Am: m mea Most Significant Bit (MSB) of Row address. 5

17 G Bits DDRL SDRAM Table : IDDR and IDDQR Measurement-Loop Pattern CK, /CK CKE Sub -Loop Cycle number Com- mand /CS /RAS /CAS /WE ODT BA* A -Am A A7 -A9 A -A6 A -A Data* RD D, /D, /D RD 5 D 6,7 /D, /D Toggling Static H to 5 6 to to to 9 to 7 8 to to 6 Repeat Sub-Loop, but BA= Repeat Sub-Loop, but BA= Repeat Sub-Loop, but BA= Repeat Sub-Loop, but BA= Repeat Sub-Loop, but BA= 5 Repeat Sub-Loop, but BA= 6 Repeat Sub-Loop, but BA= 7 Notes:.... DM must be driven low all the time. DQS, /DQS are used according to read commands, otherwise MID-LEVEL. Burst sequence driven on each DQ signal by read command. Outside burst operation, DQ signals are MID-LEVEL. BA: BA to BA. Am: m mea Most Significant Bit (MSB) of Row address. 6

18 G Bits DDRL SDRAM Table : IDDW Measurement-Loop Pattern CK, /CK CKE Sub -Loop Cycle number Com- Mand /CS /RAS /CAS /WE ODT BA* A -Am A A7 -A9 A -A6 A -A Data* WR D, /D, /D WR 5 D 6,7 /D, /D Toggling Static H to 5 6 to to to 9 to 7 8 to to 6 Repeat Sub-Loop, but BA= Repeat Sub-Loop, but BA= Repeat Sub-Loop, but BA= Repeat Sub-Loop, but BA= Repeat Sub-Loop, but BA= 5 Repeat Sub-Loop, but BA= 6 Repeat Sub-Loop, but BA= 7 Notes:.... DM must be driven low all the time. DQS, /DQS are used according to write commands, otherwise MID-LEVEL. Burst sequence driven on each DQ signal by write command. Outside burst operation, DQ signals are MID-LEVEL. BA: BA to BA. Am: m mea Most Significant Bit (MSB) of Row address. Table : IDD5B Measurement-Loop Pattern CK, /CK CKE Sub Cycle Com- -Loop number mand /CS /RAS /CAS /WE ODT BA* A -Am A A7 -A9 A -A6 A -A Data* RE, D, /D, /D 5 to 8 Repeat cycles..., but BA= 9 to Repeat cycles..., but BA= Toggling Static H to 6 7 to Repeat cycles..., but BA= Repeat cycles..., but BA= to Repeat cycles..., but BA= 5 5 to 8 Repeat cycles..., but BA= 6 9 to Repeat cycles..., but BA= 7 to Repeat Sub-Loop, until nrc -. Truncate, if necessary. nrc - Notes:.... DM must be driven low all the time. DQS, /DQS are MID-LEVEL. DQ signals are MID-LEVEL. BA: BA to BA. Am: m mea Most Significant Bit (MSB) of Row address. 7

19 G Bits DDRL SDRAM Table : IDD7 Measurement-Loop Pattern CK, /CK CKE Sub -Loop Cycle number Com- mand /CS /RAS /CAS /WE ODT BA* A A7 A A -Am A -A9 -A6 -A Data* ACT RDA D Repeat above D Command until nrrd - nrrd ACT nrrd + nrrd + RDA D Repeat above D Command until nrrd - x nrrd Repeat Sub-Loop, but BA= x nrrd Repeat Sub-Loop, but BA= x nrrd D Assert and repeat above D Command until naw -, if necessary naw naw + nrrd naw + x nrrd naw + x nrrd Repeat Sub-Loop, but BA= Repeat Sub-Loop, but BA= 5 Repeat Sub-Loop, but BA= 6 Repeat Sub-Loop, but BA= 7 9 naw D 7 + x nrrd Assert and repeat above D Command until x naw -, if necessary x naw ACT + x naw Toggling Static H RDA + x naw D + x naw + nrrd x naw + nrrd + x naw D Repeat above D Command until x naw + nrrd - ACT RDA + nrrd + Repeat above D Command until x naw + x nrrd - x naw Repeat Sub-Loop, but BA= + x nrrd x naw Repeat Sub-Loop, but BA= + x nrrd x naw D + x nrrd Assert and repeat above D Command until x naw -, if necessary x naw Repeat Sub-Loop, but BA= x naw Repeat Sub-Loop, but BA= 5 +nrrd x naw Repeat Sub-Loop, but BA= 6 + x nrrd x naw + x nrrd Repeat Sub-Loop, but BA= 7 x naw D + x nrrd 7 Assert and repeat above D Command until x naw -, if necessary Notes:.... DM must be driven low all the time. DQS, /DQS are used according to read commands, otherwise MID-LEVEL. Burst sequence driven on each DQ signal by read command. Outside burst operation, DQ signals are MID-LEVEL. BA: BA to BA. Am: m mea Most Significant Bit (MSB) of Row address. 8

20 G Bits DDRL SDRAM.. Electrical Specificatio(x/x8/x6) DC Characteristics Table 5: DC Characteristics (TC = C to +85 C,, Q =.5V) x x8 x6 Parameter Symbol Data rate (Mbps) max. max. max Unit Notes Operating current (ACT-PRE) Operating current (ACT-READ-PRE) IDD IDD ma ma Precharge power-down standby current IDDP IDDP ma ma ast PD Exit Slow PD Exit Precharge standby current IDDN ma Precharge standby ODT current IDDNT ma Precharge quiet standby current IDDQ ma Active power-down current (Always fast exit) IDDP ma Active standby current IDDN ma Operating current (Burst read operating) IDDR ma Operating current (Burst write operating) IDDW ma Burst refresh current IDD5B ma All bank interleave read current IDD ma RESET low current IDD ma 866/6/ Self-Refresh Current (TC = C to +85 C,, Q =.5V) x x8 x6 Parameter Symbol Grade. max. max. max. Unit Notes Self-refresh curre normal temperature range IDD6 866/6/ ma Self-refresh current. 866/6/ extended temperature range IDD6E ma Auto self-refresh current (Optional) IDD6TC 866/6/ 一一一 ma 9

21 G Bits DDRL SDRAM. Pin Capacitance Table 6: Pin Capacitance [DDR- to 6] (TC = 5 C,, Q =.8V to.5v) DDRL-866 DDRL-6 DDRL- Parameter Symbol Min Max Min Max Min Max Units Notes Input/output capacitance CIO p, Input capacitance, CK and /CK CCK p Input capacitance delta, CK and /CK CDCK p, Input/output capacitance delta, DQS and /DQS Input capacitance, (control, address, command, input-only pi) Input capacitance delta, (All control input-only pi) CDDQS p, CI p, 5 CDICTRL p, 6, 7 Input capacitance delta, (All addres/command input-only pi) CDIADD CMD p, 8, 9 Input/output capacitance delta, DQ,DM, DQS, /DQS, TDQS, /TDQS Input/output capacitance of ZQ pin CDIO p, CZQ p, Notes:. Although the DM, TDQS and /TDQS pi have different functio, the loading matches DQ and DQS.., Q,, Q applied and all other pi floating (except the pin under test, CKE, /RESET and ODT as necessary). = Q =.5V, VBIAS=/ and ondie termination off.. Absolute value of CCK-C/CK.. Absolute value of CIO(DQS)-CIO(/DQS). 5. CI applies to ODT, /CS, CKE, A-A5, BA-BA, /RAS, /CAS and /WE. 6. CDICTRL applies to ODT, /CS and CKE. 7. CDICTRL = CI(CTRL) -.5 x (CI(CK)+CI(/CK)). 8. CDIADDCMD applies to A-A5, BA-BA, /RAS, /CAS and /WE. 9. CDIADDCMD = CI(ADDCMD) -.5 x (CI(CK)+CI(/CK)).. CDIO=CIO(DQ,DM) -.5 x (CIO(DQS)+CIO(/DQS)).. Maximum external load capacitance on ZQ pin: 5p.

22 G Bits DDRL SDRAM. Standard Speed Bi Table 7: DDR-866 Speed Bi Speed Bin DDR-866 CL-tRCD-tRP -- Symbol /CAS write latency min max Unit Notes taa.9 trcd.9 trp.9 trc 7.9 tras. 9 x trei 8 CWL = 5..,,, 8 CWL = 6, 7, 8,9 CWL = 5.5.,,, 8 CWL = 6 CWL = 7, 8,9 CWL = 5 CWL = ,,, 8 CWL = 7,8,9 CWL = 5 CWL = ,,, 8 CWL = 7 CWL = 8,9 CWL = 5, 6 CWL= ,,, 8 CWL= 8 CWL= 9 CWL = 5, 6 CWL= 7 CWL= ,,,8 CWL = 5, 6, 7 CWL= 8.5.5,,, 8 CWL= 9 CWL = 5, 6, 7,8 CWL= 9 CWL = 5, 6, 7,8 CWL= Supported CL settings 5, 6, 7, 8, 9,,,,,,8 Supported CWL settings 5, 6, 7, 8,9

23 G Bits DDRL SDRAM Table 8: DDR-6 Speed Bi Speed Bin DDR-6 CL-tRCD-tRP -- Symbol /CAS write latency min max Unit Notes taa.75 (.5) 9 trcd.75 (.5) 9 trp.75 (.5) 9 trc 8.75 (8.5) 9 tras 5 9 x trei 8 CWL = 5..,,,, 7, CWL = 6, 7, 8 CWL = 5.5.,,, 7 CWL = 6 CWL = 7, 8 CWL = 5 CWL = <.5,,,, 7 CWL = 7 CWL = 8 CWL = 5 CWL = <.5,,, 7 CWL = 7 CWL = 8 CWL = 5, 6 CWL= 7.5 <.875,,,, 7 CWL= 8 CWL = 5, 6 CWL= 7.5 <.875,,, 7 CWL= 8 CWL = 5, 6, 7 CWL= 8.5 <.5,, Supported CL settings Supported CWL settings 5, 6, 7, 8, 9,, 5, 6, 7, 8

24 G Bits DDRL SDRAM Table 9 DDR- Speed Bi Speed Bin DDR- CL-tRCD-tRP Symbol /CAS write latency min max Unit Notes taa.5 (.5) 9 trcd.5 (.5) 9 trp.5 (.5) 9 trc 9.5 (9.5) 9 tras 6 9 x trei 8 CWL = 5..,,,, 6, CWL = 6, 7 CWL = 5.5.,,, 6 CWL = 6 CWL = 7 CWL = 5 CWL = <.5,,,, 6 CWL = 7 CWL = 5 CWL = <.5,,, 6 CWL = 7 CWL = 5, 6 CWL= 7.5 <.875,,, CWL = 5, 6 CWL= 7.5 <.875,, Supported CL settings 5, 6, 7, 8, 9, Supported CWL settings 5, 6, 7

25 G Bits DDRL SDRAM Notes:. The CL setting and CWL setting result in tck(avg)min and tck(avg)max requirements. When making a selection of tck(avg), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.. tck(avg)min limits: Since /CAS latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tck(avg) value (.,.5,.875,.5, or.5) when calculating CL() = taa() / tck(avg)(), rounding up to the next Supported CL.. tck(avg)max limits: Calculate tck(avg) + taa(max)/cl selected and round the resulting tck(avg) down to the next valid speed bin (i.e.. or.5 or.875 or.5). This result is tck(avg)max corresponding to CL selected.. settings are not allowed. User must program a different value. 5. Any DDR- speed bin also supports functional operation at lower frequencies as shown in the table DDR- Speed Bi which is not subject to production tests but verified by design/characterization. 6. Any DDR-6 speed bin also supports functional operation at lower frequencies as shown in the table DDR-6 Speed Bi which is not subject to production tests but verified by design/characterization. 7. trei depends on operating case temperature (TC). 8. or devices supporting optional down binning to CL = 7 and CL = 9, taa/trcd/trp(min) must be.5 or lower. SPD settings must be programmed to match. 9. DDR-8 AC timing apply if DRAM operates at lower than 8 MT/s data rate.

26 G Bits DDRL SDRAM. Package Drawing. 78-ball BGA. Solder ball: Lead free (Sn-Ag-Cu) 5

27 G Bit DDRL SDRAM. 96-ball BGA Solder ball: Lead free (Sn-Ag-Cu) 6

28 G Bits DDRL SDRAM. Recommended Soldering Conditio Please coult with our sales offices for soldering conditio of the G bits DDR SDRAM. Type of Surface Mount Device PPGBL, PPGBL:78-ball BGA < Lead free (Sn-Ag-Cu) > PPGBL:96-ball BGA < Lead free (Sn-Ag-Cu) > 7

29 G Bits DDRL SDRAM NOTES OR CMOS DEVICES PRECAUTION AGAINST ESD OR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using iulators that easily build static electricity. MOS devices must be stored and traported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautio need to be taken for PW boards with semiconductor MOS devices on it. HANDLING O UNUSED INPUT PINS OR CMOS DEVICES No connection for CMOS devices input pi can be a cause of malfunction. If no connection is provided to the input pi, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to or GND with a resistor, if it is coidered to have a possibility of being an output pin. The unused pi must be handled in accordance with the related specificatio. STATUS BEORE INITIALIZATION O MOS DEVICES Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. 8