Micro MINI S1C60N08/60R08

Transcription

1 Low oltage peration Products PF245-0 Micro MN SC60N08/60R08 4-bit Single Chip Microcomputer SC60C Core CPU Built-in LCD Driver Serial nterface DESCRPTN The SC60N08 Series is a single-chip microcomputer made up of the 4-bit core CPU SC60C, RM (4,096 words 2 bits), RAM (82 words 4 bits), LCD driver, serial interface, event counter with dial input function, watchdog timer, and two types of time base counter. Because of its low-voltage operation and low power consumption, this series is ideal for a wide range of applications, and is especially suitable for battery-driven systems. The SC60R08 is a microcomputer with a CMS 4-bit core CPU SC60C as main component, and a built-in programmable RAM (RM emulator). The SC60R08 has almost the same functions as the SC60N08/60A08. The mask RM in the SC60N08/60A08 has been changed to a RM emulator that allows the user to rewrite programs using a Serial EEPRM. CNFGULATN The SC60N08 Series is configured as follows, depending on supply voltage and oscillation circuits. Model Supply voltage scillation circuit Evaluation tool SC60N08.0 SC only (Single clock) SC60R08 SC60A08.0 SC and SC (Twin clock) SC60L08.5 SC only (Single clock) FEATURES SC oscillation circuit... Crystal oscillation circuit khz (Typ.)/8.400 khz (Typ.) SC oscillation circuit... CR or ceramic oscillation circuit ( ) 0 khz (Typ.)...SC60A08/60R08 only nstruction set... 8 types nstruction execution time... CLK = khz 5 µsec, 24 µsec, 66 µsec (differs depending on instruction) CLK = khz 0 µsec, 82 µsec, µsec (CLK CPU operation frequency) CLK = 0 khz µsec, 4 µsec, 24 µsec...sc60a08/60r08 only RM capacity... 4,096 words 2 bits Serial EEPRM interface... Built-in (Microchip 24AA65 two wire bus protocol interfaces...sc60r08 only RAM capacity words 4 bits nput ports... 9 bits (pull-down resistor can be added ) utput ports... 8 bits (BZ, BZ, FUT and SF outputs are available ) / ports... 8 bits (pull-down resistor is added during input data read-out) Serial interface... port (8-bit clock synchronous system) LCD driver segments 4,, or 2 commons ( ) - /4, / or /2 duty (voltage regulator and booster circuits built-in) Time base counter... Two types (timer and stopwatch) Watchdog timer... Built-in ( )

2 Event counter... Two 8-bit inputs (dial input evaluation or independent) Sound generator... Programmable in 8 sounds (8 frequencies) Digital envelope built-in ( )... nverted input, non-inverted input Battery low detection circuit (BLD).. Dual system (programmable in 8 values and a fixed value) 2.4, SC60N08/60A08/60R08.2, SC60L08 External interrupt... nput interrupt systems nternal interrupt... Time base counter interrupt 2 systems Serial interface interrupt system Supply voltage....0 (.8.5 )...SC60N08/60A08/60R08.5 (0.9.7 )...SC60L08 Current consumption... SC60N08 Halt state.0 when CLK = khz (Typ.) Run state 2.2 when CLK = khz (Typ.) SC60L08 Halt state.0 when CLK = khz (Typ.) Run state 2.2 when CLK = khz (Typ.) SC60A08 Halt state. when CLK = khz (Typ.) Run state.0 when CLK = khz (Typ.) Run state when CLK = 0 khz (Typ.) SC60R08 Halt state.0 when CLK = khz (Typ.)...Target for SC60N08. when CLK = khz (Typ.)...Target for SC60A08 Run state 6.5 when CLK = khz (Typ.)...Target for SC60N when CLK = khz (Typ.)...Target for SC60A08 Run state 5 when CLK = 0 khz (Typ.)...Target for SC60A08 only Package... QFP5-0pin, QFP5-0pin (plastic) or chip Can be selected with mask option 2

3 BLCK DAGRAM SC60N08/60L08/60A08 SC60A08 only RM 4,096 words 2 bits System Reset Control RESET Core CPU SC60C SC SC2 SC SC4 SC nterrupt Generator RAM 82 words 4 bits nput Port K00K0, K KK2 TEST CM0 SEG047 LCD Driver 48 SEG 4 CM / Port P00P0 PP DD L L2 L CA CB S SS Power Controller utput Port Sound Generator R00R0 RR SD Serial /F SN SUT SCLK Event Counter Timer AMPP AMPM Comparator Stopwatch SC60R08 SDA SCL Serial EEPRM nterface Error Detecting Circuit ERRUT RM Emulator 4,096 words 2 bits System Reset Control TPRST RESET Core CPU SC60C SC SC2 SC SC4 SC nterrupt Generator RAM 82 words 4 bits nput Port K00K0, K KK2 TEST CM0 SEG047 LCD Driver 48 SEG 4 CM / Port P00P0 PP DD L L2 L CA CB S SS Power Controller utput Port Sound Generator R00R0 RR SD Serial /F SN SUT SCLK Event Counter Timer AMPP AMPM Comparator Stopwatch

4 4 SC60N08/60R08 PN CNFGURATN SC60N08/60L08/60A08 Pin Configuration CM CM0 SEG47 SEG46 SEG45 SEG44 SEG4 SEG42 SEG4 SEG40 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG SEG2 SEG SEG SEG SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG SEG2 SEG SEG0 AMPP AMPM K2 K22 K2 K K K0 K SEG29 SEG28 SEG27 SEG26 SEG SEG24 TEST SEG2 SEG22 SEG2 SEG SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG SEG2 SEG K0 K00 SN SUT N.C. SCLK P0 P02 P0 P00 N.C. N.C. P P2 P P R0 R02 R0 R00 N.C. = No Connection R2 R R R SS RESET SC4 SC S SC2 SC DD L L2 L CA CB N.C. CM CM NDEX SC60N08/60L08/60A08 QFP5-0pin NDEX SEG47 SEG46 SEG45 SEG44 SEG4 SEG42 SEG4 SEG40 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG SEG2 SEG SEG0 SEG29 SEG SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG SEG2 SEG SEG0 AMPP AMPM K2 K22 K2 K K K0 K02 K SEG27 SEG26 SEG SEG24 TEST SEG2 SEG22 SEG2 SEG SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG SEG2 N.C. SEG SEG K00 SN SUT N.C. SCLK N.C. P0 P02 P0 P00 P P2 P P R0 R02 R0 R00 R2 R N.C. = No Connection R R SS RESET SC4 SC S SC2 SC DD L L2 L CA CB N.C. CM CM2 CM CM0 SC60N08/60L08/60A08 QFP5-0pin

5 SC60N08/60L08/60A08 Pin Description Pin name Pin No. QFP5-0 QFP5-0 / Function DD SS S L L2 L CA, CB SC SC2 SC SC4 K00K0 K KK2 P00P0 PP R00R0 R R R R2 SN SUT SCLK AMPP AMPM , , () () / / / Power supply pin (+) Power supply pin (-) scillation and internal logic system voltage output pin LCD drive voltage output pin (approx or /2 L2) LCD drive voltage output pin (2 L or approx. -2. ) LCD drive voltage output pin ( L or /2 L2) Boost capacitor connecting pin Cryctal oscillation input pin Crystal oscillation output pin CR or ceramic oscillation input pin (N.C. for SC60N08 and SC60L08) CR or ceramic oscillation output pin (N.C. for SC60N08 and SC60L08) nput port pin nput port pin nput port pin / port pin / port pin utput port pin utput port pin or BZ output pin utput port pin or BZ output pin utput port pin or SF output pin utput port pin or FUT output pin Serial interface data input pin Serial interface data output pin Serial interface clock input/output pin non-inverted input pin inverted input pin SEG , 26 9, 726, 24 LCD segment output pin or DC output pin CM0 RESET TEST 2,, 0, LCD common output pin (/2, / or /4 duty are selectable ) nitial reset input pin nput pin for test Can be selected by mask option 5

6 6 SC60N08/60R08 SC60R08 Pin Configuration CM CM0 SEG47 SEG46 SEG45 SEG44 SEG4 SEG42 SEG4 SEG40 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG SEG2 SEG SEG SEG SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG SEG2 SEG SEG0 AMPP AMPM K2 K22 K2 K K K0 K SEG29 SEG28 SEG27 SEG26 SEG SEG24 TEST SEG2 SEG22 SEG2 SEG SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG SEG2 SEG K0 K00 SN SUT TPRST SCLK P0 P02 P0 P00 SCL SDA P P2 P P R0 R02 R0 R R2 R R R SS RESET SC4 SC S SC2 SC DD L L2 L CA CB ERRUT CM CM NDEX SC60R08 QFP5-0pin NDEX SEG47 SEG46 SEG45 SEG44 SEG4 SEG42 SEG4 SEG40 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG SEG2 SEG SEG0 SEG29 SEG SEG8 SEG7 SEG6 SEG5 SEG4 SEG SEG2 SEG SEG0 AMPP AMPM K2 K22 K2 K K K0 K02 K0 K SEG27 SEG26 SEG SEG24 TEST SEG2 SEG22 SEG2 SEG SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG SEG2 SEG SEG SEG SN SUT TPRST SCLK P0 P02 P0 P00 SCL SDA P P2 P P R0 R02 R0 R00 R2 R R R SS RESET SC4 SC S SC2 SC DD L L2 L CA CB ERRUT CM CM2 CM CM0 SC60R08 QFP5-0pin

7 SC60R08 Pin Description Pin name DD SS S L L2 L CA, CB SC SC2 SC SC4 K00K0 K KK2 P00P0 PP R00R0 R R R2 R SN SUT SCLK AMPP AMPM SEG047 CM0 RESET TEST SCL SDA ERRUT TPRST Pin No. QFP5-0 QFP , 97 94, , , 24 2,, 0, Can be selected by mask option / () () / / / / Function Power supply pin (+) Power supply pin (-) scillation and internal logic system voltage output pin LCD drive voltage output pin (approx or /2 L2) LCD drive voltage output pin (2 L or approx. -2. ) LCD drive voltage output pin ( L or /2 L2) Boost capacitor connecting pin Crystal oscillation input pin Crystal oscillation output pin CR or ceramic oscillation input pin * CR or ceramic oscillation output pin * nput port pin nput port pin nput port pin / port pin / port pin utput port pin utput port pin or BZ output pin * utput port pin or SF output pin * utput port pin or FUT output pin * utput port pin or BZ output pin * Serial interface data input pin Serial interface data output pin Serial interface clock input/output pin non-inverted input pin inverted input pin LCD segment output pin or DC output pin * LCD common output pin (/2, / or /4 duty are selectable *) nitial reset input pin nput pin for test Serial EEPRM clock output pin Serial EEPRM data input/output pin Errout detecting singnal output for download program Cold reset pin for re-start download program from EEPRM 7

8 PTN LST. DECE TYPE DECE TYPE.... SC60N08 2. SC60L08. SC60A08 CLCK TYPE (for Evaluation board). 2 khz 2. SC SYSTEM CLCK (only for SC60A08). CR (Normal Type) (Low Power Type) (Note) (Twin Clock Type) 2. 8 khz 2. Ceramic. MULTPLE KEY ENTRY RESET CMBNATN.... Not Use 2. Use K00, K0. Use K00, K0, K02 4. Use K00, K0, K02, K0 TME AUTHRZE.... Use 2. Not Use 4. WATCHDG TMER. Use 2. Not Use 5. NPUT NTERRUPT NSE REJECTR K00K0.... Use K.... Use KK2.... Use 6. NPUT PRT PULL DWN RESSTR K With Resistor K0.... With Resistor K With Resistor K0.... With Resistor K.... With Resistor K.... With Resistor K2.... With Resistor K With Resistor K2.... With Resistor 7. UTPUT PRT SPECFCATN (R00R0) R Complementary R0.... Complementary R Complementary R0.... Complementary 8. R SPECFCATN UTPUT SPECFCATN.... Complementary UTPUT TYPE.... DC utput 9. R SPECFCATN UTPUT SPECFCATN.... Complementary UTPUT TYPE.... DC utput 2. Not Use 2. Not Use 2. Not Use 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Pch-penDrain 2. Pch-penDrain 2. Pch-penDrain 2. Pch-penDrain 2. Pch-penDrain 2. Buzzer utput 2. Pch-penDrain 2. S Flag. R2 SPECFCATN UTPUT SPECFCATN.... Complementary 2. Pch-penDrain UTPUT TYPE.... DC utput 2. FUT 2768 or 8400 [Hz]. FUT 684 or 90 [Hz] 4. FUT 892 or 9600 [Hz] 5. FUT 4096 or 4800 [Hz] 6. FUT 48 or 2400 [Hz] 7. FUT 24 or 0 [Hz] 8. FUT 52 or 600 [Hz] 9. FUT 6 or 00 [Hz] 8

9 . R SPECFCATN UTPUT SPECFCATN.... Complementary 2. Pch-penDrain UTPUT TYPE.... DC utput 2. Buzzer nverted utput (R Control). Buzzer nverted utput (R Control) 2. / PRT SPECFCATN P Complementary P0.... Complementary P Complementary P0.... Complementary P.... Complementary P.... Complementary P2.... Complementary P.... Complementary 2. Pch-penDrain 2. Pch-penDrain 2. Pch-penDrain 2. Pch-penDrain 2. Pch-penDrain 2. Pch-penDrain 2. Pch-penDrain 2. Pch-penDrain. SN PULL DWN RESSTR 4. SUT SPECFCATN. With Resistor. Complementary 2. Gate Direct 2. Pch-penDrain 5. SCLK SPECFCATN PULL DWN RESSTR.... With Resistor UTPUT SPECFCATN.... Complementary LGC.... Positive 2. Gate Direct 2. Pch-penDrain 2. Negative 6. S DATA PERMUTATN. MSB First 2. LSB First 7. EENT CUNTER NSE REJECTR. 48 or 2400 [Hz] 2. 6 or 00 [Hz] 8. LCD SPECFCATN BAS SELECTN SC60N / Bias, Regulator Used, LCD 2. / Bias, Regulator Not Used, LCD. /2 Bias, Regulator Not Used, LCD 4. / Bias, Regulator Not Used, LCD 4.5 SC60L08 (Note).... / Bias, Regulator Used, LCD 2. /2 Bias, Regulator Not Used, LCD. / Bias, Regulator Not Used, LCD 4.5 SC60A / Bias, Regulator Used, LCD 2. / Bias, Regulator Not Used, LCD. /2 Bias, Regulator Not Used, LCD 4. / Bias, Regulator Not Used, LCD 4.5 DUTY SELECTN.... /4 Duty 2. / Duty. /2 Duty 9. SEGMENT MEMRY ADDRESS. 0 Page (04006F) 2. 2 Page (24026F) Note The SC60R08 does not support the SC60L08. 9

10 SC60R08 RM EMULATR/RM EMULATR PRGRAMMER The SC60R08 has a built-in RM emulator, which is constructed by RAM, to emulate mask RM. The RM emulator is programmed from outside through the serial interface (programmer) circuit and then its data is read by the CPU. This chapter explain the RM emulator and the Programmer circuit. Configuration of RM Emulator The built-in RM emulator is the same structure with the mask RM built-in SC60N08. And used for loading the user-program. That has a capacity of 4,096 steps 2 bits. The program area consists of 6 (05) pages 6 (00HFFH) steps. After initial reset, the program beginning address is set to bank 0, page, step 00H. The interrupt vector is allocated to page, steps 0H0FH. Bank 0 Page 0 Page Page 2 Page Step 00H Step 0H Step 0FH Step H Program start address nterrupt vector area Page 5 Step FFH 2 bits The RM emulator data is downloaded from an external Serial EEPRM through the Programmer circuit. After power on or a HGH pulse is input to the TPRST pin, the RM emulator data is initialized and downloading will be started. Configuration of RM Emulator Programmer The RM emulator data is written through the Programmer. The Programmer supports data transmit/receive communication with Serial EEPRM, interface data error check and system reset signal generation. SC RESET SC60R08 DD Configuration flag System reset CPU and peripheral circuit A2 A A0 Serial EEPRM TPRST SDA SCL EEPRM nterface Circuit RM Emulator 4,096 2 bits CPU ERRUT Error Detect Circuit SS Terminals The Programmer uses the following input/output terminals. SCL Serial EEPRM control clock output terminal SDA Serial EEPRM data transmit/receive terminal ERRUT Data check result output terminal TPRST Data re-loading start input terminal

11 peration The SC60R08 has two operation modes, Programming mode Load the data from the Serial EEPRM Normal mode Work as if the mask RM type The following describes how to operate the SC60R08. ) Make an application software. 2) Convert the software to the Serial EEPRM format with winedg in the SC60R08 package. ) Write the program which is converted to the Serial EEPRM format to the Serial EEPRM. 4) Set up the SC60R08, the Serial EEPRM and the other peripheral components on the user target application. (The example is described in "BASC EXTERNAL CNNECTN DAGRAM".) 5) The application power on. 6) The SC60R08 enters to the Programming mode, and starts data loading from the Serial EEPRM to the built-in RM emulator automatically. n the loading, internal circuit is kept as system reset condition except the Programmer. And data error checking is done at the same time. 7) f the data error happens, the ERRUT pin goes HGH level and data loading is terminated. 8) f the data has loaded without any error, the SC60R08 enters to the Normal mode automatically. Then the CPU read the RM emulator data as the instruction and start to run as if the mask RM type. 9) f you want to re-load the data, input a HGH pulse to the TPRST pin. Then the SC60R08 enters to Programming mode and starts re-loading. SUMMARY F NTES Target Type for SC60N08 Series The SC60N08 has types (SC60N08, SC60A08 and SC60L08). n these models, the SC60R08 supports the following 2 types as the RM emulator model. SC60N08 DD =.0 (Typ.), SC SC60A08 DD =.0 (Typ.), SC/SC Refer the "SC60N08/60R08 Technical Manual". Mask/Segment ption The SC60R08 can load RM emulator data. But cannot load the mask option and segment option. Therefore customer must make the function option data and segment option data by the SC60R08 development tool at first. Then send the data to SEK EPSN and order the mask. SEK EPSN makes the SC60R08 with a customized option according to this request. Serial EEPRM The external Serial EEPRM is necessary for programming the RM emulator data, and this component is recommended. Recommended component AK60A/2A (AKM) M24C64/2 (SGS-THMSN) BR24C64 (RHM) 24AA64 (Microchip) Note Use larger EEPRM than program memory size.

12 ELECTRCAL CHARACTERSTCS Absolute Maximum Ratings SC60N08/60A08/60R08 (DD=0) Rating Supply voltage nput voltage () nput voltage (2) Permissible total output current perating temperature Storage temperature Soldering temperature / time Permissible dissipation 2 SS SC ΣSS Topr Tstg Tsol PD alue -5.0 to 0.5 SS-0. to 0.5 S-0. to to to 260 C, sec (lead section) 2 Unit ma C C mw The permissible total output current is the sum total of the current (average current) that simultaneously flows from the output pins (or is draw in). 2 n case of plastic package. SC60L08 (DD=0) Rating Supply voltage nput voltage () nput voltage (2) Permissible total output current perating temperature Storage temperature Soldering temperature / time Permissible dissipation 2 SS SC ΣSS Topr Tstg Tsol PD alue -2.0 to 0.5 SS-0. to 0.5 S-0. to to to 260 C, sec (lead section) 2 Unit ma C C mw The permissible total output current is the sum total of the current (average current) that simultaneously flows from the output pins (or is draw in). 2 n case of plastic package. Recommended perating s SC60N08 Supply voltage scillation frequency SS fsc DD=0 Either one is selected Remark Min. -.5 (Ta=- to 70 C) Typ. Max. Unit khz khz SC60L08 Supply voltage scillation frequency SS fsc Remark DD=0 DD=0, with software control DD=0, when analog comparator is used Either one is selected When switching to heavy load protection mode. 2 The possibility of LCD panel display differs depending on the characteristics of the LCD panel. Min (Ta=- to 70 C) Typ. Max. Unit khz khz SC60A08/60R08 Supply voltage scillation frequency () SS fsc DD=0 Either one is selected Remark scillation frequency (2) fsc duty ±5%, SS=-2.2 to when the SC60R08 is used as the SC60N08. Min. -.5 (Ta=- to 70 C) Typ. Max. Unit khz khz khz 2

13 DC Characteristics SC60N08/60A08/60R08 (Unless otherwise specified DD=0, SS=-.0, fsc=2.768khz, Ta= C, S/LL are internal voltage, CC5=0.µF) H K000, K, K2, P000, P SN, (SDA) Min. 0.2 SS Typ. Max. 0 Unit H2 L SCLK, RESET, TEST, (TPRST) K000, K, K2, P000, P SN, (SDA) 0. SS SS SS L2 SCLK, RESET, TEST, (TPRST) SS 0.9 SS H H=0 K000, K, K2, P000, P Characteristic High level input voltage () High level input voltage (2) Low level input voltage () Low level input voltage (2) High level input current () High level input current (2) High level input current () Low level input current High level output current () High level output current (2) Low level output current () Low level output current (2) H2 H L H H2 L L2 Common output current H L Segment output current H4 (during LCD output) L4 Segment output current H5 (during DC output) L5 ( ) indicate the SC60R08 pins. High level output current () High level output current (2) Low level output current () Low level output current (2) Common output current Segment output current (during LCD output) Segment output current (during DC output) H H2 L L2 H L H4 L4 H5 L5 No pull-down SN, SCLK, AMPP, AMPM (SDA) H2=0 K000, K, K2 With pull-down SN, SCLK H=0 P000, P, RESET, TEST With pull-down (TPRST) L=SS K000, K, K2, P000, P SN, SCLK, AMPP, AMPM, RESET, TEST (TPRST), (SDA) H=0. SS R, R, R H2=0. SS R000, R2, P000, P, SUT SCLK, (SDA), (ERRUT), (SCL) L=0.9 SS R, R, R L2=0.9 SS R000, R2, P000, P, SUT SCLK, (SDA), (ERRUT), (SCL) H=-0.05 CM0 L=L+0.05 H4=-0.05 SEG047 L4=L+0.05 H5=0. SS SEG047 L5=0.9 SS SC60L08 (Unless otherwise specified DD=0, SS=-.5, fsc=2.768khz, Ta= C, S/LL are internal voltage, CC5=0.µF) Characteristic High level input voltage () H K000, K, K2, P000, P SN Min. 0.2 SS Typ. Max. 0 Unit High level input voltage (2) Low level input voltage () H2 L SCLK, RESET, TEST K000, K, K2, P000, P SN 0. SS SS SS Low level input voltage (2) L2 SCLK, RESET, TEST SS 0.9 SS High level input current () H H=0 No pull-down K000, K, K2, P000, P SN, SCLK AMPP, AMPM High level input current (2) H2 H2=0 With pull-down K000, K, K2 SN, SCLK 2 High level input current () H H=0 With pull-down P000, P RESET, TEST 2 60 Low level input current L L=SS K000, K, K2, P000, P SN, SCLK, AMPP, AMPM RESET, TEST H=0. SS R, R, R H2=0. SS R000, R2, P000, P SUT, SCLK L=0.9 SS R, R, R L2=0.9 SS R000, R2, P000, P SUT, SCLK H=-0.05 CM0 L=L+0.05 H4=-0.05 SEG047 L4=L+0.05 H5=0. SS SEG047 L5=0.9 SS ma ma ma ma

14 Analog Circuit Characteristics and Current Consumption SC60N08 (Normal perating Mode) (Unless otherwise specified DD=0, SS=-.0, fsc=2.768khz, Ta= C, CG=pF, S/LL are internal voltage, CC5=0.µF) Characteristic LCD drive voltage L Min. Typ. Max. Unit BLD voltage BLD circuit response time Sub-BLD voltage Sub-BLD circuit response time input voltage offset voltage response time Current consumption L2 L B0 B B2 B B4 B5 B6 B7 tb BS tbs P M F tamp P Connect MΩ load resistor between DD and L Connect MΩ load resistor between DD and L2 Connect MΩ load resistor between DD and L BLC="0" BLC="" BLC="2" BLC="" BLC="4" BLC="5" BLC="6" BLC="7" Non-inverted input (AMPP) nverted input (AMPM) P=-.5 M=P±5m During HALT During operation 2 The relationships among B0B7 are B0>B>B2>...B5>B6>B7. 2 The BLD circuit, sub-bld circuit and analog comparator are in the FF status. SC60N08 (Heavy Load Protection Mode) Without panel load /2 L2-2.0 /2 L SS /2 L /2 L µsec µsec DD-0.9 (Unless otherwise specified DD=0, SS=-.0, fsc=2.768khz, Ta= C, CG=pF, S/LL are internal voltage, CC5=0.µF) Characteristic LCD drive voltage L Min. Typ. Max. Unit BLD voltage BLD circuit response time Sub-BLD voltage Sub-BLD circuit response time input voltage offset voltage response time Current consumption L2 L B0 B B2 B B4 B5 B6 B7 tb BS tbs P M F tamp P Connect MΩ load resistor between DD and L Connect MΩ load resistor between DD and L2 Connect MΩ load resistor between DD and L BLC="0" BLC="" BLC="2" BLC="" BLC="4" BLC="5" BLC="6" BLC="7" Non-inverted input (AMPP) nverted input (AMPM) P=-.5 M=P±5m During HALT During operation 2 The relationships among B0B7 are B0>B>B2>...B5>B6>B7. 2 The BLD circuit and sub-bld circuit are in the N status (HLMD="", BLS="0"). The analog comparator is in the FF status. Without panel load /2 L2-2.0 /2 L SS /2 L m msec /2 L µsec µsec DD-0.9 m msec 4

15 SC60L08 (Normal perating Mode) (Unless otherwise specified DD=0, SS=-.5, fsc=2.768khz, Ta= C, CG=pF, S/LL are internal voltage, CC5=0.µF) Characteristic LCD drive voltage L Min. -.5 Typ Max Unit BLD voltage BLD circuit response time Sub-BLD voltage Sub-BLD circuit response time input voltage offset voltage response time Current consumption L2 L B0 B B2 B B4 B5 B6 B7 tb BS tbs P M F tamp P Connect MΩ load resistor between DD and L Connect MΩ load resistor between DD and L2 Connect MΩ load resistor between DD and L BLC="0" BLC="" BLC="2" BLC="" BLC="4" BLC="5" BLC="6" BLC="7" Non-inverted input (AMPP) nverted input (AMPM) P=-. M=P±0m During HALT During operation 2 The relationships among B0B7 are B0>B>B2>...B5>B6>B7. 2 The BLD circuit, sub-bld circuit and analog comparator are in the FF status. SC60L08 (Heavy Load Protection Mode) Without panel load 2 L L SS L L µsec -. 0 µsec DD-0.9 (Unless otherwise specified DD=0, SS=-.5, fsc=2.768khz, Ta= C, CG=pF, S/LL are internal voltage, CC5=0.µF) Characteristic LCD drive voltage L Min. -.5 Typ Max Unit BLD voltage BLD circuit response time Sub-BLD voltage Sub-BLD circuit response time input voltage offset voltage response time Current consumption L2 L B0 B B2 B B4 B5 B6 B7 tb BS tbs P M F tamp P Connect MΩ load resistor between DD and L Connect MΩ load resistor between DD and L2 Connect MΩ load resistor between DD and L BLC="0" BLC="" BLC="2" BLC="" BLC="4" BLC="5" BLC="6" BLC="7" Non-inverted input (AMPP) nverted input (AMPM) P=-. M=P±0m During HALT During operation 2 The relationships among B0B7 are B0>B>B2>...B5>B6>B7. 2 The BLD circuit and sub-bld circuit are in the N status (HLMD="", BLS="0"). The analog comparator is in the FF status. Without panel load 2 L L SS m msec 2 L 0.85 L µsec -. 0 µsec DD m msec 5

16 SC60A08 (Normal perating Mode) (Unless otherwise specified DD=0, SS=-.0, fsc=2.768khz, Ta= C, CG=pF, S/LL are internal voltage, CC5=0.µF) Characteristic LCD drive voltage L Min. -.5 Typ Max Unit BLD voltage BLD circuit response time Sub-BLD voltage Sub-BLD circuit response time input voltage offset voltage response time Current consumption L2 L B0 B B2 B B4 B5 B6 B7 tb BS tbs P M F tamp P Connect MΩ load resistor between DD and L Connect MΩ load resistor between DD and L2 Connect MΩ load resistor between DD and L BLC="0" BLC="" BLC="2" BLC="" BLC="4" BLC="5" BLC="6" BLC="7" Non-inverted input (AMPP) nverted input (AMPM) P=-.5 M=P±5m During HALT During operation 2 During operation at 0kHz 2 The relationships among B0B7 are B0>B>B2>...B5>B6>B7. 2 The BLD circuit, sub-bld circuit and analog comparator are in the FF status. Without panel load 2 L L SS L L µsec µsec DD-0.9 SC60A08 (Heavy Load Protection Mode) (Unless otherwise specified DD=0, SS=-.0, fsc=2.768khz, Ta= C, CG=pF, S/LL are internal voltage, CC5=0.µF) Characteristic LCD drive voltage L Min. -.5 Typ Max Unit BLD voltage BLD circuit response time Sub-BLD voltage Sub-BLD circuit response time input voltage offset voltage response time Current consumption L2 L B0 B B2 B B4 B5 B6 B7 tb BS tbs P M F tamp P Connect MΩ load resistor between DD and L Connect MΩ load resistor between DD and L2 Connect MΩ load resistor between DD and L BLC="0" BLC="" BLC="2" BLC="" BLC="4" BLC="5" BLC="6" BLC="7" Non-inverted input (AMPP) nverted input (AMPM) P=-.5 M=P±5m During HALT During operation 2 During operation at 0kHz 2 The relationships among B0B7 are B0>B>B2>...B5>B6>B7. 2 The BLD circuit and sub-bld circuit are in the N status (HLMD="", BLS="0"). The analog comparator is in the FF status. Without panel load 2 L L SS m msec 2 L L µsec µsec DD m msec 6

17 SC60R08 (Normal perating Mode) Target SC60N08 (Unless otherwise specified DD=0, SS=-.0, fsc=2.768khz, Ta= C, CG=pF, S/LL are internal voltage, CC5=0.µF) Characteristic LCD drive voltage L Min. Typ. Max. Unit BLD voltage BLD circuit response time Sub-BLD voltage Sub-BLD circuit response time input voltage offset voltage response time Current consumption L2 L B0 B B2 B B4 B5 B6 B7 tb BS tbs P M F tamp P Connect MΩ load resistor between DD and L Connect MΩ load resistor between DD and L2 Connect MΩ load resistor between DD and L BLC="0" BLC="" BLC="2" BLC="" BLC="4" BLC="5" BLC="6" BLC="7" Non-inverted input (AMPP) nverted input (AMPM) P=-.5 M=P±5m During HALT During operation 2 The relationships among B0B7 are B0>B>B2>...B5>B6>B7. 2 The BLD circuit, sub-bld circuit and analog comparator are in the FF status. Without panel load /2 L2-2.0 /2 L SS /2 L /2 L µsec µsec DD m msec SC60R08 (Heavy Load Protection Mode) Target SC60N08 (Unless otherwise specified DD=0, SS=-.0, fsc=2.768khz, Ta= C, CG=pF, S/LL are internal voltage, CC5=0.µF) Characteristic LCD drive voltage L Min. Typ. Max. Unit BLD voltage BLD circuit response time Sub-BLD voltage Sub-BLD circuit response time input voltage offset voltage response time Current consumption L2 L B0 B B2 B B4 B5 B6 B7 tb BS tbs P M F tamp P Connect MΩ load resistor between DD and L Connect MΩ load resistor between DD and L2 Connect MΩ load resistor between DD and L BLC="0" BLC="" BLC="2" BLC="" BLC="4" BLC="5" BLC="6" BLC="7" Non-inverted input (AMPP) nverted input (AMPM) P=-.5 M=P±5m During HALT During operation 2 The relationships among B0B7 are B0>B>B2>...B5>B6>B7. 2 The BLD circuit and sub-bld circuit are in the N status (HLMD="", BLS="0"). The analog comparator is in the FF status. Without panel load /2 L2-2.0 /2 L SS /2 L /2 L µsec µsec DD-0.9 m msec 7

18 SC60R08 (Normal perating Mode) Target SC60A08 (Unless otherwise specified DD=0, SS=-.0, fsc=2.768khz, Ta= C, CG=pF, S/LL are internal voltage, CC5=0.µF) Characteristic LCD drive voltage L Min. -.5 Typ Max Unit BLD voltage BLD circuit response time Sub-BLD voltage Sub-BLD circuit response time input voltage offset voltage response time Current consumption L2 L B0 B B2 B B4 B5 B6 B7 tb BS tbs P M F tamp P Connect MΩ load resistor between DD and L Connect MΩ load resistor between DD and L2 Connect MΩ load resistor between DD and L BLC="0" BLC="" BLC="2" BLC="" BLC="4" BLC="5" BLC="6" BLC="7" Non-inverted input (AMPP) nverted input (AMPM) P=-.5 M=P±5m During HALT During operation 2 During operation at 0kHz 2 The relationships among B0B7 are B0>B>B2>...B5>B6>B7. 2 The BLD circuit, sub-bld circuit and analog comparator are in the FF status. Without panel load 2 L L SS L L µsec µsec DD m msec SC60R08 (Heavy Load Protection Mode) Target SC60A08 (Unless otherwise specified DD=0, SS=-.0, fsc=2.768khz, Ta= C, CG=pF, S/LL are internal voltage, CC5=0.µF) Characteristic LCD drive voltage L Min. -.5 Typ Max Unit BLD voltage BLD circuit response time Sub-BLD voltage Sub-BLD circuit response time input voltage offset voltage response time Current consumption L2 L B0 B B2 B B4 B5 B6 B7 tb BS tbs P M F tamp P Connect MΩ load resistor between DD and L Connect MΩ load resistor between DD and L2 Connect MΩ load resistor between DD and L BLC="0" BLC="" BLC="2" BLC="" BLC="4" BLC="5" BLC="6" BLC="7" Non-inverted input (AMPP) nverted input (AMPM) P=-.5 M=P±5m During HALT During operation 2 During operation at 0kHz 2 The relationships among B0B7 are B0>B>B2>...B5>B6>B7. 2 The BLD circuit and sub-bld circuit are in the N status (HLMD="", BLS="0"). The analog comparator is in the FF status. Without panel load 2 L L SS L L µsec µsec DD m msec 8

19 scillation Characteristics scillation characteristics will vary according to different conditions (elements used, boad pattern). Use the following characteristics are as reference values. SC60N08/60R08 (SC Crystal scillation) (Unless otherwise specified DD=0, SS=-.0, Crystal QMC46, CG=pF, CD=built-in, Ta= C) Characteristic Min. Typ. Max. Unit scillation start voltage scillation stop voltage sta stp tsta 5sec (SS) tstp sec (SS) Built-in capacitance (drain) CD ncluding the parasitic capacitance inside the chip pf Frequency/voltage deviation f/ SS=-.8 to ppm Frequency/C deviation f/ C - ppm Frequency adjustment range f/ CG CG=5 to pf 5 45 ppm Harmonic oscillation start voltage hho (SS) -.5 Permitted leak resistance Rleak Between SC and DD 0 MΩ SC60L08 (SC Crystal scillation) (Unless otherwise specified DD=0, SS=-.5, Crystal QMC46, CG=pF, CD=built-in, Ta= C) Characteristic Min. Typ. Max. Unit scillation start voltage scillation stop voltage sta stp tsta 5sec (SS) tstp sec (SS) (-0.9) Built-in capacitance (drain) CD Frequency/voltage deviation f/ Frequency/C deviation f/ C Frequency adjustment range f/ CG Harmonic oscillation start voltage hho Permitted leak resistance Rleak ncluding the parasitic capacitance inside the chip SS=-. (-0.9) to -.7 CG=5 to pf (SS) Between SC and DD Parentheses indicate value for operation in heavy load protection mode pf ppm ppm ppm MΩ SC60A08 (SC Crystal scillation) Characteristic scillation start voltage scillation stop voltage Built-in capacitance (drain) Frequency/voltage deviation Frequency/C deviation Frequency adjustment range Harmonic oscillation start voltage Permitted leak resistance (Unless otherwise specified DD=0, SS=-.0, Crystal QMC46, CG=pF, CD=built-in, Ta= C) sta stp Min Typ. Max. CD f/ f/ C f/ CG hho Rleak tsta 5sec (SS) tstp sec (SS) ncluding the parasitic capacitance inside the chip SS=-2.2 to -.5 CG=5 to pf (SS) Between SC and DD Unit pf ppm ppm ppm MΩ SC60A08/60R08 (SC CR scillation) Characteristic scillation frequency dispersion scillation start voltage scillation start time scillation stop voltage fsc sta tsta stp (SS) SS=-2.2 to -.5 (SS) (Unless otherwise specified DD=0, SS=-.0, RCR=82kΩ, Ta= C) Min Typ. 480kHz Max. 0 Unit % msec SC60A08/60R08 (SC Ceramic scillation) (Unless otherwise specified DD=0, SS=-.0, Ceramic oscillator 0kHz, CGC=CDC=0pF, Ta= C) Characteristic Min. Typ. Max. Unit scillation start voltage sta (SS) -2.2 scillation start time tsta SS=-2.2 to msec scillation stop voltage stp (SS)

20 BASC EXTERNAL CNNECTN DAGRAM SC60N08 and SC60L08 LCD panel K00 K0 K K K2 SEG0 SEG47 CM0 CM CB CA L L2 L C s (C2C4) are connected. Connection depending on power supply and LCD panel specification. S / P00 P0 P P SN SUT SCLK AMPM AMPP SC60N08 SC60L08 [The potential of the substrate (back of the chip) is DD.] DD SC SC2 S SC SC4 RESET CGX X'tal C5 N.C. N.C..0 (SC60N08) or.5 (SC60L08) R00 R0 R2 (FUT) R (LAMP) R (BZ) R (BZ) TEST SS + CP Lamp Piezo X'tal CGX C C2 C C4 C5 CP RA RA2 Crystal oscillator Trimmer capacitor Protection resistor Protection resistor khz or khz, C = 5 kω 5 pf. µf 0 Ω 0 Ω R (BZ) R (BZ) RA RA2 Piezo When the piezoelectric buzzer is driven directly Note The above tables are simply an example, and are not guaranteed to work.

21 SC60A08 LCD panel K00 K0 K K K2 SEG0 SEG47 CM0 CM CB CA L L2 L C s (C2C4) are connected. Connection depending on power supply and LCD panel specification. S / P00 P0 P P SN SUT SCLK AMPM AMPP SC60A08 [The potential of the substrate (back of the chip) is DD.] DD SC SC2 S SC SC4 RESET CGX X'tal CR C5 CGC CDC RCR 2.0 R00 R0 R2 (FUT) R (LAMP) R (BZ) R (BZ) TEST SS + CP Lamp Piezo Ceramic oscillation 2 CR oscillation X'tal CGX CR CGC CDC RCR C C2 C C4 C5 CP RA RA2 Crystal oscillator Trimmer capacitor Ceramic oscillator Gate capacitor Drain capacitor Resistor for CR oscillation Protection resistor Protection resistor khz or khz, C = 5 kω 5 pf 0 khz 0 pf 0 pf 82 kω. µf 0 Ω 0 Ω RA R (BZ) R (BZ) Piezo RA2 When the piezoelectric buzzer is driven directly Note The above tables are simply an example, and are not guaranteed to work. 2

22 SC60R08 (Target for SC60N08) LCD panel K00 K0 K K K2 SEG0 SEG47 CM0 CM CB CA L L2 L C s (C2C4) are connected. Connection depending on power supply and LCD panel specification. S / P00 P0 P P SN SUT SCLK TPRST AMPM AMPP SC60R08 [The potential of the substrate (back of the chip) is DD.] DD SC SC2 S SC SC4 RESET N.C. N.C. CGX X'tal C5.0 SCL SDA ERRUT R2 (FUT) R (LAMP) R (BZ) R (BZ) TEST SS + CP A0 CC Lamp Piezo A A2 C NC SCL SS SDA X'tal CGX C C2 C C4 C5 CP RA RA2 C Crystal oscillator Trimmer capacitor Protection resistor Protection resistor Serial EEPRM khz or khz 5 pf. µf 0 Ω 0 Ω See "Serial EEPRM" RA R (BZ) R (BZ) RA2 Piezo When the piezoelectric buzzer is driven directly Note The above tables are simply an example, and are not guaranteed to work. 22

23 SC60R08 (Target for SC60A08) LCD panel K00 K0 K K K2 SEG0 SEG47 CM0 CM CB CA L L2 L C s (C2C4) are connected. Connection depending on power supply and LCD panel specification. S / P00 P0 P P SN SUT SCLK TPRST AMPM AMPP SC60R08 [The potential of the substrate (back of the chip) is DD.] DD SC SC2 S SC SC4 RESET CGX X'tal C5 CGC CR CDC RCR 2.0 SCL SDA ERRUT R2 (FUT) R (LAMP) R (BZ) R (BZ) TEST SS + CP A0 CC Lamp Piezo Ceramic oscillation 2 CR oscillation A A2 C NC SCL SS SDA X'tal CGX CR CGC CDC RCR C C2 C C4 C5 CP RA RA2 C Crystal oscillator Trimmer capacitor Ceramic oscillator Gate capacitor Drain capacitor Resistor for CR oscillation Protection resistor Protection resistor Serial EEPRM khz or khz 5 pf 0 khz 0 pf 0 pf 82 kω. µf 0 Ω 0 Ω See "Serial EEPRM" RA R (BZ) R (BZ) RA2 Piezo When the piezoelectric buzzer is driven directly Note The above tables are simply an example, and are not guaranteed to work. 2

24 PACKAGE Plastic QFP5-0pin.6 ±0.4 ± NDEX 4 ± ± ±0. 0.4max 2.7 ± ± Plastic QFP5-0pin 6 ±0.4 4 ± ±0. 6 ±0.4 NDEX max.4 ± ± Unit mm 24

25 SC60N08/60R08 PAD LAYUT SC60N08/60L08/60A08 Diagram of Pad Layout X (0, 0) Die No. Y.7 mm.74 mm Chip thickness 400 µm Pad opening 95 µm SC60N08/60L08/60A08 Pad Coordinates No Pad name AMPP AMPM K2 K22 K2 K K K0 K02 K0 K00 SN SUT SCLK P0 P02 P0 P00 P P2 P P R0 R02 R0 R00 R2 R R R SS RESET X,294,64, ,048 -,78 -,08 -, Y,686,556,426,296,66, No Pad name SC4 * SC * S SC2 SC DD L L2 L CA CB CM CM2 CM CM0 SEG47 SEG46 SEG45 SEG44 SEG4 SEG42 SEG4 SEG40 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG SEG2 SEG X ,45 -,285 -,55 -, Y ,022 -,5 -,28 -,4 -,54 -,67 No Pad name SEG0 SEG29 SEG28 SEG27 SEG26 SEG SEG24 TEST SEG2 SEG22 SEG2 SEG SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG SEG2 SEG SEG SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG SEG2 SEG SEG0 X 795 9,055,85,5,445 Y -,62 -,465 -, -,80 -, ,00,60,290,4,5,680 Unit µm SC60A08 only

26 26 SC60N08/60R08 SC60R08 Diagram of Pad Layout Y X (0, 0) 7.00 mm 8.5 mm 5 5 Die No Chip thickness 400 µm Pad opening 95 µm SC60R08 Pad Coordinates No Pad name AMPP AMPM K2 K22 K2 K K K0 K02 K0 K00 SN SUT TPRST SCLK P0 P02 P0 P00 SCL SDA P P2 P P R0 R02 R0 R00 R2 R R R SS X 2,89 2,68 2,82 2,27,87,66,60, ,064 -,275 -,566 -,82-2,26-2,405-2,685-2,978 -, Y,090 2,787 2,657 2,527 2,288 2,064,599,470 No Pad name REST SC4 SC S SC2 SC DD L L2 L CA CB ERRUT CM CM2 CM CM0 SEG47 SEG46 SEG45 SEG44 SEG4 SEG42 SEG4 SEG40 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG SEG2 SEG X ,4 -,6-2,8-2,7-2, -,899 -,595 -, ,42,446 Y, ,74 -,9 -,607 -,824-2,040-2,24-2,429-2,645-2,862 -, No Pad name SEG0 SEG29 SEG28 SEG27 SEG26 SEG SEG24 TEST SEG2 SEG22 SEG2 SEG SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG SEG2 SEG SEG SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG SEG2 SEG SEG0 X,75 2,055 2,59 2,66 2,967,272,66 Y ,049-2,590-2,55-2,9 -,88 -,647 -,4 -, ,84,4,656,892 2,28 2,64 2,600 2,86 Unit µm

27 THS PAGE S BLANK. 27

28 NTCE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of nternational Trade and ndustry or other approval from another government agency. Seiko Epson Corporation 0 All right reserved. SEK EPSN CRPRATN ELECTRNC DECES MARKETNG DSN C Marketing & Engineering Group ED nternational Marketing Department Europe & U.S.A. 42-8, Hino, Hino-shi, Tokyo 9-8, JAPAN Phone FAX ED nternational Marketing Department Asia 42-8, Hino, Hino-shi, Tokyo 9-8, JAPAN Phone FAX EPSN Electronic Devices Website http// ssue August, 0 Printed in Japan L