A4955. Full-Bridge PWM Gate Driver PACKAGES:

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1 FEATURES AND BENEFITS Standard IN/IN control logic Overcurrent indication Adjustable off-time and blank-time Adjustable current limit Adjustable gate drive Synchronous rectification Internal UVLO rossover-current protection MOSFET VDS protection Voltage output proportional to load current A4955K is AE-Q00 Grade qualified ommercial temperature grade (A4955G: 40 to 05 ) Automotive temperature grade (A4955K: 40 to 5 ) PAKAGES: 0-Pin QFN (suffix ES ) with Exposed Thermal Pad 0-Pin etssop (suffix LP ) with Exposed Thermal Pad DESRIPTION Designed for pulse-width-modulated (PWM) control of D motors, the A4955 is capable of 50 V operation and provides gate drive for an all N-channel external MOSFET bridge. Input terminals are provided for use in controlling the speed and direction of a D motor with externally applied PWM control signals. Internal synchronous rectification control circuitry is provided to lower power dissipation during PWM operation. Internal circuit protection includes VDS protection, thermal shutdown with hysteresis, undervoltage monitoring of, and crossover-current protection. The A4955 is supplied in a low-profile 4 4 mm, 0-contact QFN package (suffix ES ) and a 0-lead etssop (suffix LP ), both with exposed thermal pad. Not to scale 0. µf P P TSD UVLO HARGE PUMP VREG VP 0. µf VIN R VP SLEEPn IN STANDBY ontrol Logic GATE DRIVE GHA GHB SB GHA IN SA SA System ontroller optional OLn OL Filter GLA GLB GLA HOLD 0 + R Inrush current limit = V /0 * R REF VREF 0 Functional Block Diagram A4955-DS, Rev. MO November 30, 07

2 SPEIFIATIONS SELETION GUIDE Part Number Ambient Temperature Range Packing Notes A4955GESTR-T 40 to pieces per 7-inch reel A4955GLPTR-T 40 to pieces per 3-inch reel A4955KLPTR-T 40 to pieces per 3-inch reel AE-Q00 Qualified ABSOLUTE MAXIMUM RATINGS haracteristic Symbol Notes Rating Unit Load Supply Voltage V BB 50 V Motor Outputs V Sx V Sx V ; V BB V Sx to 5 V V 0.5 to 0.5 V t W < 500 ns 4 to 4 V OLn V OLn 0.3 to 5.5 V VREF V REF 0.3 to 5.5 V V 0.3 to 5.5 V V 0.3 to 5.5 V Logic Input Voltage Range V IN SLEEPn, IN, IN 0.3 to 5.5 V Junction Temperature T J 50 Storage Temperature Range T S 55 to 50 Operating Temperature Range T A Range G 40 to 05 Range K 40 to 5 4-Layer PB, in. copper THERMAL HARATERISTIS (may require derating at maximum conditions; see application information) haracteristic Symbol Test onditions* Value Unit ES Package 37 /W R θja LP Package 4-Layer PB, in. copper 8 /W *Power dissipation and thermal limits must be observed.

3 R IN IN VREF OLn 0 P SLEEPn GLB GLA PAD P P OLn VREF IN IN R PAD P VP SA GHA SB GHB GHB SB GHA SA VP SLEEPn 9 GLA 0 GLB Package ES, 0-Pin QFN Pinouts Package LP, 0-Pin etssop Pinouts Terminal List Table Number Name ES Package LP Package Function 8 Terminal to set gate drive current SLEEPn 9 Sleep input, active low 3 0 Sense resistor connection, low-side gate return GLB 4 Gate driver GLA 5 Gate driver GHB 6 3 Gate driver SB 7 4 High-side bridge reference GHA 8 5 Gate driver SA 9 6 High-side bridge reference VP 0 7 harge pump reservoir cap connection P 8 harge pump terminal 9 Supply voltage P 3 0 harge pump terminal 4 Ground 5 Analog output proportional to V OLn 6 3 OP and OVP output flag, open drain VREF 7 4 Analog OP reference input IN 8 5 Digital IN input IN 9 6 Digital IN input R 0 7 Terminal to set blank- and off-time PAD 3

4 ELETRIAL HARATERISTIS: Valid for Temperature Range G version at T J = 5 and for Temperature Range K version at T J = 40 to 50, V BB = 5.5 to 50 V, unless otherwise specified haracteristics Symbol Test onditions Min. Typ. Max. Unit Supply urrent GATE DRIVE I BB 6 0 ma I BB SLEEPn = low, Standby Mode 5 µa Relative to V BB, I GATE = 00 µa, V BB = 8 to 50 V V High-Side Gate Drive Output V GH Relative to V BB, I GATE = 00 µa, V BB = 5.5 V 5. V I GATE = 00 µa, V BB = 8 to 50 V V Low-Side Gate Drive Output V GL I GATE = 00 µa, V BB = 5.5 V 5.4 V Gate Drive Pull-Up urrent I GPU R = 30 kω; V GH = V GL = 4 V ma Gate Drive Pull-Down urrent I GPD R = 30 kω; V GH = V GL = 4 V ma Dead-Time t DT 000 ns Passive Pull-Down Resistance R GPD kω LOGI INPUT AND OUTPUT Logic Output Voltage V OLn I = ma, overcurrent detected V Logic Output Leakage I OLn V = 5 V, normal operation 5 µa PWM urrent Limit Flag Timer t OLn µs V IH.0 V Logic Input Voltage V IL 0.8 V V IL(SLEEPn) SLEEPn input 0.4 V Logic Input Hysteresis V HYS 30 mv Logic Input Pull-Down Resistor R PD kω VREF Input urrent I VREF V REF =.5 V 5 < 5 µa VREF Input Range V REF 0.5 V urrent Gain A V V REF / V, V REF =.5 V V/V Input Offset, V OS 0 0 mv Fixed Off-Time t OFF R R = 30 kω, R = nf 30 µs Percent Fast Decay P FD Internal PWM chop 3 % Blank-Time t BLK R R = 30 kω, R = nf µs Power-Up Delay t pu Time until outputs are enabled µs Gain A IOUT /V, V = 50 to 00 mv 9 0 V/V Input Offset, V OS 5 5 mv Sample-and-Hold Accuracy V SH(A) 5 mv Sample-and-Hold Droop Rate V DROOP mv/µs Output Impedance R OUT() kω PROTETION IRUITS UVLO Enable Threshold V BB(UVLO) V BB rising V UVLO Hysteresis V BB(UVLO,HYS) mv VDS Threshold V DSTH V Thermal Shutdown Temperature T JTSD Temperature increasing Thermal Shutdown Hysteresis ΔT J Recovery = T JTSD ΔT J 30 [] Specified limits are tested at a single temperature and assured over operating temperature range by design and characterization. [] Target trip level = V DSTH = V DRAIN V Sx (High Side On) or V DSTH = V Sx V (Low Side On). 4

5 ontrol Logic IN IN SLEEPn 0 V > V REF OUTA OUTB Function x x 0 x Z Z Sleep (Standby) Mode 0 0 x Z Z oast 0 false L H Reverse 0 false H L Forward x L L Slow Decay SR (Brake) 0 true H/L L Internal hop Reverse, Mixed Decay * 0 true L H/L Internal hop Forward, Mixed Decay * * In fast decay, outputs change to high-z state when load current approaches zero, to prevent reversal of current. I OL = V REF / R / 0 I_OUT t OLn OLn OLn Output Flag OLn output function is described in the Functional Description section. A A B B 300 µs 0 V V = V REF /0 V 0 V IN (IN = High) Output A. Internal OL chop. holds while voltage varies during the mixed-decay off-time. B. INx chop. holds while voltage drops to 0 V during slow decay.. Slow-decay timeout. is forced to 0 V 300 µs after ENABLE goes low. 5

6 FUNTIONAL DESRIPTION Device Operation The A4955 is designed to operate D motors. The output drivers are capable of 50 V with gate-driver capability for an all N-channel external MOSFET H-bridge. ontrol logic includes synchronous rectification to reduce power dissipation. urrent limit is regulated by fixed off-time pulse-width-modulated (PWM) control circuitry. Internal PWM urrent ontrol Peak current is regulated by monitoring the voltage on an external sense resistor. I = PEAK V REF (0 R ) When the peak current is exceeded, the source driver turns off for a fixed period t OFF to chop the current. The outputs operate in mixed-decay mode during t OFF. Refer to the Fixed Off-Time Setting section to set t OFF. The internal current-sense circuit is ignored for t BLANK after PWM transitions. The comparator output is blanked to prevent false overcurrent detection due to reverse recovery currents of the clamp diodes, or switching transients related to the capacitance of the load, or both. Refer to the Blank-Time Setting section to set t BLANK. Brake It is important to note that the internal PWM current-control circuit will not limit the current when braking, since the current does not flow through the sense resistor. The maximum current can be approximated by V BEMF / R MOTOR. are should be taken to ensure that the maximum ratings of the external MOSFET are not exceeded in worst-case braking situations of high speed and high inertial loads. A resistor from terminal to ground sets the magnitude of the gate current. The sink and source current ratios are fixed at approximately -to- where the pull-down current is approximately two times the pull-up current. R should be between 5 and 50 kω. The formula for determining the gate drive is: 900 I GATE_HS (ma) =.9 + R (kω) R I (ma) = GATE_LS 700 R (kω) The R terminal is used to set both fixed off-time and blank-time for the internal PWM current control. Refer to the following three sections to select R component values. Fixed Off-Time Setting The internal PWM current-control circuitry uses a one-shot to control the time the drivers remain off. The one-shot off-time (t OFF ) is determined by the selection of an external resistor and capacitor connected from the R timing terminal to ground. The off-time, over a range of values of R = 470 to 500 pf and R R = to 00 kω, is approximated by: t OFF = R R R + dead time Blank-Time Setting This circuit blanks the output of the current-sense comparator when the outputs are switched by the internal current-control circuitry or by an external PWM chop command. The comparator blanking time, t BLANK, is determined by the selection of an external resistor and capacitor connected from the R timing terminal to ground, and is approximated by: Slow Decay t BLANK R =.6 µs (nf) e (3.6/R R(kΩ)) In slow-decay mode, the low-side switch stays on and the high-side switch turns off. Due to the synchronous rectification feature, the complementary low-side switch turns on after a deadtime. Fast Decay SR In fast-decay mode, the high-side and low-side switches turn off, and the complementary pair of switches is turned on, effectively reversing the voltage polarity across the motor winding. 6

7 Mixed Decay When the peak current is reached, as set by the sense resistor and voltage on VREF, the PWM current limiter initiates an off-time. The off-time is determined by the resistor and capacitor on the R terminal. In mixed-decay mode, the driver will initiate a fast decay, after a dead-time, for 3% of the programmed off-time. After the fast-decay time expires, the bridge will switch to slow decay for the remaining off-time. When the bridge is operating in fast decay, it will internally prevent current reversal by putting the bridge in a high-z state if the current through the sense resistor falls close to zero. OLn Output An open-drain logic output will be driven low to indicate system operation. The OLn terminal is driven low under two conditions:. When the system is limiting current to value set by V REF and R. Once overcurrent events are no longer detected, the A4955 will release the indication after a time t OLn.. When a VDS fault is detected, the OLn terminal is driven low. It is released when the fault is reset. The OLn terminal, in combination with the terminal, can provide valuable information about how the system is behaving: Overcurrent events can indicate a motor stall condition, in which case the system controller can respond to the fault condition by reducing PWM duty. When OLn is low and the voltage on is greater than 0 V, the controller is actively limiting current with the internal, fixed off-time PWM current limiter. In the case of a VDS fault, the OLn terminal is also driven low, but the voltage will be 0 V, because the bridge has been disabled. This notifies the user that a VDS fault has occurred and the driver has been disabled. An analog output can be used to monitor current through the external sense resistor (if used). The voltage is gained by a factor of 0 and fed to the terminal. A sample-and-hold circuit is used to capture the voltage across the sense resistor and holds it during periods when the voltage is not representative of the current in the motor. The Output diagram illustrates when the voltage is held. The held voltage will droop at a rate equal to V DROOP. In the case of a VDS fault on the bridge, the terminal will be discharged to zero volts. harge Pump The charge pump is used to generate a supply above V BB to drive the high-side MOSFETs. The VP voltage is internally monitored and, in the case of a fault condition, the outputs of the device are disabled. MOSFET VDS Protection The drain-to-source voltage is monitored across the MOSFET any time the MOSFET is on. If the voltage across the MOSFET exceeds V DSTH, the bridge is disabled and latched off. In order to prevent false VDS faults, the VDS monitor is blanked immediately after any MOSFET is turned on. The VDS monitor waits for a blank-time defined by the components on the R terminal before monitoring the VDS level. During the off-time when SR is active, VDS blanking is fixed at μs. VDS Fault When a VDS fault occurs, and the bridge is disabled, and the fault is latched, the OLn terminal is immediately driven low. The latch can only be reset by going into standby or by dropping V BB below the UVLO threshold. Standby Mode Low power standby mode is activated when SLEEPn is brought low. Standby mode disables most of the internal circuitry, including the charge pump and internal regulator. When coming out of standby mode, the A4955 requires up to 300 μs before the outputs can respond to input commands. TSD If the die temperature increases to approximately T TSD, the full bridge outputs will be disabled until the internal temperature falls below T TSD minus a hysteresis level of T HYS. Fault Shutdown In the event of a fault due to excessive junction temperature, or low voltage on VP or, the outputs of the device are disabled until the fault condition is removed. At power-up, the UVLO circuit disables the drivers until the UVLO thresholds are exceeded. 7

8 TERMINAL IRUIT DIAGRAMS SX 6.7 V VP IN IN R VREF SLEEPn R OLn 0 V GHX VP GLX 8 V 6.7 V SX P VP 8 V P 56 V 8 V 8

9 PAKAGE OUTLINE DRAWINGS For Reference Only Not for Tooling Use (Reference JEDE MO-0WGGD) Dimensions in millimeters NOT TO SALE Exact case and lead configuration at supplier discretion within limits shown A 4.00 ± ± X D ±0.05 SEATING PLANE PB Layout Reference View BS A Terminal # mark area 0.45 B.45 B D Exposed thermal pad (reference only, terminal # identifier appearance at supplier discretion) Reference land pattern layout (reference IP735 QFN50P400X400X80-BM); all pads a minimum of 0.0 mm from all adjacent pads; adjust as necessary to meet application process requirements and PB layout tolerances; when mounting on a multilayer PB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDE Standard JESD5-5) oplanarity includes exposed thermal pad and terminals ES Package, 0-Pin QFN with Exposed Thermal Pad 9

10 ± For Reference Only Not for Tooling Use (Reference MO-53 AT) NOT TO SALE Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown 8º 0º ± ±0.0 A 0.60 ± REF 0X MAX SEATING PLANE 0.5 BS SEATING PLANE GAUGE PLANE BS NNNNNNN YYWW LLLLLLL D Standard Branding Reference View N = Device part number = Supplier emblem Y= Last two digits of year of manufacture W = Week of manufacture L= Lot number B 4.0 PB Layout Reference View A B D Terminal # mark area Exposed thermal pad (bottom surface) Branding scale and appearance at supplier discretion LP Package, 0-Pin etssop with Exposed Thermal Pad Reference land pattern layout (reference IP735 SOP65P640X0-M); all pads a minimum of 0.0 mm from all adjacent pads; adjust as necessary to meet application process requirements and PB layout tolerances; when mounting on a multilayer PB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDE Standard JESD5-5) 0

11 Revision History Revision Revision Date Description of Revision February, 05 Initial Release July 4, 05 Updated functional block diagram (page ); added packing information (page ); changed references to LSS to November 30, 07 Updated section (page 6) opyright 07, reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: