BiCMOS Advanced Sign Magnitude 20-Bit DIGITAL-TO-ANALOG CONVERTER

Transcription

1 9% FPO P U BiCMOS Advanced Sign Magnitude 0-Bit DIGITAL-TO-ANALOG CONVERTER FEATURES ULTRA LOW 9dB max THDN (No External Adjustment Required) NEAR-IDEAL LOW LEVEL OPERATION GLITCH-FREE OUTPUT 0dB SNR TYP (A-Weight Method) INDUSTRY STD SERIAL INPUT FORMAT FAST (00ns) CURRENT OUTPUT (±.ma) CAPABLE OF X OVERSAMPLING COMPLETE WITH REFERENCE LOW POWER (50mW typ) DESCRIPTION The is a precision 0-bit digital-to-analog converter with ultra-low distortion ( 9dB typ with a full scale output). Incorporated into the is an advanced sign magnitude architecture that eliminates unwanted glitches and other nonlinearities around bipolar zero. The also features a very low noise (0dB typ SNR: A-weighted method) and fast settling current output (00ns typ,.ma step) which is capable of X oversampling rates. Applications include very low distortion frequency synthesis and high-end consumer and professional digital audio applications. Clock Data LE Input Shift Register and Control Logic Balanced Current Segment DAC A DCOM ACOM V CC V CC Reference and Servo Balanced Current Segment DAC B Bipolar Offset I OUT RF DC SERV DC BPO DC International Airport Industrial Park Mailing Address: PO Box 00 Tucson, AZ 8573 Street Address: 730 S. Tucson Blvd. Tucson, AZ 8570 Tel: (50) 7- Twx: Cable: BBRCORP Telex: 0-9 FAX: (50) Immediate Product Info: (800) Burr-Brown Corporation PDS-75B Printed in U.S.A. June, 995 SBAS0

2 SPECIFICATIONS All specifications at 5 C, ±V CC and V DD = ±5V unless otherwise noted. P/U, -J, -K PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 0 Bits DYNAMIC RANGE, THD N at 0dB Referred to Full Scale, with A-weight 0 db DIGITAL INPUT Logic Family TTL/CMOS Compatible Logic Level: V IH. V DD V V IL V I IH V IH = V DD ±0 µa I IL V IL = 0V ±0 µa Data Format Serial, MSB First, BTC () Input Clock Frequency MHz TOTAL HARMONIC DISTORTION N () P/U = 0dB f S = 35.8kHz (3), f = 00Hz () 9 88 db = 0dB f S = 35.8kHz (3), f = 00Hz () 8 7 db = 0dB f S = 35.8kHz (3), f = 00Hz () 0 db P/U, -J = 0dB f S = 35.8kHz (3), f = 00Hz () 9 9 db = 0dB f S = 35.8kHz (3), f = 00Hz () 83 7 db = 0dB f S = 35.8kHz (3), f = 00Hz () 8 db P/U, -K = 0dB f S = 35.8kHz (3), f = 00Hz () 00 9 db = 0dB f S = 35.8kHz (3), f = 00Hz () 8 80 db = 0dB f S = 35.8kHz (3), f = 00Hz () 50 db ACCURACY Level Linearity At 90dB Signal Level ±0.5 db Gain Error ±0.5 ±3 % Bipolar Zero Error (5) ±0.5 % Gain Drift 0 C to 70 C ±5 ppm of FSR/ C Bipolar Zero Drift 0 C to 70 C ±5 ppm of FSR/ C Warm-up Time minute IDLE CHANNEL SNR () Bipolar Zero, A-weighted Filter 0 0 db ANALOG OUTPUT Output Range ±. ma Output Impedance.0 kω Settling Time (±0.003% of FSR,.mA Step) 00 ns Glitch Energy No Glitch Around Zero POWER SUPPLY REQUIREMENTS Supply Voltage Range: V CC = V DD V V CC = V DD V Combined Supply Current: I CC V CC = V DD = 5V ma Combined Supply Current: I CC V CC = V DD = 5V ma Power Dissipation ±V CC = ±V DD = ±5V mw TEMPERATURE RANGE Operating 5 85 C Storage 55 5 C NOTES: () Binary Two s Complement coding. () Ratio of (Distortion RMS Noise RMS ) / Signal RMS. (3) D/A converter sample frequency (8 x.khz; 8x oversampling). () D/A converter output frequency (signal level). (5) Offset error at bipolar zero. () Measured using an OPA7 and 5kΩ feedback and an A-weighted filter. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

3 ABSOLUTE MAXIMUM RATINGS (DIP Package) Power Supply Voltage... ±.5VDC Input Logic Voltage... DGND 0.3V~V DD 0.3V Operating Temperature... 5 C to 85 C Storage Temperature C to 5 C Power Dissipation mW Lead Temperature (soldering, 0s)... 0 C ABSOLUTE MAXIMUM RATINGS (SOP Package) Power Supply Voltage... ±.5VDC Input Logic Voltage... DGND 0.3V~V DD 0.3V Operating Temperature... 5 C to 85 C Storage Temperature C to 5 C Power Dissipation mW Lead Temperature (soldering, 5s)... 0 C PIN ASSIGNMENTS (DIP Package) PIN MNEMONIC PIN MNEMONIC DATA 9 V CC CLOCK 0 BPO DC 3 V DD I OUT DCOM ACOM 5 V DD 3 ACOM LE SERV DC 7 NC 5 REF DC 8 NC V CC PACKAGE INFORMATION () PACKAGE DRAWING MODEL PACKAGE NUMBER P -Pin Plastic DIP 80 U 0-Pin Plastic SOP 8 NOTE: () For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. PIN ASSIGNMENTS (SOP Package) PIN MNEMONIC PIN MNEMONIC DATA V CC CLOCK BPO DC 3 NC 3 NC V DD I OUT 5 DCOM 5 ACOM V DD ACOM 7 LE 7 SERV DC 8 NC 8 NC 9 NC 9 RFE DC 0 NC 0 V CC GRADE MARKING (SOP Package) MODEL PACKAGE U Marked. U-J Marked with white dot by pin 0. U-K Marked with red dot by pin 0. CONNECTION DIAGRAM 7µF CLOCK DATA µf 5V V CC R NF LE 7 7 5V V DD 7µF 3 7µF UT 5V V DD 7µF µF 5V V CC 5 = SOP = DIP 3

4 TYPICAL PERFORMANCE CURVES All specifications at 5 C, ±V A and ±V D = ±5.0V unless otherwise noted. 0 THDN vs FREQUENCY 8 -BIT LEVEL LINEARITY (Dithered Fade-to-Noise) THDN (db) dB 0dB 0dB 0dB Deviation from Ideal Level (db) k 0k Output Frequency (Hz) Output Signal Level (db).5 -BIT MONOTONICITY 80 90dB SIGNAL SPECTRUM (00Hz Bandwidth) Output Voltage (mv) Power Spectrum (db) ms/div 0 0 k 8k k k 0k Frequency (Hz) 00 90dB SIGNAL (0Hz to 0kHz Bandwidth) 0 0dB SIGNAL (0Hz to 0kHz Bandwidth) Output Level (µv) Output Level (µv) Time (µs) Time (µs)

5 THEORY OF OPERATION ADVANCED SIGN MAGNITUDE Digital audio systems have traditionally used laser-trimmed, current-source DACs in order to achieve sufficient accuracy. However, even the best of these suffer from potential lowlevel nonlinearity due to errors at the major carry bipolar zero transition. More recently, DACs employing a different architecture which utilizes noise shaping techniques and very high over-sampling frequencies, have been introduced ( Bitstream, MASH, or -bit DAC). These DACs overcome the low level linearity problem, but only at the expense of signal-to-noise performance, and often to the detriment of channel separation and intermodulation distortion if the succeeding circuitry is not carefully designed. The is a new solution to the problem. It combines all the advantages of a conventional DAC (excellent full scale performance, high signal-to-noise ratio and ease of use) with superior low-level performance. Two DACs are combined in a complementary arrangement to produce an extremely linear output. The two DACs share a common reference, and a common R-R ladder for bit current sources by dual balanced current segments to ensure perfect tracking under all conditions. By interleaving the individual bits of each DAC and employing precise laser trimming of resistors, the highly accurate match required between DACs is achieved. This new, complementary linear or advanced sign magnitude approach, which steps away from zero with small steps in both directions, avoids any glitching or large linearity errors and provides an absolute current output. The low level performance of the is such that real 0-bit resolution can be realized, especially around the critical bipolar zero point. Table shows the conversion made by the internal logic of the from binary two s complement (BTC). Also, the resulting internal codes to the upper and lower DACs (see front page block diagram) are listed. Notice that only the LSB portions of either internal DAC are changing around bipolar zero. This accounts for the superlative performance of the in this area of operation. DISCUSSION OF SPECIFICATIONS DYNAMIC SPECIFICATIONS Total Harmonic Distortion Noise The key specifications for the is total harmonic distortion plus noise (THDN). Digital data words are read into the at eight times the standard compact disk audio sampling frequency of.khz (35.8kHz) so that a sine wave output of 00Hz is realized. For production testing, the output of the DAC goes to an I to V converter, then through a 0kHz low pass filter, and then to a programmable gain amplifier to provide gain at lower signal output test levels before being fed into an analog-type distortion analyzer. Figure shows a block diagram of the production THDN test setup. For the audio bandwidth, THDN of the is essentially flat for all frequencies. The typical performance curve, THDN vs Frequency, shows four different output signal levels: 0dB, 0dB, 0dB, and 0dB. The test signals are derived from a special compact test disk (the CBS CD-). It is interesting to note that the 0dB signal falls only about 0dB below the full scale signal instead of the expected 0dB. This is primarily due to the superior low level signal performance of the advanced sign magnitude architecture of the. In terms of signal measurement, THDN is the ratio of Distortion RMS Noise RMS / Signal RMS expressed in db. For the, THDN is 00% tested at all three specified output levels using the test setup shown in Figure. It is significant to note that this test setup does not include any output deglitching circuitry. All specifications are achieved without the use of external deglitchers. Dynamic Range Dynamic range in audio converters is specified as the measure of THDN at an effective output signal level of 0dB referred to 0dB. Resolution is commonly used as a theoretical measure of dynamic range, but it does not take into account the effects of distortion and noise at low signal levels. The advanced sign magnitude architecture of the, with its ideal performance around bipolar zero, provides a more usable dynamic range, even using the strict audio definition, than any previously available D/A converter. INPUT CODE LOWER DAC CODE UPPER DAC CODE ANALOG OUTPUT (0-bit Binary Two's Complement) (9-bit Straight Binary) (9-bit Straight Binary) Full Scale LSB ()... Full Scale LSB LSB ()...0 Bipolar Zero LSB LSB () Bipolar Zero LSB LSB () Bipolar Zero LSB () Bipolar Zero LSB Bipolar Zero LSB Full Scale LSB Full Scale NOTE: () The extra weight of LSB is added at this point to make the transfer function symmetrical around bipolar zero. TABLE I. Binary Two's Complement to Sign Magnitude Conversion Chart. 5

6 Use 00Hz High-Pass Filter and 30kHz Low-Pass Filter Meter Settings Distortion Analyzer Programmable Gain Amp 0dB to 0dB Low-Pass Filter 0kHz 3rd Order GIC Type (Shiba Soku Model 75 or Equivalent) Binary Counter Digital Code (EPROM) DATA Parallel-to-Serial Conversion DUT () I to V Converter OPA7 CLOCK LE (Latch Enable) Timing Logic Sampling Rate =.khz x 8(35.8kHz) Output Frequency = 00Hz FIGURE. Production THDN Test Setup. Level Linearity Deviation from ideal versus actual signal level is sometimes called level linearity in digital audio converter testing. See the 90dB Signal Spectrum plot in the Typical Performance Curves section for the power spectrum of a at a 90dB output level. (The 90dB Signal plot shows the actual 90dB output of the DAC). The deviation from ideal for at this signal level is typically less than ±0.3dB. For the 0dB Signal plot in the Typical Performance Curves section, true 0-bit digital code is used to generate a 0dB output signal. This type of performance is possible only with the lownoise, near-theoretical performance around bipolar zero of the advanced sign magnitude. A commonly tested digital audio parameter is the amount of deviation from ideal of a khz signal when its amplitude is decreased form 0dB to 0dB. A digitally dithered input signal is applied to reach effective output levels of 0dB using only the available -bit code from a special compact disk test input. See the -bit Level Linearity plot in the Typical Performance Curves section for the results of a tested using this -bit dithered fade-to-noise signal. Note the very small deviation from ideal as the signal goes from 0dB to 00dB. DC SPECIFICATION Idle Channel SNR Another appropriate specification for a digital audio converter is idle channel signal-to-noise ratio (idle channel SNR). This is the ratio of noise on the DAC output at bipolar zero in relation to the full scale range of the DAC. To make this measurement, the digital input is continuously fed the code for bipolar zero, while the output of the DAC is bandlimited from 0Hz to 0kHz and an A-weighted filter is applied. The idle channel SNR for the is typically greater than 0dB, making it ideal for low-noise applications. Monotonicity Because of the unique advanced sign magnitude architecture of the, increasing values of digital input will always result in increasing values of DAC output as the signal moves away from bipolar zero in one-lsb steps (in either direction). The -bit Monotonicity plot in the Typical Performance Curves section was generated using -bit digital code from a test compact disk. The test starts with 0 periods of bipolar zero. Next are 0 periods of alternating LSBs above and below zero, and then 0 periods of alternating LSBs above and below zero, and so on until 0LSBs above and below zero are reached. The signal pattern then begins again at bipolar zero. With, the low-noise steps are clearly defined and increase in near-perfect proportion. This performance is achieved without any external adjustments. By contrast, sigma-delta ( Bit-stream, MASH, or -bit DAC) architectures are too noisy to even see the first 3 or bits change (at bits), other than by a change in the noise level. Absolute Linearity Even though absolute integral and differential linearity specs are not given for the, the extremely low THDN performance is typically indicative of 7-bit integral linearity in the DAC. The relationship between THDN and linearity, however, is not such that an absolute linearity specification for every individual output code can be guaranteed. Offset, Gain, and Temperature Drift Although the is primarily meant for use in dynamic applications, specifications are also given for more traditional DC parameters such as gain error, bipolar zero offset error, and temperature gain and offset drift. DIGITAL INPUT Timing Considerations The accepts TTL compatible logic input levels. The data format of the is binary two s complement (BTC) with the most significant bit (MSB) being first

7 in the serial input bit stream. Table II describes the exact relationship of input data to voltage output coding. Any number of bits can precede the 0 bits to be loaded, since only the last 0 will be transferred to the parallel DAC register after Latch Enable (Pin <P>, Pin7 <U>, LE) has gone low. All DAC serial input data (Pin, DATA) bit transfers are triggered on positive clock (Pin, CLOCK), edges. The serial-to-parallel data transfer to the DAC occurs on the falling edge of Latch Enable. The change in the output of the DAC occurs at a rising edge of the th clock of the CLOCK after the falling edge of Latch Enable. Refer to Figure for graphical relationships of these signals. Maximum Clock Rate A typical clock rate of.9mhz for the is derived by multiplying the standard audio sample rate of.khz by sixteen times (X over-sampling) the standard audio word bit length of bits (.khz x x =.9MHz). Note that this clock rate accommodates a -bit word length, even though only 0 bits are actually being used. The setup and hold timing relationships are shown in Figure 3. Stopped Clock Operation The is normally operated with a continuous clock input signal. If the clock is to be stopped between input data words, the last 0 bits shifted in are not actually shifted from the serial register to the latched parallel DAC register until Latch Enable goes low. Latch Enable must remain low until after the first clock cycle of the next data word to insure proper DAC operation. In any case, the setup and hold times for Data and LE must be observed as shown in Figure 3. INSTALLATION POWER SUPPLIES Refer to CONNECTION DIAGRAM for proper connection of the. The only requires a ±5V supply. Both positive supplies should be tied together at a single point. Similarly, both negative supplies should be connected together. No real advantage is gained by using separate analog and digital supplies. It is more important that both these supplies be as clean as possible to reduce coupling of supply noise to the output. Power supply decoupling capacitors should be used at each supply pin to maximize power supply rejection, as shown in CONNECTION DIA- GRAM regardless of how good the supplies are. Both commons should be connected to an analog ground plane as close to the as possible. FILTER CAPACITOR REQUIREMENTS As shown in CONNECTION DIAGRAM, various size decoupling capacitors can be used, with no special tolerances being required. The size of the offset decoupling capacitor is not critical either, with larger values (up to ) giving slightly better SNR readings. All capacitors should be as close to the appropriate pins of the as possible to reduce noise pickup from surrounding circuitry. Data Input > 0ns LSB > 5ns > 5ns MSB DIGITAL INPUT ANALOG OUTPUT CURRENT OUTPUT,08,57LSBs Full Scale Range mA LSB NA.88805nA 7FFFF HEX Full Scale mA HEX Bipolar Zero LSB mA HEX Full Scale mA Clock Input Latch Enable > 0ns > 0ns > 5ns > 5ns > One Clock Cycle > One Clock Cycle TABLE II. Digital Input/Output Relationships. FIGURE 3. Setup and Hold Timing Diagram. Clock DATA "N" Data MSB LSB Latch Enable I OUT N- N NOTES : () If clock is stopped between input of 0-bit data words, "Latch" Enable (LE) must remain low until after the first clock cycle of the next 0-bit data word stream. () Data format is binary two's complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge. (3) Latch Enable (LE) must remain low at least one clock cycle after going negative. () Latch Enable (LE) must be high for at least one clock cycle before going negative. (5) I OUT changes on positive going edge of the th clock after negative going edge of Latch Enable (LE). FIGURE. Timing Diagram. 7

8 5V Interleaved Digital Input.93MHz (9F S ) MΩ 0pF 0pF 5V.7µF 7.kΩ 7 Digital Interface Format Receiver 8 φ A 8 BCO 5 L/R 5 DA 7 Yamaha YM Ω 700pF.7µF 0.µF 5V.7µF.7µF 3 7 8X Interpolation Digital Filter DOR 3 BCO 8 WCK 5 DOL Burr-Brown DF700P 00pF 8 0 5V V CC C 5 C C DATA BCK 5V P GND 5V LE 5V I OUT BPO DC 5V C 9 C 7 C 5 C 5 5V V CC 5V V CC RF.5kΩ C 55 0p IC C C C 3 5 DATA BCK 5V P GND 5V LE 5V I OUT BPO DC C 50 C 8 C 5 5V 5V V CC 5V V CC C 5 5V V CC RF.5kΩ C 5 0p IC3 R.0kΩ IC R 3.0kΩ IC3 R.0kΩ R 5.0kΩ C pF R 5.3kΩ C pF R 7.0kΩ R 8.0kΩ C pF R 9 5.3kΩ C 0 000pF IC IC IC-: OPA0 R 0 IC kω C 000pF Low-pass 3-pole Butterworth f 3dB = 0kHz R IC kω C 000pF Low-pass 3-pole Butterworth f 3dB = 0kHz See Application Bulletin AB-0 for information on GIC filters. FIGURE. Typical Application for Stereo Audio 8X Oversampling system. 8

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