PART OBSOLETE - USE PI3PCIE3412A

Transcription

1 PART OBSOLETE - USE A.V, PCI Express.0 -Lane, : Mux/DeMux Switch, with Single Enable Features Differential Channel, : Mux/DeMux PCI Express.0 Performance, 8.0Gbps Bi-directional Operation Low Bit-to-Bit Skew, 0ps max Low channel-to-channel skew, 0ps max Low Crosstalk: -db@ GHz High Off Isolation: -db@ GHz (8.0Gbps) Low insertion loss: -.db@ GHz (8.0Gbps) Return loss: -db@ GHz Support for DP. - HBR, HBR, RBR Supply Voltage.V Industrial Temperature Range: -0 o C to 8 o C Packaging (Pb-free & Green): -contact, TQFN (ZH),. x 9mm 0-contact, TQFN (ZL0), x mm Pin Configuration - 0- Contact TQFN A0 A0- A A- SEL A A- A A Description The is an 8 to differential channel multiplexer/ demultiplexer switch. This solution can switch full PCI Express.0, lanes to one of two locations. Using a unique design technique, Diodes has been able to minimize the impedance of the switch such that the attenuation observed through the switch is minimal. The unique design technique also offers a layout targeted for PCI Express signals, which minimizes the channel to channel skew as well as channel to channel crosstalk as required by the PCI Express specification. can also be used for application up to Gbps Application Routing of PCI Express.0, DP., USB.0, SAS.0, SATA.0, XAUI, RXAUI signals with low signal attenuation. Pin Configuration - - Contact TQFN B0 B0- B B- C0 C0- C C- B B- B B- C C- C C- A0 A0- A A- SEL A A- A A V D D GN D V D D GN D C- B0 C B0- B B- C0 C0- C C- B B- B B- C C- V D D D GN V D D D GN

2 PART OBSOLETE - USE A Block Diagram A0 A0- A A- A A- A A- SEL Truth Table Function A N to B N A N to C N SEL L H B0 B0- B B- C0 C0- C C- B B- B B- C C- C C-

3 PART OBSOLETE - USE A Pin Description -TQFN Pin # 0-TQFN Pin Name Description A0 A0 A A A A A A B0 B0 B B B B B B C0 C0 C C C C C C 9 SEL I, 8,,8, 0, 0, 0,,, 0,,, 9,, 9,, Center Pad Signal, Channel 0, Port A Signal, Channel, Port A Signal, Channel, Port A Signal, Channel, Port A Signal, Channel 0, Port B Signal, Channel, Port B Signal, Channel, Port B Signal, Channel, Port B Signal, Channel 0, Port C Signal, Channel, Port C Signal, Channel, Port C Signal, Channel, Port C,,,, 8, 8 8,,,, 8,,, 9, 0 Operation mode Select (when SEL=0: A B, when SEL=: A C Pwr.V ±0% Positive Supply Voltage Pwr Power ground

4 PART OBSOLETE - USE A Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature... C to C Supply Voltage to Ground Potential...0.V to.v Channel DC Input Voltage...0.V to.v DC Output Current...0mA Power Dissipation...0.W SEL DC Input Voltage...0.V to.v Electrical Characteristics Recommended Operating Conditions Switching Characteristics Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Symbol Parameter Conditions Min. Typ. Max. Units.V Power Supply.0.. V I DD Total current from.v supply SEL = 0V or 0. ma V -DIF Differential Voltage (differential pins). V ppd V -CM Common Mode Voltage (differiential pins) V T A Operating temperature range -0 8 o C DC Electrical Characteristics for Switching over Operating Range Parameters Description Test Conditions () Min. Typ. () Max. Units VIH - SEL Input HIGH Voltage, SEL Input. VIL - SEL Input LOW Voltage, SEL Input VIK Clamp Diode Voltage = Max., I IN = 8mA 0.. IIH Input HIGH Current, SEL = Max., V IN = ± IIL Input LOW Current, SEL = Max., V IN = 0V ± IIN - SEL Input Leakage Current, SEL Input V IN = V IH - SEL Max or V IL - SEL Min 0 0 µa IIH Input HIGH Current, A X, B X, C X = Max., V IN =.V 0 0 IIL Input LOW Current, A X, B X, C X = Max., V IN = 0V 0 0 IOZH HighZ HIGH Current, B X, C X = Max., V IN =.V 0 0 µa IOZL HighZ LOW Current, B X, C X = Max., V IN = 0V 0 0 µa C-ON ON state capacitance. pf RON ON state resistance =.V, IO = 8mA, V IN = 0.8V Ω Note:. Typical values are at =.V, T A = C ambient and maximum loading. Parameters Description Test Conditions Min. Typ. Max. Units tpzh, tpzl Line Enable Time - SEL to AN, BN, CN 0 tphz, tplz Line Disable Time - SEL to AN, BN, CN 0. tb-b Bit-to-bit skew within the same differential pair 0 ps tch-ch Channel-to-channel skew 0 ps V µa µa ns

5 PART OBSOLETE - USE A Dynamic Electrical Characteristics Parameter Description Test Conditions Min. Typ. () Max. Units DDIL Differential Insertion Loss (V IN = -0dBm, DC = 0V) f= MHz -.GHz f=.ghz -.GHz f=.ghz - GHz f=ghz f= MHz -.GHz DDIL OFF Differential Off Isolation f=.ghz -.GHz f=.ghz - GHz -. - db f=ghz - -0 f= MHz -.GHz -0 - DDRL Differential Return Loss f=.ghz -.GHz f=.ghz - GHz db f=ghz f= MHz -.GHz DDNEXT Near End Crosstalk f=.ghz -.GHz f=.ghz - GHz db f=ghz -. - Insertion loss.db, V IN =0.Vpp, DC=0V.0 V I F Max Signal Frequency Range Insertion loss.db, V IN =0.Vpp, DC=0.9V.0 Insertion loss db, V IN =0.Vpp, DC=0V 8.0 GHz Insertion loss db, V IN =0.Vpp, DC=0.9V 8.0 BW -db Bandwidth 8. GHz Notes:. Guaranteed by design. Typical values are at =.V, T a = C ambient and maximum loading. BALANCED PORT BALANCED PORT DUT BALANCED PORT DUT BALANCED PORT DUT BALANCED PORT BALANCED PORT db Diff. Insertion Loss and Return Test Circuit Diff. Off Isolation Test Circuit Diff. Near End Xtalk Test Circuit

6 PART OBSOLETE - USE A Differential Insertion Loss Differential Return Loss

7 PART OBSOLETE - USE A Differential Off Isolation Differential Crosstalk

8 PART OBSOLETE - USE A.0 Gbps RX signal eye without.0 Gbps RX signal eye with 8.0 Gbps RX signal eye without 8.0 Gbps RX signal eye with 8

9 PART OBSOLETE - USE A Test Circuit for Electrical Characteristics (-) Port Port D.U.T xen Switching Waveforms COM Port xen Output Output pf C L Tsw Tsw 00-ohm Tsw Switch Positions Test Switch t PLZ, t PZL.0V t PHZ, t PZH Prop Delay % % Tsw % % Voltage Waveforms Enable and Disable Times 0V VOH VOL VOH VOL Open Notes:. C L = Load capacitance: includes jig and probe capacitance.. R T = Termination resistance: should be equal to Z OUT of the Pulse Generator. Output is for an output with internal conditions such that the output is low except when disabled by the output control. Output is for an output with internal conditions such that the output is high except when disabled by the output control.. All input impulses are supplied by generators having the following characteristics: PRR MHz, Z O = Ω, t R.ns, t F.ns.. The outputs are measured one at a time with one transition per measurement. 9

10 PART OBSOLETE - USE A DP. Application DP Source DP TX AUX TX AUX RX Vbias_TX (0 -.V) Vbias_TX (0 -.V) SEL_GPIO DP_LANEx DP_LANEx# Same goes for other lanes DP_AUX DP_AUX# DP_HPD V_ and pins should be shorted to PCB power planes via shortest paths. V_ and V_ should be employed at the same time. AUX_P AUX_P DP_AUX AUX_N AUX_N DP_AUX# HEAT U0 A0 A0- A 8 A- 9 0 SEL A A- A A- B0 B0-8 B B- C0 C0- C C- 0 B B- 8 9 B B- C C- C C- V_ U0 IN SA #EN SA SD DA SD SB DD SB SC 8 DB SC 0 DC 9 PIV0 C V_.u_080 C0 u_080 C0 C0 HPD HPD DP_HPD C0 C0 C0 At least pc.uf and pc 0.uF decoupling capacitors are recommended. Each decoupling capacitor should be connected to PCB power plane via shortest path. C C C C C C C C8 C C C C C C8 C9 C0 AUX_N AUX_P C0 C08 C09 C0 C9 C0 AUX_N C AUX_P C u_080 u_080 V_ V_ J0 0 9 LCD_VCC LCD_VCC 8 LCD_VCC H_ LCD_VCC LCD_Self_Test LCD_ LCD_ AUX_CH_N LCD_ AUX_CH_P LCD_ H_ HPD Lane0_P 0 H_ Lane0_N BL_ 8 BL_ Lane_N Lane_P BL_ 0 BL_ H_ BL_ENABLE Lane_N Lane_P BL_PWM_DIM NC H_ Lane_N Lane_P H_ NC BL_PWR BL_PWR BL_PWR 8 BL_PWR 9 NC NC 0 Lane edp Source Receptacle J0 0 9 LCD_VCC LCD_VCC 8 LCD_VCC LCD_VCC LCD_Self_Test LCD_ H_ LCD_ AUX_CH_N LCD_ AUX_CH_P LCD_ H_ HPD Lane0_N Lane0_P BL_ Lane_P H_ BL_ 9 BL_ 0 8 H_ Lane_N Lane_P H_ Lane_N BL_ BL_ENABLE BL_PWM_DIM NC NC Lane_N Lane_P BL_PWR BL_PWR NC H_ BL_PWR 8 BL_PWR 9 NC 0 Lane edp Source Receptacle V_ V_ HPD HPD 0

11 PART OBSOLETE - USE A Packaging Information Notes:. All dimensions are in mm. Angles in degrees.. Coplanarity applies to the exposed pad as well as the terminals.. Refer JEDEC MO-0 DATE: 0// DESCRIPTION: 0-contact, Thin Fine Pitch Quad Flat No-Lead, TQFN PACKAGE CODE: ZL (ZL0) DOCUMENT CONTROL #: PD- REVISION: --

12 PART OBSOLETE - USE A Packaging Information Ordering Information Note: For latest package info, please check: Ordering Code Package Code Package Description ZLE ZL 0-contact, Thin Fine Pitch Quad Flat No-Lead (TQFN) ZLEX ZL 0-contact, Thin Fine Pitch Quad Flat No-Lead (TQFN), Tape & Reel ZHE ZH -contact, Very Thin Quad Flat No-Lead (TQFN) ZHEX ZH -contact, Very Thin Quad Flat No-Lead (TQFN), Tape & Reel Notes: Thermal characteristics can be found on the company web site at "E" denotes Pb-free and Green Adding an "X" at the end of the ordering code denotes tape and reel packaging

13 PART OBSOLETE - USE A IMPORTANT NOTICE DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes without further notice to this document and any product described herein. does not assume any liability arising out of the application or use of this document or any product described herein; neither does convey any license under its patent or trademark rights, nor the rights of others. Any Customer or user of this document or products described herein in such applications shall assume all risks of such use and will agree to hold and all the companies whose products are represented on website, harmless against all damages. does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized sales channel. Should Customers purchase or use products for any unintended or unauthorized application, Customers shall indemnify and hold Diodes Incorporated and its representatives harmless against all claims, damages, expenses, and attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized application. Products described herein may be covered by one or more United States, international or foreign patents pending. Product names and markings noted herein may also be covered by one or more United States, international or foreign trademarks. This document is written in English but may be translated into multiple languages for reference. Only the English version of this document is the final and determinative format released by. LIFE SUPPORT products are specifically not authorized for use as critical components in life support devices or systems without the express written approval of the Chief Executive Officer of. As used herein: A. Life support devices or systems are devices or systems which:. are intended to implant into the body, or. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user. B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or to affect its safety or effectiveness. Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of products in such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related information or support that may be provided by. Further, Customers must fully indemnify and its representatives against any damages arising out of the use of Diodes Incorporated products in such safety-critical, life support devices or systems. Copyright 0,