OSCILLATORS and timers are critical to all systems with

Transcription

1 1866 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 8, AUGUST 2016 An RC Oscillator With Comparator Offset Cancellation Arun Paidimarri, Member, IEEE, Danielle Griffith, Member, IEEE, Alice Wang, Senior Member, IEEE, Gangadhar Burra, Member, IEEE, and Anantha P. Chandrakasan, Fellow, IEEE Abstract A fully-integrated 18.5 khz RC time-constant-based oscillator is designed in 65 nm CMOS for sleep-mode timers in wireless sensors. A comparator offset cancellation scheme achieves 4 to 25 temperature stability improvement, leading to an accuracy of ±0.18% to ±0.55% over 40 to 90 C. Subthreshold operation and low-swing oscillations result in ultra-low power consumption of 130 nw. The architecture also provides timing noise suppression, leading to 10 reduction in long-term Allan deviation. It is measured to have a stability of 20 ppm or better for measurement intervals over 0.5 s. The oscillator also has a fast startup-time, with the period settling in 4 cycles. Index Terms Allan deviation, Allan variance, crystal replacement, guard time, offset cancellation, RC oscillator, Schmitt trigger, startup time, temperature stability, timing accuracy. I. INTRODUCTION OSCILLATORS and timers are critical to all systems with the frequency, accuracy, stability specifications dependent on the application. Some extreme low duty cycle systems such as [1] operate with a timing clock of only 12.8 Hz, have very intermittent activity, and achieve an average power of about 1 nw. On the other hand, standards-based wireless systems typically require accurate, low power timers to maintain protocol-level timing to ensure the radios are turned on at the right times [2]. The necessity for high-accuracy oscillators are made clear in the operation of slave sensor nodes in connectedmodes of Bluetooth Low Energy (BLE) or networks, especially at low duty cycles. These sensor nodes wake up periodically to receive beacons to synchronize transmissions. However, due to the potential inaccuracy of its clock, the receiver needs to be turned on for a guard time before the actual beacon in order to ensure reliable reception. This guard time t guard is given by: t guard = p t interval (1) where p is the fractional frequency inaccuracy in the timer and t interval is the packet interval. Since the full receiver is on during this guard time, at low duty cycles (or large Manuscript received November 3, 2015; revised March 20, 2016; accepted April 14, Date of publication May 30, 2016; date of current version July 25, This paper was approved by Associate Editor Andrea Baschirotto. A. Paidimarri and A. P. Chandrakasan are with the Massachusetts Institute of Technology (MIT), Cambridge, MA USA ( arun_p@mit.edu). D. Griffith is with Texas Instruments, Dallas, TX USA. A. Wang is with Mediatek, Hsinchu 300, Taiwan. G. Burra is with Qualcomm, San Jose, CA USA. Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /JSSC t interval ), the active energy consumption is dominated by this guard time (as it extends longer than the short BLE packets). This limits the average power of the system [2]. There is a tradeoff between spending higher power towards a more accurate oscillator (resulting in lower guard time) on the one hand and spending lower power in a less accurate oscillator (resulting in higher guard time) on the other hand. Wireless systems typically use 32 khz crystal oscillators since they provide both high accuracy and low power, with some recent works such as [3] showing power consumption below 6 nw. However, the external component results in board area and cost concerns, motivating the need for a fully-integrated replacement. One potential solution was demonstrated in [4] where a silicon-based resonator is integrated with the CMOS circuits to achieve an excellent ±2 ppm temperature accuracy and 0.4 μw power. In this paper, however, we explore fullyintegrated RC oscillators as an alternate low-cost solution. A. Oscillator Requirements In (1), inaccuracy of the timer, p, has three main sources. a) temperature, b) supply voltage and c) timing noise. Only transient sources of inaccuracies are considered since process variation related inaccuracies can be removed with a one-time calibration. Overall, p can be expressed as: p total = p temperature + p voltage + p Allan at tinterval (2) where the timing noise component is captured by the Allan deviation [5] at the given measurement duration (or averaging time) t interval. Allan deviation improves with increasing averaging of the white noise process. Eventually, at large averaging times, Allan deviation stops improving and is limited by flicker noise processes. Before discussing the core-oscillator design, we first consider system-level techniques that can improve on the intrinsic voltage and temperature inaccuracies of the oscillator. Supply voltage variation can be mitigated through the use of voltage regulators, either explicitly, or implicitly in the oscillator structure itself [6], [7]. Temperature variations can be mitigated by the use of temperature sensors and look-uptable based frequency compensation [8]. A second approach to mitigate temperature variation is to periodically wake up a higher-accuracy (and higher power) oscillator to measure and compensate the lower power oscillator [9], [10]. Timing noise, being random, however, cannot be calibrated out. In this work, we present a fully-integrated RC oscillator particularly focusing on improvements to intrinsic temperature and noise performance IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 PAIDIMARRI et al.: AN RC OSCILLATOR WITH COMPARATOR OFFSET CANCELLATION 1867 Fig. 1. A basic RC oscillator topology and associated timing diagram. Delay of the comparator and reset logic, t delay is neglected in the timing diagram for simplicity. B. Integrated RC Oscillators, Design Tradeoffs and Previous Work Fig. 1 shows the basic architecture of an RC oscillator (simplified version of [11]). The scheme results in an oscillation period of RC + t delay,wheret delay is the delay of the comparator and reset logic. t delay is assumed to be negligible in the timing diagram shown. A key advantage of this scheme is that it doesn t rely on absolute accuracy of the current source, and thus nominally eliminates a major source of uncertainty from the system. The key tradeoffs for low-power and high accuracy design are explained in detail in Section II, but are summarized in the following: a) The voltage swing can be reduced with low I, but, in the face of comparator offset, which is temperature dependent, a given offset affects the period by a larger fraction. This leads to worse temperature variation. b) Similarly, the input-referred noise as well as current source noise also leads to a larger effective timing noise. c) Low power consumption of the comparator, especially with offset constraints, results in finite speed (and thus finite t delay ), and variation in this speed due to temperature can now result in variation in the period. d) At low values of current source I, the temperature dependent leakage currents in the switches can have larger fractional effect on the period. Some alternate RC oscillator topologies use the exponential RC time-constant settling response [6], [12], [13], and have similar tradeoffs. These and other previous works are summarized below (and in Table I towards the end of the paper), focusing on some key circuit components. Comparator offset has been previously identified as a key bottleneck for low power RC-based oscillator design [7], [13] [15]. If offset is canceled, low swing operation is made feasible, and comparator design is eased, ultimately reducing power (see Section II). The voltage-averaging feedback scheme of [13] uses two comparators and an opamp, but eliminates comparator offsets and delays. It is shown to be effective for MHz-range oscillators. The self-chopped offset compensation schemes in [7] and [15] show that the clock output can itself be fed back to chop offsets, resulting in improved performance. The offset and delay compensation of [14] has an excellent scheme for overcoming comparator non-idealities, operates at low power (400 nw at 33 khz), and uses two comparators in the design. In this work, we present an RC oscillator architecture with a new offset cancellation scheme that requires a single comparator, allows low swing, low power operation and achieves 4 to 25 temperature variation reduction. The architecture also has noise canceling properties, resulting in about 10 Allan deviation reduction, similar to the design and analysis in [16]. This paper expands on the results initially presented in [17]. Choice of resistors is critical for the design of the oscillator, since temperature variation of the resistor results in variation of the period. Works such as [11], [12], [14], [18] have shown that two resistor types with opposing temperature coefficients (for example poly and diffusion resistors) can be combined to achieve high overall accuracy. In this work, we use nominally temperature compensated poly-resistors provided by the process itself. Finally, the design choice for the current reference used in an oscillator can vary depending up on the value of the required currents. Higher frequency oscillators that consume power in the μw range might use bandgap-referenced current and voltage [19]. However, lower power oscillators avoid these by making the frequency nominally independent of these factors. For currents in the tens of na and higher, constantg m current sources (such as in [7], [11]) and thresholdreferenced bias circuits (such as in [14]) are used. As the current values decrease, the values of the resistor used in the reference increases. Thus, to avoid area penalty, at even lower currents in the sub-na regime, higher valued current references are duty-cycled (in the tens of pa regime in [20]), or triode-based transistors are used as resistors (as done in [21]) or gate leakage in thin-oxide devices is used (as in [8]). In this paper, the oscillator is designed for the tens of khz regime for wireless protocol timing applications, and the power budget allows the use of a simple constant-g m current reference. This paper is organized as follows. In Section II, the architecture along with its operation are presented. Analysis of the offset and noise cancellation properties are discussed along with analysis of the effects of various component matching. Section III discusses the design and tradeoffs of individual circuit blocks in the oscillator. Section IV presents measurement results for a testchip fabricated in a 65 nm CMOS process.

3 1868 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 8, AUGUST 2016 Fig. 2. Architecture of the RC oscillator with offset compensation. Fig. 3. Nominal timing diagram of the RC oscillator. Delay of the comparator and Schmitt trigger, t delay, is neglected for simplicity. II. OFFSET CANCELLATION OSCILLATOR ARCHITECTURE Fig. 2 shows the architecture of the offset-canceling oscillator. It has a timing circuit, a continuous time comparator and a Schmitt trigger. The timing circuit includes two matched current sources I, two matched capacitors C and a resistor R. We first describe the nominal operation and then discuss process variation, temperature stability and noise performance. A. Nominal Operation The circuit operates in two phases, as shown in the nominal timing diagram in Fig. 3. In phase φ = 0, node V 2 sets a reference voltage of I R at the negative terminal of the comparator. Node V 1 ramps up and triggers the comparator when the voltage crosses I R which then flips the phase of operation, making φ = 1. Small glitches at the output of the comparator during phase change are eliminated with the Schmitt trigger. The operation during phase φ = 1is symmetric, with V 2 = I R and V 1 ramping. The duration of each phase, and the total period of oscillation is given by: t phase = R C + t delay (3) t period = 2R C + 2t delay (4) where t delay is the delay of the comparator and Schmitt trigger circuits. This non-ideal t delay causes the actual swing on the capacitors to be slightly larger than I R. In order to ensure that the passives determine the period and the temperature stability for the oscillator, it is desirable to minimize t delay with a high-speed comparator. The timing diagram in Fig. 3 is thus drawn assuming t delay = 0, for simplicity. B. Effect of Mismatch and Process Variation Process variation in the values of R and C can directly affect the period, based on (4), but can be compensated with a one-time calibration. Process variation in I does not nominally impact the period, however it can affect voltage swings (= I R) and comparator bandwidth, and can again be one-time calibrated. Mismatch variations in the values of C and I, however, need to be considered carefully. Finally, mismatch in the comparator leads to offset, which also affects period. All these mismatch and process variation effects are analyzed below. Fig. 4 shows the circuit diagrams for two phases of operation in the presence of mismatch. Fig. 4(c) shows the waveforms and timing for this. The two current sources are I 1 and I 2, the capacitors are C 1 and C 2 and the comparator offset is V os. The duration of the two phases, and the total

4 PAIDIMARRI et al.: AN RC OSCILLATOR WITH COMPARATOR OFFSET CANCELLATION 1869 Fig. 4. Operation of the RC oscillator under mismatch, showing the circuit for the two phases as well as the timing diagram. (a) Operation for phase φ = 0. (b) Operation for phase φ = 1. (c) Timing diagram for the oscillator under mismatch conditions. period are given by: t φ=0 = (I 2 R + V os ) C1 + t delay (5) I 1 t φ=1 = (I 1 R V os ) C2 + t delay (6) I [ 2 RC1 I 2 t period = + RC ] [ 2 I 1 C1 + V os C ] 2 + 2t delay. (7) I 1 I 2 I 1 I 2 Now, rewriting this by assuming a fractional mismatch of ±α, β around nominal values of C, I respectively [or, C 1 = C(1 + α) and C 2 = C(1 α), I 1 = I (1 β) and I 2 = I (1 + β)]: [ t φ=0 RC 1 + α + 2β + 2αβ + V ] os (1 + α + β + αβ) IR + t delay (8) [ t period 2RC 1 + 2αβ + V ] os (α + β) + 2t delay. (9) IR Thus, we see that with well matched components, the effect of offset on the overall period is significantly attentuated (by the factor (α + β)), as compared to the durations of the individual phases, where offset directly affects them without any attenuation. For example, even with modest mismatch numbers such as α +β = 5%, the effect of offset is attenuated by 20. Simulations of the implemented circuit at nominal operation indicate up to 100 reduction in offset-dependence. This demonstrates the offset canceling timing architecture. Because R is shared between the two phases, there is no mismatch term for this, improving robustness of the oscillator. Using a single shared resistor also saves die area. In addition, for processes where low temperature coefficient resistors are not available, a single external resistor is sufficient. Resistor sharing between the two phases is feasible because, during phase-change, only the current needs to be switched between I 1 and I 2. Since the currents are themselves well matched, the resistor voltage stays almost constant. Any transients in the voltage have half the period to stabilize, before the comparator needs to trigger, and this is easily met. Capacitor mismatch α directly affects offset cancellation, and it could be desirable to use the same capacitor for both phases of oscillations. However, unlike with resistor, during change of phase, the capacitor needs to be discharged to 0 V before the current sources are switched. This requires more complex timing with separate small-time-constant pulse generation circuits, as done in [21]. Such an alternative was not chosen, in order to avoid extending t delay and its temperature and process dependencies. In addition, because of the use of large capacitors, and common-centroid layout, the mismatch α can be kept small. C. Temperature Variation The sources of temperature variation for the oscillator are the temperature variation of the resistor, the capacitors, switch

5 1870 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 8, AUGUST 2016 matrix (S 1 S 6 ), comparator offset and comparator delay. Capacitors are implemented as metal oxide metal (MOM) capacitors, and thus have negligible temperature variation. The on-chip resistors in this work have a special zerotemperature coefficient design, where the linear temperature dependence is removed, giving low overall temperature dependence. An alternative is, as shown in previous work such as [14], [18], to use two resistors of different temperature coefficients and cancel their effects. A third alternative is to use one low temperature coefficient external resistor. The switches S 1 S 6 have finite on-resistance and offleakage, which in turn change with temperature and can thus affect the period of oscillations. Section III will discuss the detailed design considerations for the switches in this design. Given low temperature coefficient of the intrinsic RC time constant, it is critical to ensure that the rest of the circuit does not start to dominate the overall performance. The comparator is designed with constant-g m biasing in order to achieve constant bandwidth across temperature and thus, constant comparator delay. The delay of the Schmitt trigger and buffers is designed to be much smaller than the delay of the comparator itself. Temperature variation in the comparator offset is attenuated by the factor (α+β) through the offset cancellation scheme. This significantly relaxes the requirements for offset in the comparator design, making it easier to build a lowpower high-speed comparator. More of the circuit design is described in Section III. The impact of offset in (9) is also a function of the swing I R, where larger swing implies more robustness. However, because of the offset cancellation architecture, a low-swing design is feasible, 1 thus significantly reducing power consumption. For example, in this work, a swing of only 150 mv is used. If offset varies by 10 mv across temperature, when no offset-cancellation is applied, the frequency varies by as much as 6%. However, with offset-cancellation, simulations indicate that this is attenuated by 100 to 0.06%. 2 D. Noise and Allan Deviation Noise in the circuits lead to variation in the timing of edges in the oscillator. For the applications described in Section I, the long-term variation of this timing noise is important, and is typically characterized by the Allan deviation. For measurement of long time intervals, this is preferred over phase noise [22] based characterization of the oscillator noise, even though they are equivalent [5]. Allan deviation is estimated by: [ ] σ(τ) M 1 1/2 1 ( ) = f est,k+1 2 f est,k (10) 2(M 1) k=1 where f est,k is the estimated frequency during the interval [τ k,τ (k + 1)] [5]. This indicates the uncertainty in the 1 The impact of offset on the total period in (9) is a factor (α + β) lower than the impact of offset on the phase duration in (8). Thus, the oscillator can now be operated with low swings. 2 Simulations are performed with artificially applied offset to an ideal comparator in order to capture only the offset-cancellation aspects of the design. In reality, temperature dependence of R C delay as well as t delay will limit amount of cancellation Fig. 5. An alternate switch matrix design that can potentially ease the design. (Not implemented.). measurement of consecutive periods of duration τ. The Allan deviation improves with averaging of white frequency noise sources as τ 0.5, while flicker frequency noise sources result in an Allan deviation floor. This long-term noise floor dictated by flicker noise sources ultimately limits the timing accuracy. The primary noise sources are the low frequency noise in the current sources I 1 and I 2, in the comparator and the resistor. Flicker noise in I 1 and I 2 result in β variation. 3 The duration of each phase of the oscillator offers no attenuation to the noise (8), but its effect on total period variation is attenuated by the capacitor mismatch factor α. Flicker noise in the comparator translates to long-term variation of the offset of the comparator V os, which is attenuated by the offset-cancellation scheme. Resistor noise results in variation in the i noise,rms R reference noise, but, this is not differential between the two phases, and is thus not canceled by the offset cancellation scheme. However, since the noise is white, this is averaged out, and long-term Allan deviation is unaffected [5]. Thus, overall, the architecture is robust to noise sources, and can result in excellent long-term Allan deviation results. E. Summary of Design Considerations The architecture of the oscillator allows significant power reduction as a result of the following design choices: 1) The architecture requires only one comparator. 2) The design of the comparator requires optimization of gain and bandwidth with only weak constraints on the offset and flicker noise performance. This results in a low-power comparator implementation. 3) Given the attenuation of offset and its variation with temperature, the architecture allows low swings (I R), thereby allowing operation at low currents. III. CIRCUIT DESIGN AND TRADEOFFS In this design, R = 5M and C = 5 pf for an RC time constant of 25 μs, giving a nominal frequency around 20 khz (4). The charging current I is 30 na, for a swing of 150 mv. 3 This results from flicker noise in the current mirror transistors. Flicker noise in the PTAT reference itself manifests as common-mode variation in I, and has a negligible effect on the period.

6 PAIDIMARRI et al.: AN RC OSCILLATOR WITH COMPARATOR OFFSET CANCELLATION 1871 Fig. 6. Implementation of the comparator and Schmitt trigger circuits. Fig. 7. Implementation and measurement results for the PTAT current reference. (a) Implementation of the current reference. (b) Measured current source output as a function of temperature showing PTAT behavior. A. Switch Matrix We now look at the design of the switch matrix S 1 S 6. Switches S 5 6 discharge the capacitors. These switches are sized for low leakage, while the resistance requirement R sw R (= 5M ) is easily met since V GS,on,S5,6 = V DD. Leakage of S 5 6 is important because it is exponential with temperature and diverts current from charging the capacitor C, thereby affecting timing. Switches S 3 4, when off, operate at V GS,off,S3,4 = I R. It results in reduced leakage (by up to 30 ), which is thus negligible. However, when on, V GS,on,S3 4 = V DD I R, and the comparator trigger voltage has an error of I R S3 4.Temperature variation of this voltage error through on-resistance change can lead to frequency variation. Switches S 1 2 are the most stringent in their design. When off, V GS,off,S1 2 = 0, and when on, they have a voltage error arising from the finite switch resistance. Overall, if the voltage error from S 1 2 is equal to the voltage error of S 3 4, timing is unaffected, but switch resistance differences as low as 5 k can lead to a frequency error of 0.1%. Similarly, if the leakage of S 5 6 is equal to the leakage of S 1 2, timing is unaffected, but, leakage mismatch as low as 30 pa can lead to frequency error of 0.1%. Thus, the switches need to be optimally sized and matched. The various device flavors available in the process are explored for optimal design. High-V t, low-leakage 1.8 V capable devices are chosen for the switch matrix due to their nominally high on/off current ratio (equivalently low offleakage and low on-resistance). Additionally, V t varies with device length and width [23], [24]. Thus, device sizing is optimized to meet the switch resistance and leakage requirements described above, keeping the timing unaffected. However, an alternate switch matrix design using a 4-point probe (or Kelvin connection) as shown in Fig. 5 could be utilized to relax the requirements and ease the design process. The resistance constraints on switches S 1 4 are eliminated. Switches S 7 10 multiplex voltages onto the comparator and do not conduct current. 4 4 This technique was brought to our attention during the Q & A session at the conference presentation of this work at [17]

7 1872 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 8, AUGUST 2016 Fig. 8. Die photo of the RC oscillator in 65 nm LPCMOS. Fig. 10. Variation in period of oscillator with supply voltage for four chips. Fig. 9. Measured tuning range of the oscillator period with digitally tuned R and C. The frequency tunes from 9 khz up to 30 khz. B. Comparator The comparator used in this design is shown in Fig. 6. The primary requirements are low current, high bandwidth and constant delay across temperature, while secondary requirements are low-offset. The comparator needs to handle low common-mode voltages around 150 mv. A PMOS input pair topology is chosen due to the low input common-mode voltage required. Sub-threshold operation and constant-g m biasing (with PTAT current biasing) leads to nominally constant bandwidth across temperature, and consequently, constant delay. The nominal delay of the comparator is designed to be about 100 ns, or 0.4% of the period. The comparator consumes about 50 na, with 30 na in the first differential stage, and the average current of the second stage about 20 na. In addition. Additionally, both statistical and systematic variations in the offset are minimized through common-centroid layout and careful sizing of the second stage, respectively. C. Schmitt Trigger and Buffers During the change of phase, when nodes V 1 and V 2 switch roles, in order to prevent potential glitching, a Schmitt trigger Fig. 11. Startup time of the oscillator shows the period settling in 4 cycles to an accuracy better than ±1%. Both the current source and oscillator enables are turned on simultaneously. stage is used. Shown in Fig. 6, weak high-v t transistors are added to provide a small hysteresis (tens of mv in simulations). The Schmitt trigger and inverter-chain buffers make the edge from the comparator sharp, and give strong rail-to-rail outputs. The delay of these is about 10 ns, and is much smaller than the comparator delay, and thus does not affect overall oscillator performance. The current consumption of these buffers is also lower than 10 na. D. Current Source The PTAT current reference for the oscillator is shown in Fig. 7(a) [25]. This current reference is designed to supply currents to other blocks in the system including LDOs, and thus operates from the I/O supply. It includes a 5 M reference resistor and has a quiescent current of 25 na, while generating an output current of 10 na. Long-length, and wide devices are used to improve matching, resulting in a Monte-Carlo mismatch variation of ±0.5 na. IV. MEASUREMENTS The oscillator was fabricated in a 65 nm CMOS process. The die photograph is shown in Fig. 8. The RC oscillator

8 PAIDIMARRI et al.: AN RC OSCILLATOR WITH COMPARATOR OFFSET CANCELLATION 1873 Fig. 12. Measured temperature variation for four chips showing variation in the period, contribution due to the resistors as well as the contribution of the rest of the circuits (a) Temperature variation of oscillator period (b) Temperature variation of replica resistors (c) Temperature variation of oscillator period minus the variation due to the resistors. occupies an area of mm 2 while the current reference occupies as additional mm 2. A. Nominal Performance The oscillator core operates from a 1 V supply. The current reference is designed to operate off a battery voltage of V in order to supply currents to other blocks of a wireless SoC, including battery management and LDOs. The PTAT current reference draws 25 na, and provides a nominal output of 10 na at room temperature. Fig. 7(b) shows the measured PTAT performance of the current source in the 40 Cto+90 C range. The oscillator core itself consumes 130 na, 5 with 30 na each consumed by the current sources charging the R and C, 50 na in the comparator, 10 na in the Schmitt trigger and the buffers and 10 na in the current mirror from the current reference. Fig. 9 shows the period of the oscillator as the on-chip R and C are tuned digitally. It shows linear relationship of the period to linear increase in R or C. The frequency can be tuned from 9 khz up to about 30 khz. The nominal frequency of 5 In our original conference paper, [17], the current reported was 120 na, however, further measurements with multiple chips showed better performance with slightly increased current in the comparator. the oscillator is chosen at the mid-range, at 18.5 khz. All temperature and noise measurements are performed at this operating point. The voltage variation of the oscillator is plotted in Fig. 10 for four measured chips. The chips have variation around 0.4%/V up to about 5%/V for the worst-case chip. However, since the total variation is lower than ±0.12% across 50 mv, only a coarse-regulated LDO/power supply is needed to maintain constant frequency. For example, the architecture of [6] includes a coarse voltage regulator to significantly improve the voltage accuracy of the oscillator. Because there are no long time-constant bias voltages in the oscillator, the startup-time is low. Fig. 11 shows the measured startup transient of the oscillator. Both the current source and oscillator enable signals are turned on simultaneously. The oscillator period settles in 4 cycles to an accuracy better than ±1% of the steady-state period. If the current source is already enabled, the settling time reduces to 2 cycles. B. Temperature Variation Experiments for temperature variation were performed for four chips to characterize the resistor temperature variation and the offset cancellation. All measurements were performed across the temperature range of 40 C to +90 C unless otherwise specified.

9 1874 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 8, AUGUST 2016 Fig. 13. Variation of the full period and phase of the oscillator versus temperature. It shows the effect of the offset cancellation architecture. Fig. 15. The Allan deviation measurement noise floor is 30 ppb. The measurement setup uses a 48 MHz crystal oscillator as a frequency reference. from 4 to as high as 25 between the chips. This strongly shows the benefit of the offset cancellation scheme, especially at the low voltage swings (and current levels) used in this design. Finally, a copy of the oscillator with Nwell resistors instead of the temperature compensated resistor is characterized in Fig. 14. The variation is as high as ±2.6%. This shows the importance of temperature compensation of the resistor itself. Fig. 14. The oscillator performance with Nwell resistors shows degraded performance due to the temperature variation of the resistor. Fig. 12(a) shows the performance with on-chip temperature compensated resistors, while the temperature variation of replica resistors is plotted in Fig. 12(b). The resistors have very low temperature variation, below ±0.19% across the full temperature range. The temperature variation of the period for the four chips are ±0.18%, ±0.225%, ±0.25% and ±0.55%. If the temperature variation of the resistor is subtracted from that of the period, the resulting temperature variation is plotted in Fig. 12(c). We see that the residual temperature variation is still about the same (±0.19% to ±0.6%), though the shape changes. This variation is intrinsic to the active oscillator structure itself (without resistor variation), and includes the residual components of comparator offset, delay and current source variation effects described in Section II. Fig. 13 compares the temperature variation of the total period versus the variation of the positive phase of the oscillator. This shows the effectiveness of the offset cancellation technique (8) versus (9). Again, four chips are measured. The duration of each phase of the oscillator has a variation as large as ±7%. The improvement due to offset cancellation varies C. Allan Deviation Typically, Allan deviation measurements are carried out using specialized frequency counter equipment such as [26]. These have high accuracy, with Allan deviation noise floor as low as 1 ppb or 0.01 ppb at averaging time τ = 1 s. For this work, we implemented a custom FPGA-based setup to capture the frequency estimates for various averaging times τ, the f est terms in (10). A 48 MHz crystal oscillator-based frequency reference is used for frequency estimation. Fig. 15 shows the measured noise floor of the setup. The long term stability, at 30 ppb is determined by the crystal oscillator and is sufficient for the RC oscillator measurements to follow. The long-term Allan deviation of one of the chips is plotted in Fig. 16. For short averaging intervals, the white frequency noise process is apparent (τ 0.5 trend) while flicker frequency noise leads to flattening (τ 0 trend). For the full period (capturing offset cancellation) at averaging intervals τ>1s, the Allan deviation is better than 20 ppm. However, for just one phase of the oscillator, due to no offset cancellation, the flicker frequency noise flattens out at around 200 ppm. As discussed in Section II-D, the oscillator is more resilient to current source noise as well as comparator flicker noise, leading to the 10 improvement. Shorter-term Allan deviation measurements were performed for the four chips across temperature, from 0 Cto+90 C. Fig. 17 plots it for averaging interval of τ = 2s.Itshowsthat the Allan deviation stays below 35 ppm across the four chips and across the temperature range, indicating high accuracy timing measurements for wireless systems. Chip 3 in this plot

10 PAIDIMARRI et al.: AN RC OSCILLATOR WITH COMPARATOR OFFSET CANCELLATION 1875 TABLE I COMPARISON TO PREVIOUS FULLY INTEGRATED OSCILLATORS Fig. 16. Allan deviation for the oscillator with and without offset compensation shows that the circuit attenuates noise as well. Fig. 17. Allan measurements for four chips across temperature at τ = 2 s. shows relatively higher Allan deviation with respect to the other chips, due to larger sensitivity to temperature [Fig. 12(a)] and variations in the temperature chamber. D. Comparison Table I summarizes this work and compares it with previously published integrated oscillators. In addition to RC oscillators, also compared are alternate oscillator topologies that are referenced to electron mobility [27] and a ring oscillator with special biasing [9]. V. CONCLUSIONS In conclusion, an offset cancellation scheme has been presented that helps achieve temperature stability of ±0.18%, ultra-low power operation at 130 nw and long-term stability of better than 20 ppm, advancing the state of fully-integrated timers for wireless sensors. ACKNOWLEDGMENT The authors would like to acknowledge P. Roine and P. Nadeau for useful discussion, and J. Reid for skilled layout.

11 1876 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 8, AUGUST 2016 REFERENCES [1] P. P. Mercier, A. C. Lysaght, S. Bandyopadhyay, A. P. Chandrakasan, and K. M. Stankovic, Energy extraction from the biologic battery in the inner ear, Nature Biotechnol., vol. 30, no. 12, pp , [2] D. Griffith, Ultra-Low-Power Short-Range Radios, ser. Integrated Circuits and Systems, P. P. Mercier and A. P. Chandrakasan Eds. Switzerland: Springer International, 2015, pp , [Online]. Available: [3] D. Yoon, D. Sylvester, and D. Blaauw, A 5.58nW kHz DLLassisted XO for real-time clocks in wireless sensing applications, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2012, pp [4] D. Ruffieux et al., A versatile timing microsystem based on waferlevel packaged XTAL/BAW resonators with sub-μ W RTC mode and programmable HF clocks, IEEE J. Solid-State Circuits, vol. 49, no. 1, pp , Jan [5] IEEE Standard Definitions of Physical Quantities for Fundamental Frequency and Time Metrology Random Instabilities, IEEE Std Feb. 2008, C1 35. [6] D. Griffith, P. T. Roine, J. Murdock, and R. Smith, A 190nW 33 khz RC oscillator with ±0.21% temperature stability and 4 ppm long-term stability, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2014, pp [7] K.-J. Hsiao, A 32.4 ppm/ C V self-chopped relaxation oscillator with adaptive supply generation, in Symp. VLSI Circuits Dig., 2012, pp [8] Y. Lee, B. Giridhar, Z. Foo, D. Sylvester, and D. Blaauw, A 660 pw multi-stage temperature-compensated timer for ultra-low-power wireless sensor node synchronization, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2011, pp [9] A. Shrivastava and B. Calhoun, A 150 nw, 5 ppm/ C, 100 khz on-chip clock source for ultra low power SoCs, in Proc. IEEE Custom Integr. Circuits Conf. (CICC), 2012, pp [10] AM08X5 Real-Time Clock Family,Ambiq Micro, [11] Y. Lu, G. Yuan, L. Der, W.-H. Ki, and C. Yue, A ±0.5% precision onchip frequency reference with programmable switch array for crystal-less applications, IEEE Trans. Circuits Syst. II, vol. 60, no. 10, pp , Oct [12] V. De Smedt, P. D. Wit, W. Vereecken, and M. Steyaert, A 66 μw 86 ppm/ C fully-integrated 6 MHz Wienbridge oscillator with a 172 db phase noise FOM, IEEE J. Solid-State Circuits, vol. 44, no. 7, pp , Jul [13] Y. Tokunaga, S. Sakiyama, A. Matsumoto, and S. Dosho, An on-chip CMOS relaxation oscillator with voltage averaging feedback, IEEE J. Solid-State Circuits, vol. 45, no. 6, pp , Jun [14] K. Tsubaki, T. Hirose, N. Kuroki, and M. Numa, A khz, 472 nw, 120 ppm/ C, fully on-chip, variation tolerant CMOS relaxation oscillator for a real-time clock application, in Proc. IEEE Eur. Solid- State Circuits Conf. (ESSCIRC), 2013, pp [15] K. Choe, O. Bernal, D. Nuttman, and M. Je, A precision relaxation oscillator with a self-clocked offset-cancellation scheme for implantable biomedical SoCs, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2009, pp , 403a. [16] P. F. Geraedts, E. A. Tuijl, E. A. Klumperink, G. J. Wienk, and B. Nauta, Towards minimum achievable phase noise of relaxation oscillators, Int. J. Circuit Theory Applicat., vol. 42, no. 3, pp , [17] A. Paidimarri, D. Griffith, A. Wang, A. Chandrakasan, and G. Burra, A 120 nw 18.5 khz RC oscillator with comparator offset cancellation for ±0.25% temperature stability, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2013, pp [18] T. Tokairin et al., A 280 nw, 100 khz, 1-cycle start-up time, on-chip CMOS relaxation oscillator employing a feedforward period control scheme, in Symp. VLSI Circuits Dig., 2012, pp [19] K. Sundaresan, P. Allen, and F. Ayazi, Process and temperature compensation in a 7 MHz CMOS clock oscillator, IEEE J. Solid-State Circuits, vol. 41, no. 2, pp , Feb [20] Y.-S. Lin, D. M. Sylvester, and D. T. Blaauw, A 150 pw program-andhold timer for ultra-low-power sensor platforms, in IEEE Int. Solid- State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2009, pp [21] U. Denier, Analysis and design of an ultralow-power CMOS relaxation oscillator, IEEE Trans. Circuits Syst. I, vol. 57, no. 8, pp , [22] R. Navid, T. H. Lee, and R. W. Dutton, Minimum achievable phase noise of RC oscillators, IEEE J. Solid-State Circuits, vol. 40, no. 3, pp , Mar [23] P. P. Mercier, Communication and Energy Delivery Architectures for Personal Medical Devices, Ph.D. dissertation dissertation, Mass. Inst. Technol. (MIT), Cambridge, MA, USA, 2012, [Online]. Available: [24] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, Leakage current mechanisms and leakage reduction techniques in deepsubmicrometer CMOS circuits, Proc. IEEE, vol. 91, no. 2, pp , [25] S. Mandal, S. Arfin, and R. Sarpeshkar, Fast startup CMOS current references, in IEEE Int. Symp. Circuits Syst. (ISCAS), 2006, p. 4. [26] 53230A 350 MHz Universal Frequency Counter/Timer, 12 Digits/s, 20 ps, Keysight Technologies, [27] F. Sebastiano, L. Breems, K. Makinwa, S. Drago, D. Leenaerts, and B. Nauta, A low-voltage mobility-based frequency reference for crystal-less ULP radios, IEEE J. Solid-State Circuits, vol. 44, no. 7, pp , Jul [28] J. Lim, K. Lee, and K. Cho, Ultra low power RC oscillator for system wake-up using highly precise auto-calibration technique, in Proc. IEEE Eur. Solid-State Circuits Conf. (ESSCIRC), 2010, pp Arun Paidimarri (S 10 M 16) received the B.Tech. degree in electrical engineering from the Indian Institute of Technology, Bombay, India, in 2009, and the S.M. and Ph.D degrees in electrical engineering and computer science from the Massachusetts Institute of Technology (MIT), Cambridge, MA, USA, in 2011 and 2015, respectively. He is currently a postdoctoral associate in the Microsystems Technology Laboratories at MIT. His research interests are in low-power wireless system, including the design of RF circuits, protocols, timers and energy harvesting. From June 2011 to August 2011, he worked in the Low Power RF division in Texas Instruments, Dallas, TX, USA, designing low-power timer circuits. From June 2012 to August 2012, he worked on low-power PAs at Kilby Labs at Texas Instruments, Dallas. Dr. Paidimarri was a co-recipient of the Best Paper Award at the IEEE International Conference on Communications (ICC) He was awarded the President of India Gold Medal in He won a Silver Medal at the 37th International Chemistry Olympiad held in Taipei, Taiwan, in Danielle Griffith (M 97) received the B.S.E.E. and M.Eng. degrees from the Massachusetts Institute of Technology, Cambridge, MA, USA, in 1996 and 1997, respectively. She joined Motorola, Tempe, AZ, USA, in 1997 and worked in the area of RF circuit design. In 2003, she joined Texas Instruments, Dallas, TX, USA, and is currently a Distinguished Member of the Technical Staff in the Low Power RF group. She develops circuits and techniques for reducing cost, power consumption, and circuit board area for wireless connectivity products that support standards such as Bluetooth Low Energy and Zigbee. Her current focus areas are low-power oscillators and MEMS circuitry. She holds 11 U.S. patents. Alice Wang (M 97 SM 09) received the Bachelors, Masters, and Ph.D. degrees in electrical engineering and computer science from the Massachusetts Institute of Technology, Cambridge, MA, USA, in 1997, 1998, and 2004, respectively. She wrote the paper A 180-mV Subthreshold FFT Processor Using a Minimum Energy Design Methodology with Prof. A. Chandrakasan which inspired a new research field in ultra-low power technology. After her Ph.D., she spent 8 years at Texas Instruments developing low-power circuit and system technology for mobile, application processors and radios. Her work on low-power technology has been showcased in 30+ IEEE publications and she has co-authored two books. Currently, she is a Senior Director in High-Performance Processor Technology at MediaTek, Taiwan, working on advanced processors for consumer electronics including Smartphones, Tablets and Smart TVs. Dr. Wang also serves on the Technology Directions committee for the International Solid-State Circuits Conference. She is a long-time supporter of Sub-Vt research.

12 PAIDIMARRI et al.: AN RC OSCILLATOR WITH COMPARATOR OFFSET CANCELLATION 1877 Gangadhar Burra (M 93) received the Ph.D. degree in electrical engineering in He is a Senior Director of Technology at Qualcomm Inc., San Jose, CA, USA, since In this role, he is currently responsible for the system and circuit development for the next generation cellular and wireless LAN products. From 1999 to 2013 he was at Texas Instruments Inc., Dallas, TX, USA, where he served in many capacities including as the Chief Technologist for the wireless connectivity organization. He was a Senior Design Engineer at Analog Devices Inc. from 1993 to He has 10 issued patents. Dr. Burra served on the International Solid State Circuits program committee from 2009 to Anantha P. Chandrakasan (M 95 SM 01 F 04) received the B.S, M.S., and Ph.D. degrees in electrical engineering and computer sciences from the University of California, Berkeley, CA, USA, in 1989, 1990, and 1994, respectively. Since September 1994, he has been with the Massachusetts Institute of Technology (MIT), Cambridge, MA, USA, where he is currently the Vannevar Bush Professor of Electrical Engineering and Computer Science. He was the Director of the MIT Microsystems Technology Laboratories from 2006 to Since July 2011, he is the Head of the MIT EECS Department. He is a co-author of Low Power Digital CMOS Design (Kluwer Academic, 1995), Digital Integrated Circuits (Pearson Prentice-Hall, 2003, 2nd ed.), and Sub-threshold Design for Ultra-Low Power Systems (Springer, 2006). His research interests include ultra-low-power circuit and system design, energy harvesting, energy efficient RF circuits, and hardware security. Dr. Chandrakasan was a co-recipient of several awards including the 2007 ISSCC Beatrice Winner Award for Editorial Excellence and the ISSCC Jack Kilby Award for Outstanding Student Paper (2007, 2008, 2009). He received the 2009 Semiconductor Industry Association (SIA) University Researcher Award and the 2013 IEEE Donald O. Pederson Award in Solid- State Circuits. In 2015 he was elected to the National Academy of Engineering. He has served in various roles for the IEEE ISSCC including Program Chair, Signal Processing Sub-committee Chair, and Technology Directions Sub-committee Chair. He has been the Conference Chair of ISSCC since 2010.

13 本文献由 学霸图书馆 - 文献云下载 收集自网络, 仅供学习交流使用 学霸图书馆 ( 是一个 整合众多图书馆数据库资源, 提供一站式文献检索和下载服务 的 24 小时在线不限 IP 图书馆 图书馆致力于便利 促进学习与科研, 提供最强文献下载服务 图书馆导航 : 图书馆首页文献云下载图书馆入口外文数据库大全疑难文献辅助工具