Assembling EPC GaN Transistors

Transcription

1 Assembling EPC GaN Transistors EFFICIENT POWER CONVERSION Alana Nakata, Edgar Abdoulin, Jianjun Cao PhD, and Yanping Ma PhD, EPC Corporation Table of Contents 1. Overview of GaN Technology page 1. PCB Design Guide page 3 3. Quick Start Assembly Guide page 6 4. Die Storage Requirements page 8 5. Heatsinking page 8 6. Post Assembly Inspection page 8 7. Future Work page 9 8. Summary and Conclusions page 9 Appendix A: Low Cost Assembly Kit page 10 Appendix B: Step-by-Step Quick Start Assembly Process.. page 10 S G D GaN Si Fig 1: EPC s GaN Power Transistor Structure Top Layer Insulation Interlayer Insulation Metal Layer 3 AIGaN Protection Dielectric Two Dimensional Electron Gas (DEG) Aluminum Nitride Isolation Layer 1. Overview of Gallium Nitride (GaN) Technology In June 009 Efficient Power Conversion Corporation (EPC) introduced the first enhancement mode gallium nitride on silicon power transistors designed specifically as power MOSFET replacements. These products were developed to be produced in high volume at low cost using standard silicon manufacturing technology and facilities. The initial product family consists of 10 part numbers ranging from 40V to 00V and from 4 milliohms to 100 milliohms. Table 1 lists the devices and their basic characteristics. For more information about EPC s GaN transistors, go to www. epc-co.com. STRUCTURE A device s cost effectiveness starts with leveraging existing production infrastructure. EPC s process begins with silicon wafers. A thin layer of Aluminum Nitride (AlN) is grown on the Silicon to isolate the device structure from the substrate. The isolation between the substrate and the active device, for product with voltage ratings 00 V and below, is over 300 V. On top of this AlN, a thick layer of highly resistive GaN is grown. This layer provides a foundation on which to build the active transistor. An electron generating material comprised of Aluminum, Gallium, and Nitrogen (AlGaN) is applied on top of the GaN. This layer creates an abundance of free electrons just below it. Further processing forms a depletion region under the gate. To enhance the transistor, a positive voltage is applied to the gate in a similar manner to turning on an n-channel, enhancement mode power MOSFET. A cross section of this structure, repeated many times to form a complete power device, is depicted in figure 1. The end result is a fundamentally simple, cost effective solution for power switching 1. EPC s GaN transistors are lateral devices with all three terminals: gate, drain, and source, on the top side of the chip. The active device is isolated from the substrate and fully encapsulated by passivation layers. Generally, EPC devices have three layers of metal used to connect the active device to the outside world (fig ). The top metal layer is then used as a foundation for solder bumps as shown in Figure 3. This configuration allows EPC s GaN transistors to eliminate unnecessary elements of traditional power MOSFET packaging that contribute to higher inductance, thermal and electrical resistance, higher costs, and compromised reliability. Metal Layer Interlayer Insulation Metal Layer 1 S G Semi Insulating GaN (ugan) S I L I C O N S U B S T R AT E Figure : Device Construction D AIGaN Strain Layer AIN Isolation Layer SILICON COPPER TRACES Fig 3: Flip Chip Active GaN Device Region Solder Bumps PRINTED CIRCUIT BOARD Aluminum Nitride EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 010 PAGE 1

2 EPC TRANSISTOR CONFIGURATIONS As of March 010, EPC transistors come in four different layout configurations (fig 4,5,6,7, bottom view). All devices use eutectic lead solder, 63Sn/37Pb (Conversion to lead-free is scheduled for late 010). Bump height is 75 µm +/- 0 µm. All products are delivered in tape and reel for efficient and low cost assembly (Fig 8). Fig 4: EPC1001, EPC1005, EPC1015 Die and Solder Bump Layout, bottom view DIM MILLIMETERS MIN Nominal MAX A B c d e f g Fig 6: EPC1010, EPC1011 Die and Solder Bump Layout, bottom view DIM MILLIMETERS MIN Nominal MAX A B c d e f g Fig 5: EPC1007, EPC1009, EPC1014 Die and Solder Bump Layout, bottom view DIM MILLIMETERS MIN Nominal MAX A B c d e f g Fig 7: EPC101, EPC1013 Die and Solder Bump Layout, bottom view DIM MILLIMETERS MIN Nominal MAX A B c d e f g mm pitch, 8mm wide tape on 7 reel b d e f g Loaded Tape Feed Direction 7 reel a c Die orientation dot Gate Pad bump is under this corner Fig 8: Tape and Reel configuration EPC101 Dimension (mm) target min max a b c (see note) d e f (see note) g Die is placed into pocket bump side down (face side down) Note: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 010 PAGE

3 . Printed Circuit Board (PCB) Design Guide LAND PATTERN DESIGN Figure 9 shows the recommended land pattern design for EPC s products listed in Table 1. As an example, for EPC1001 transistors, pad no. 1 is gate, pads no. 3, 5, 7, 9, 11 are drain, and pad no., 4, 6, 8, and 10 are source (Pad number is recommended to pin out as source sense). For products with 50 µm wide solder bars, the land pad width is 00 µm. For products with 300 µm wide solder bars, the land pad width is 50 µm. Fig 9a: Recommended Land Pads for EPC1001, EPC1005, and EPC1015 (units in µm) Fig 9b: Recommended Land Pads for EPC1010 and EPC1011 (units in µm) Pads no. 3, 5, 7, 9, 11 are Drain; Pads no. 4, 6, 8, 10 are Source; Pad no. is source and is recommended to pin out as a source sense. Pads no. 3, 5, 7 are Drain; Pads no. 4, 6 are Source; Pad no. is source and is recommended to pin out as a source sense X X5 Fig 9c: Recommended Land Pads for EPC1007, EPC1009, and EPC1014 (units in µm) Fig 9d: Recommended Land Pads for EPC101 and EPC1013 (units in µm) Pads no. 3 and 5 are Drain; Pads no. and 4 are Source X3 05 Pad no. 3 is Drain; Pads no. and 4 are Source. 50 EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 010 PAGE 3

4 SOLDER MASK Non-solder-mask-defined (NSMD) land is preferred. NSMD provides a more accurate pattern registration than SMD (solder-mask-defined) which is required due to the fine pitch configuration. Furthermore, NSMD land allows solder to flow around the edges of the land, eliminating areas of stress concentrations, and potentially improving reliability. Figures 10 is the recommended solder mask opening dimensions for EPC products listed in Table 1. Units are in µm. SURFACE FINISH The commonly used pad-surface finishes are as follows: NiAu (electroless nickel immersion gold); OSP (organic solderability preservative); HASL (hot-air surface leveling); Immersion Ag (silver). EPC has no preference on the suitable surface finish for this package. Reliability tests were performed on NiAu finish. BOARD VIA EPC recommends OZ top layer Cu and through PCB vias just outside of the die area. A thick top and multi layer PCB (e.g., 4 layers or 6 layers), connected by vias just outside of the die area is important to minimize the resistance added by the PCB. Figure 11 shows the relative positions and dimensions of top layer Cu, board vias, and solder mask for EPC products listed in Table 1. Fig 10a: Recommended solder mask for EPC1001, EPC1005, EPC Fig 11a: Top trace(oz), EPC1001, EPC1005, EPC X5 Fig 10b: Recommended Solder Mask for EPC1010 and EPC1011 Pads no. 3, 5, 7, 9, 11 are Drain; Pads no. 4, 6, 8, 10 are Source; Pad no. is source and is recommended to pin out as a source sense. Fig 11b: Top trace(oz), EPC1001, EPC1005, EPC Pads no. 3, 5, 7, 9, 11 are Drain; Pads no., 4, 6, 8, 10 are Source. Fig 10c: Recommended Solder Mask for EPC1007, EPC1009, and EPC Fig 11c: Top trace(oz), EPC1001, EPC1005, EPC Fig 10d: Recommended Solder Mask for EPC101 and EPC1013 Pads no. 3, 5, 7, 9, 11 are Drain; Pads no., 4, 6, 8, 10 are Source; Pad no. is source and is recommended to pin out as a source sense. EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 010 PAGE 4

5 Fig 11d: Top trace(oz), EPC1010 and EPC FIDUCIALS Depending on the accuracy of the pick and place equipment, it may be necessary to have local fiducials. Local fiducials are typically placed diagonally outside of the die. Alignment legends can be used as visual indicators for good placement of the die on PCB. Such alignment legends can be copper features on the top layer, or solder mask features, or silkscreen features. STENCIL DESIGN The recommended stencil aperture designs are shown in Figure 1. The rectangular shaped apertures are larger than the land pads. The corners of the apertures are rounded at radius of 60 µm. The recommended stencil foil thickness is 100 µm. Pads no. 3, 5, 7 are Drain; Pads no., 4, 6 are Source; Fig 11e: Top trace(oz), EPC1007, EPC1009, and EPC Fig 1a: Recommended Stencil Aperture Design for EPC1001, EPC1005, EPC1015 (units in µm) Pads no. 3 and 5 are Drain; Pads no. and 4 are Source X5 Fig 1b: Recommended Stencil Aperture Design for EPC1010 and EPC1011 Fig 11f: Top trace(oz), EPC101 and EPC Fig 1c: Recommended Stencil for EPC1007, EPC1009, and EPC Pad no. 3 is Drain; Pads no. and 4 are Source. Fig 1d: Recommended Stencil for EPC101 and EPC EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 010 PAGE 5

6 SOLDER PASTE AND SOLDER PASTE PRINTING Eutectic SnPb solder (63Sn- 37Pb) is used with particle size of either Type 4 or Type 3. The solder paste typically contains about 50% of solder and 50% of flux by volume. EPC recommends that solder pastes with a no-clean flux be used. Reflow Profile Solder paste printing is accomplished by stenciling solder paste onto the PCB land pads. Alignment of the aperture to the pad is recommended to be 50 µm or less, however, the solder paste realigns with the land pad during reflow. As a result, the alignment of the solder paste to the land pad is not very critical. Temperature ( C) Assembly House Profile Flux Vendor Profile Die Solder bump 675 ± Time (Seconds) ± 0 Fig 15: Reflow profile from Kester Datasheet for TSF 650 overlaid with assembly house profile PCB Copper trace Stencil printed solder paste Solder mask Fig 16: Tacky Flux assembly process [Pictures courtesy of Promex-Industries] Fig 13: Schematic cross-sectional view of a die placed on a PCB with a stencil-printed solder paste DIE PLACEMENT EPC recommends that misalignment of bumps on the die to the land pads on the PCB be 50 µm or less. However, the surface tension of the molten solder will self-align the die to the land pads. Misalignment up to 100 µm during placement of the die on the PCB is tolerable. It is advisable not to correct a placement offset. This can smear the paste underneath, and can lead to bridging and solder balling. Figure 13 illustrates a die placement prior to reflow. 3. Quick-Start Assembly Guidelines GaN users can generally apply standard surface mount techniques to successfully attach EPC s GaN transistors onto standard PCBs. Below are two techniques that have demonstrated reliable and high yielding results; a tacky flux process, and a solder stencil process. TACKY FLUX PROCESS EPC s GaN transistors can be mounted directly onto PC boards without added solder by using a tacky flux to hold the part in place while reflowing the solder on the die (fig 14). An example Die Solder bump of an acceptable process uses Kester TSF650 no-rinse flux. The reflow profile used by EPC to assemble product used in the Application Readiness Review 3 is shown in figure 15 compared with the manufacturer s recommended profile. Figure 16 is an X-Ray image of a mounted device on FR408 PCB material using the temperature profile of figure 15. SOLDER STENCIL PROCESS Many high volume assembly processes involve using a solder stencil mask to apply additional solder to the PCB prior to mounting devices (fig 13). This is recommended in order to insure adequate die standoff distance following reflow when die are mounted onto a PCB with a solder mask. A recommended reflow temperature profile is shown in figure 17 and an X-Ray of the resulting die mounted on the PCB is shown in figure 18. Fig 17 and 18: Solder Stencil Process [Pictures courtesy of Promex-Industries] Temperature ( C) Reflow Profile PCB Copper trace Solder mask Tacky flux Fig 14: Schematic cross-sectional view of a die placed on a PCB with tacky flux Time (Seconds) EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 010 PAGE 6

7 APPLICATION NOTE 0a: Soldering/de-soldering time-temperature profile Fig 0b: X-Ray of a part assembled using the profile in figure 0a [X-Ray Photos courtesy of EAG] Fig 0c (below left and right): X-Ray and Optical of part assembled using a too long time temp profile Fig 19a and 19b: Low volume die mounting apparatus SIMPLE, LOW-VOLUME ASSEMBLY EQUIPMENT EPC GaN transistors are extremely small when compared with silicon power MOSFETs of similar current handling capability. This can pose a challenge to designers wanting to quickly produce experimental or prototype circuits. EPC s applications group has been successful in using a simple two-station setup for mounting individual die on PCBs as shown in figure 19 (a) and (b). The system consists of an XYZ-θ table with a vacuum pump for aligning and installing the die on the board and a separate hot air station to solder the die (For a full list of equipment, see Appendix A). The use of tacky flux enables the board to be moved from one station to another without loss of alignment. Best results are obtained when the board is at room temperature prior to applying the flux; this preserves the tackiness of the flux and prevents the die from shifting while being transferred from one station to another. The process begins by applying a small amount of flux on the die footprint area, and then continues with aligning and installing the die on the XYZ-θ table. The soldering profile shown in figure 0 (a) has proven to be an adequate starting point to obtain a good solder joint as can be seen from the X-Ray and optical images in figure 0 (b). Ambient temperature and other factors in a specific lab setting might cause minor adjustments to the time and temperature setting to be required. Figure 0(c) shows the X-Ray and optical result of a part that used the same temperature profile as the part in 0(b), but was reflowed for almost double the time. The result is too much reflow, and the solder is now seen to be flowing out from under the die. Depending on how much solder flows out, this could cause a bridge between terminals and therefore an electrical short. Preheating the boards is a must. Whereas the amount of preheat will depend on the type of board used, maintaining a PCB surface temperature of about 100 C prior to beginning the soldering sequence has proven to be an adequate condition to ensure a proper solder joint regardless of copper content or thickness. Appendix B is a basic step-by step process successfully used by EPC s applications group. As always, experimenting with various settings is a good practice to find an optimum solution. DIE REMOVAL De-soldering the EPC die from the boards is an easier process. Again, the preheat step is important to bring the solder to a melting point to remove the die. The die can be removed using a pair of fine tweezers when the solder is re-flowed in zone one or two. There is no need to apply additional flux prior to removal. A cleaning/solder wicking step following the removal will assist in achieving a flat surface for subsequent die mounts. EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 010 PAGE 7

8 4 APPLICATION NOTE UNDERFILL CONSIDERATIONS EPC has tested parts with both underfill and no-undefill with no measured difference in performance or reliability. In figure 1 we show reliability tests under high voltage and high humidity conditions. All groups show good results after 1000 hours of stress. Additional stress testing was done with reduced separation between gatesource and drain terminals without underfill. Experimental parts with 100 um gaps between all terminals were put on stress at 00V (Production 00V product from EPC has a 300um gap between terminals). Results shown in figure demonstrate that, even under stresses as high as V/ um, devices without underfill do not degrade after 1000 hrs. Underfill may still be warranted if the users manufacturing process may expose the GaN transistors to contamination after mounting. EPC has successfully applied two underfill materials during product development and during demo-board manufacture. 1. Loctite FP4549Si 9. Zymet CN Die Storage Requirements EPC s GaN transistors are packed in nitrogen purged, vacuum sealed antistatic bags including desiccant packs 4. Devices in sealed, unopened bags have a shelf life in excess of two years. Once a bag is opened, its contents should be treated as Moisture Sensitivity Level (MSL) 3 to guarantee good solderability. 5. Heatsinking EPC s GaN transistors are able to conduct significantly higher current than similarly-sized power MOSFETs. In general, the lower on-resistance and lower temperature coefficient of that on-resistance 5 make additional heatsinking unnecessary. If, however, even greater power density is desired, heatsinks can be attached directly to the back of the GaN device as per figure 3. To avoid mechanically damaging the devices, it is recommended that a thermal pad be used between the device and the heatsink such as 3M thermally conductive interface pads 6, Dow Corning thermal interface pads and films 7, or Bergquist Gap Pads 8 6. Inspection EPC s GaN transistors are mechanically robust and have demonstrated high yield in volume assembly. Damage, however, can still occur if several standard precautions are not taken to insure adequate solder reflow, reduce excessive die tilt, and avoid residual solder flux. ADEQUATE SOLDER REFLOW As with all chip scale packaging, the best way to determine if devices are properly reflowed is by taking X-ray images. Figures 16 and 18 show X-ray images of parts assembled with tacky flux (no added solder) and with a solder stencil process. EPC found that the solder stencil process typically yields less voiding, but both processes can be used to produce a reliable product based on EPC s reliability testing. 100 V (µa) 100 V (µa) HTRB, Underfill vs. No-underfill Stress Hour THB, Underfill vs. No-underfill Stress Hour Fig 1: HTRB and THB comparing underfilled parts with no-underfill parts 00 V (µa) HTRB, 00 V Drain Bias, 100 µm Solder Spacing Stress Hour Fig : HTRB tests with 100uM terminal spacing and no underfill Heat Sink Thermal Pad EPC GaN Die PCB Figure 3: GaN devices mounted on a PCB with heatsink directly attached EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 010 PAGE 8

9 4 APPLICATION NOTE DIE TILT AND DENDRITES During EPC s product testing and assembly process development, several parts were observed to be tilted after reflow using a solder stencil process (figure 4). Three causes of die tilt were found; (1) uneven thickness of solder paste, () excessive vibration during reflow, and (3) non-optimized temperature profile. If the assembly process uses a solder with a flux that requires rinsing, die tilt can obstruct the flow of the rinse and cause flux to be trapped under the die. This residual flux can cause rapid formation of dendrites (figure 5) which will cause early device failure. For this reason, EPC recommends using a no rinse solder flux with low ionic content. 7. Future Work Tilted Die PCB PLANE Trapped flux residue coming up the side of die Fig 4: Die Tilt EPC will be converting to a lead free solder system in the second half of 010. In addition to full qualification of the new system, an update of preferred assembly conditions will be published. EPC s reliability testing continues. Phase One testing is complete 3 and Phase Two testing is scheduled to be published in May 010. In Phase Three, scheduled for September 010, EPC will have reliability data for lead free product. 8. Summary and Conclusions EPC s enhancement mode GaN transistors give the power conversion designer a whole new spectrum of capabilities unachievable with siliconbased power MOSFETs. The intrinsic low conduction losses and high frequency capability are complimented by the ability of GaN-on-silicon to be assembled without additional packaging. The assembly technology required is not significantly more demanding than the technology already in place for LGA, chipscale, and high-density SO packages. Figure 5: Solder dendrites after exposure to non-reflowed solder flux Table 1 Single Part Number Package (mm) Mode Ch V DS V GS Max. R DS(ON) 5V Q 5V Q GS Typ. Q GD Typ. V TH Typ. Q RR I D EPC1014 LGA 1.7 x 1.1 EN EPC1015 LGA 4.1 x 1.6 EN EPC1009 LGA 1.7 x 1.1 EN EPC1005 LGA 4.1 x 1.6 EN EPC1007 LGA 1.7 x 1.1 EN EPC1001 LGA 4.1 x 1.6 EN EPC1013 LGA 1.7 x 0.9 EN EPC1011 LGA 3.6 x 1.6 EN EPC101 LGA 1.7 x 0.9 EN EPC1010 LGA 3.6 x 1.6 EN EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 010 PAGE 9

10 4 APPLICATION NOTE Appendix A: Low Cost Die Mount Apparatus for EPC GaN Transistors Pick and Place Station With Vacuum Pump: XYZ Table with Vacuum pump: Madell Technologies CCD Camera : Swann Security Model HD-40 LCD Display: Swann Security Compact 8 LCD Monitor P/N SW48-LM8 LED Flex Lights: Coast Products Model Soldering/De-soldering Station: Soldering station: HAKKO USA Model FR-803B Re-work fixture: HAKKO USA Model C139B Board Pre-preheater : HAKKO USA Model FR-80 Panavise rapid assembly circuit board holder Model Appendix B: Die Mount Process for Low Volume Assembly of EPC GaN Transistors To solder: Apply a drop of Kester Tacky Flux (TSF-650/65) to die area with an appropriate syringe. Always apply flux with board at room temperature! Secure board on pick and place table. With vacuum on, align die over the footprint between alignment marks, then lower die to contact the board and turn off vacuum to release die. Carefully move board to soldering station. Use time/temperature profile in fig 0(a) to solder die. To de-solder: Install board in soldering station, start soldering profile, remove die at stage three with a pair of fine tweezers. Note: Board preheat settings depend on type of board used With Pre-heater ~1 below area of board to be soldered: For ~4 layer boards (1or oz copper) Use pre-heat setting of 150~00oC. For 4~8 layer boards ( oz copper) Use pre-heat setting of 00~50oC. EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 010 PAGE10

11 4 APPLICATION NOTE REFERENCES [1] Steve Colino and Robert Beach, Fundamentals of Gallium Nitride Power Transistors, [] [3] Yanping Ma, EPC GaN Transistor Application Readiness: Phase One Testing, [4] Dessi Pak dessicant packs, Sud-Chemie, [5] Alex Lidow, Is it the End of the Road for Silicon?, [6] 3M pads : [7] Dow Corning Pads: [8] Bergquist Pads: [9] [10] EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 010 PAGE 11