EPC2007C Enhancement Mode Power Transistor

Transcription

1 EPC7C EPC7C Enhancement Mode Power Transistor V DSS, V R DS(on), 3 mw I D, 6 A NEW PRODUCT EFFICIENT POWER CONVERSION HAL Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment leveraging the infrastructure that has been developed over the last years. GaN s exceptionally high electron mobility and low temperature coefficient allows very low R DS(on), while its lateral device structure and majority carrier diode provide exceptionally low Q G and zero Q RR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. Maximum Ratings V DS Drain-to-Source Voltage (Continuous) V Continuous (T A = C, R θja = 6 C/W) 6 I D Pulsed ( C, T Pulse = 3 µs) 4 Gate-to-Source Voltage 6 V GS Gate-to-Source Voltage -4 T J Operating Temperature -4 to T STG Storage Temperature -4 to A V C EPC7C egan FETs are supplied only in passivated die form with solder bumps Applications High Speed DC-DC conversion Class-D Audio High Frequency Hard-Switching and Soft-Switching Circuits Benefits Ultra High Efficiency Ultra Low R DS(on) Ultra low Q G Ultra small footprint Static Characteristics (T J = C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BV DSS Drain-to-Source Voltage V GS = V, I D = 7 µa V I DSS Drain Source Leakage V DS = 8 V, V GS = V 6 µa Gate-to-Source Forward Leakage V GS = V. ma I GSS Gate-to-Source Reverse Leakage V GS = -4 V 6 µa V GS(TH) Gate Threshold Voltage V DS = V GS, I D =. ma.8.4. V R DS(on) Drain-Source On Resistance V GS = V, 4 3 mω V SD Source-Drain Forward Voltage I S =. A, V GS = V. V All measurements were done with substrate shorted to source. Thermal Characteristics R θjc Thermal Resistance, Junction to Case 3.6 C/W R θjb Thermal Resistance, Junction to Board 9.3 C/W R θja Thermal Resistance, Junction to Ambient (Note ) 8 C/W Note : R θja is determined with the device mounted on one square inch of copper pad, single layer oz copper on FR4 board. See for details. TYP UNIT EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT PAGE

2 EPC7C Dynamic Characteristics (T J = C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT C ISS Input Capacitance 7 C OSS Output Capacitance V DS = V, V GS = V 6 pf C RSS Reverse Transfer Capacitance.9.7 R G Gate Resistance.4 Ω Q G Total Gate Charge V DS = V, V GS = V,.6. Q GS Gate-to-Source Charge.6 Q GD Q G(TH) Gate-to-Drain Charge V DS = V,.3 Gate Charge at Threshold.4 Q OSS Output Charge V DS = V, V = V 8.3 Q RR Source-Drain Recovery Charge All measurements were done with substrate shorted to source. GS.6 nc. 4 Figure : Typical Output Characteristics at C 4 Figure : Transfer Characteristics ID Drain Current (A) 3 3 V GS = V V GS = 4 V V GS = 3 V V GS = V ID Drain Current (A) 3 3 C C V DS = 3 V V DS Drain-to-Source Voltage (V) Figure 3: R DS(on) vs. V GS for Various Drain Currents Figure 4: R DS(on) vs. V GS for Various Temperatures RDS(on) Drain-to-Source Resistance (mω) I D = 3 A I D = 9 A I D = A RDS(on) Drain-to-Source Resistance (mω) C C EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT PAGE

3 EPC7C 3 Figure a: Capacitance (Linear Scale) Figure b: Capacitance (Log Scale) Capacitance (pf) Capacitance (pf) C OSS = C GD + C SD C ISS = C GD + C GS C RSS = C GD C OSS = C GD + C SD C ISS = C GD + C GS C RSS = C GD V DS Drain-to-Source Voltage (V) V DS Drain-to-Source Voltage (V) Figure 6: Gate Charge 4 Figure 7: Reverse Drain-Source Characteristics VGS Gate-to-Source Voltage (V) 4 3 V DS = V ISD Source-to-Drain Current (A) 3 3 C C.... Q G Gate Charge (nc) V SD Source-to-Drain Voltage (V). Figure 8: Normalized On-State Resistance vs. Temperature.4 Figure 9: Normalized Threshold Voltage vs. Temperature Normalized On-State Resistance RDS(on) V GS = V Normalized Threshold Voltage I D =. ma.8 7 T J Junction Temperature ( C).6 7 T J Junction Temperature ( C) All measurements were done with substrate shortened to source. EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT PAGE 3

4 EPC7C 6 Figure : Gate Leakage Current IG Gate Current (ma) 4 3 C C Figure : Transient Thermal Response Curves ZθJB, Normalized Thermal Impedance.. Duty Cycle:..... Junction-to-Board t p, Rectangular Pulse Duration, seconds P DM t t Notes: Duty Factor: D = t /t Peak T J = P DM x Z θjb x R θjb +T B Single Pulse ZθJC, Normalized Thermal Impedance Duty Cycle: Single Pulse Junction-to-Case t p, Rectangular Pulse Duration, seconds P DM t t Notes: Duty Factor: D = t /t Peak T J = P DM x Z θjc x R θjc + T C EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT PAGE 4

5 EPC7C Figure : Safe Operating Area ID Drain Current (A) Pulse Width ms ms ms µs Limited by R DS(on) T J = Max Rated, T C = + C, Single Pulse.. V DS Drain Voltage (V) µs ms ms ms TAPE AND REEL CONFIGURATION 4mm pitch, 8mm wide tape on 7 reel b d e f g Loaded Tape Feed Direction 7 reel a c Die orientation dot Gate solder bar is under this corner EPC7C (note ) Dimension (mm) target min max a b c (see note) d e f (see note)..9. g...6 Die is placed into pocket solder bar side down (face side down) Note : MSL (moisture sensitivity level ) classified according to IPC/JEDEC industry standard. Note : Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS 7 Die orientation dot Gate Pad bump is under this corner YYYY ZZZZ Part Number Part # Marking Line Laser Markings Lot_Date Code Marking line Lot_Date Code Marking Line 3 EPC7C 7 YYYY ZZZZ EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT PAGE

6 EPC7C DIE OUTLINE Solder Bar View c d X f A f X3 3 4 B DIM MICROMETERS MIN Nominal MAX A B c d e 3 6 f 9 g Side View e g g X 8 Max +/- (68) SEATING PLANE RECOMMENDED LAND PATTERN (measurements in µm) The land pattern is solder mask defined Solder mask is µm smaller per side than bump Pad no. is Gate Pad no. is Substrate Pad no. 3 and are Drain Pad no. 4 is Source X X3 For assembly recommendations please visit Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. egan is a registered trademark of Efficient Power Conversion Corporation. U.S. Patents 8,3,94; 8,44,8; 8,43,96; 8,436,398 Information subject to change without notice. revised January, EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT PAGE 6