EPC2107 Enhancement-Mode GaN Power Transistor Half-Bridge with Integrated Synchronous Bootstrap

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1 EPC7 Enhancement-Mode GaN Power Transistor Half-Bridge with Integrated Synchronous Bootstrap V DSS, V R DS(on), 9 m I D,.7 A EFFICIENT POWER CONVERSION HAL EPC7 Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment leveraging the infrastructure that has been developed over the last 6 years. GaN s exceptionally high electron mobility and low temperature coefficient allows very low R DS(on), while its lateral device structure and majority carrier diode provide exceptionally low Q G and zero Q RR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. Maximum Ratings DEVICE PARAMETER VALUE UNIT Q & Q Q VDS ID VGS Drain-to-Source Voltage (Continuous) Drain-to-Source Voltage (up to, 5 ms pulses at 5 C) Continuous (TA = 5 C, RθJA = 6 C/W).7 Pulsed (5 C, TPULSE = µs).8 Gate-to-Source Voltage 6 Gate-to-Source Voltage TJ Operating Temperature to 5 TSTG Storage Temperature to 5 VDS ID Drain-to-Source Voltage (Continuous) Drain-to-Source Voltage (up to, 5 ms pulses at 5 C) Continuous (TA = 5 C, RθJA = C/W).5 Pulsed (5 C, TPULSE = µs).5 VGS Gate-to-Source Voltage 6 V TJ Operating Temperature to 5 TSTG Storage Temperature to 5 V A V C V A C EPC7 egan ICs are supplied only in passivated die form with solder bumps Die Size:.5 mm x.5 mm Applications High Frequency DC-DC Conversion Class-D Audio Wireless Power (Highly Resonant and Inductive) Benefits Ultra High Efficiency Ultra Low R DS(on) Ultra Low Q G Ultra Small Footprint Thermal Characteristics PARAMETER TYP UNIT D BTST G upper Positive 6 7 RJC Thermal Resistance, Junction-to-Case 6 RJB Thermal Resistance, Junction-to-Board RJA Thermal Resistance, Junction-to-Ambient (Note ) 8 C/W S BTST 9 Q Q 5 Out Out Note : RθJA is determined with the device mounted on one square inch of copper pad, single layer oz copper on FR board. See for details D Grev G BTST Q G lower 8 Ground EPC7 Detailed Schematic EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 7

2 EPC7 Static Characteristics DEVICE PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BVDSS Drain-to-Source Voltage VGS = V, ID =. ma V IDSS Drain-Source Leakage VDS = 8 V, VGS = V.5.5 ma Gate-to-Source Forward Leakage VGS = 5 V. ma IGSS Q & Q Gate-to-Source Reverse Leakage VGS = - V.5.5 ma VGS(TH) Gate Threshold Voltage VDS = VGS, ID =. ma V RDS(on) Drain-Source On Resistance VGS = 5 V, ID = A 5 9 mω VSD Source-Drain Forward Voltage IS =.5 A, VGS = V.5 V BVDSS Drain-to-Source Voltage VGS = V, ID =.5 ma V IDSS Drain Source Leakage VDS = 8 V, VGS = V.. ma IGSS Gate-to-Source Forward Leakage VGS = 5 V. ma Q VF Source-Gate Forward Voltage IF =. ma, VDS = V.7 V VGS(TH) Gate Threshold Voltage VDS = VGS, ID =. ma V RDS(on) Drain-Source On Resistance VGS = 5 V, ID =.5 A mω VSD Source-Drain Forward Voltage IS =. A, VGS = V.9 V Dynamic Characteristics DEVICE PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CISS Input Capacitance 5 CRSS Reverse Transfer Capacitance VDS = 5 V, VGS = V. COSS Output Capacitance 9. pf COSS(ER) Effective Output Capacitance, Energy Related (Note ) VDS = to 5 V, VGS = V COSS(TR) Effective Output Capacitance, Time Related (Note ) 8 Q RG Gate Resistance.7 Ω QG Total Gate Charge VDS = 5 V, VGS = 5 V, ID = A 9 QGS Gate-to-Source Charge 77 QGD Gate-to-Drain Charge VDS = 5 V, ID = A QG(TH) Gate Charge at Threshold 9 pc QOSS Output Charge VDS = 5 V, VGS = V 9 5 QRR Source-Drain Recovery Charge CISS Input Capacitance 5 CRSS Reverse Transfer Capacitance VDS = 5 V, VGS = V. COSS Output Capacitance pf COSS(ER) Effective Output Capacitance, Energy Related (Note ) 9 VDS = to 5 V, VGS = V COSS(TR) Effective Output Capacitance, Time Related (Note ) 5 Q RG Gate Resistance.7 Ω QG Total Gate Charge VDS = 5 V, VGS = 5 V, ID = A 9 QGS Gate-to-Source Charge 77 QGD Gate-to-Drain Charge VDS = 5 V, ID = A QG(TH) Gate Charge at Threshold 9 pc QOSS Output Charge VDS = 5 V, VGS = V QRR Source-Drain Recovery Charge CISS Input Capacitance 7 8. CRSS Reverse Transfer Capacitance VDS = 5 V, VGS = V. COSS Output Capacitance.6. pf COSS(ER) Effective Output Capacitance, Energy Related (Note ). VDS = to 5 V, VGS = V COSS(TR) Effective Output Capacitance, Time Related (Note ).7 Q RG Gate Resistance.8 Ω QG Total Gate Charge VDS = 5 V, VGS = 5 V, ID =.5 A 55 QGS Gate-to-Source Charge QGD Gate-to-Drain Charge VDS = 5 V, ID =.5 A QG(TH) Gate Charge at Threshold 8 pc QOSS Output Charge VDS = 5 V, VGS = V QRR Source-Drain Recovery Charge Note : COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from to 5% BVDSS. Note : COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from to 5% BVDSS. EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 7

3 EPC7 Figure a (Q & Q): Typical Output Characteristics at 5 C.5 Figure b (Q): Typical Output Characteristics at 5 C V GS = 5 V I D Drain Current (A) V GS = V V GS = V V GS = V I D Drain Current (A).... V GS = 5 V V GS = V V GS = V V GS = V Figure a (Q & Q): Transfer Characteristics.5 Figure b (Q): Transfer Characteristics 5 C 5 C. 5 C 5 C I D Drain Current (A) V DS = V I D Drain Current (A).. V DS = V R DS(on) Drain-to-Source Resistance (mω) Figure a (Q & Q): R DS(on) vs. V GS for Various Drain Currents I D =. A I D =.5 A I D =. A I D =.5 A R DS(on) Drain-to-Source Resistance (mω) 8 6 Figure b (Q): R DS(on) vs. V GS for Various Drain Currents I D =.5 A I D =. A I D =.5 A I D =. A EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 7

4 EPC7 Figure a (Q & Q): R DS(on) vs. V GS for Various Temperatures 8 Figure b (Q): R DS(on) vs. V GS for Various Temperatures R DS(on) Drain-to-Source Resistance (mω) C 5 C I D = A R DS(on) Drain-to-Source Resistance (mω) 6 5 C 5 C I D =.5 A Figure 5a (Q): Capacitance (Linear Scale) Figure 5b (Q): Capacitance (Log Scale) Figure 5c (Q): Capacitance (Linear Scale) Figure 5d (Q): Capacitance (Log Scale) EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 7

5 EPC7 8 Figure 5e (Q): Capacitance (Linear Scale) Figure 5f (Q): Capacitance (Log Scale) Figure 6a: (Q): Output Output Charge Charge and Cand OSS Stored C OSS Stored Energy Energy 5. Figure 6a: 6b (Q): Output Output Charge Charge and Cand OSS Stored C OSS Stored Energy Energy 7 Q OSS Output Charge (nc) E OSS C OSS Stored Energy (μj) Q OSS Output Charge (nc) E OSS C OSS Stored Energy (μj) Figure 6a: 6c (Q): Output Output Charge Charge and and C OSS Stored C OSS Stored Energy Energy Q OSS Output Charge (nc) E OSS C OSS Stored Energy (μj). 6 8 EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 7 5

6 EPC7 5 Figure 7a (Q & Q): Gate Charge 5 Figure 7b (Q): Gate Charge I D = A V DS = 5 V I D =.5 A V DS = 5 V 5 5 Q G Gate Charge (pc) 5 Q G Gate Charge (pc) Figure 8a (Q & Q): Reverse Drain-Source Characteristics.5 Figure 8b (Q): Reverse Drain-Source Characteristics I SD Source-to-Drain Current (A) 5 C 5 C V DS GS = V I SD Source-to-Drain Current (A) C 5 C V DS GS = V V SD Source-to-Drain Voltage (V) V SD Source-to-Drain Voltage (V). Figure 9a (Q & Q): Normalized On-State Resistance vs. Temperature. Figure 9b (Q): Normalized On-State Resistance vs. Temperature Normalized On-State Resistance R DS(on) I D = A V GS = 5 V Normalized On-State Resistance R DS(on) I D =.5 A V GS = 5 V T J Junction Temperature ( C) T J Junction Temperature ( C) EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 7 6

7 EPC7.. Figure a (Q & Q): Normalized Threshold Voltage vs. Temperature.. Figure b (Q): Normalized Threshold Voltage vs. Temperature Normalized Threshold Voltage I D =. ma Normalized Threshold Voltage I D =. ma T J Junction Temperature ( C) T J Junction Temperature ( C) Figure a Transient Thermal Response Curves ZθJB, Normalized Thermal Impedance Duty Cycle: Single Pulse (Q/Q/Q) Junction-to-Board t p, Rectangular Pulse Duration, seconds P DM t t Notes: Duty Factor: Single D = Pulse t /t Peak T J = P DM x Z θjb x R θjb + T B Figure b Transient Thermal Response Curves ZθJC, Normalized Thermal Impedance P (Q/Q/Q) Junction-to-Case Duty Cycle: DM. t. t Single Pulse Notes: Duty Factor: D = t /t Peak T J = P DM x Z θjc x R θjc + T C t p, Rectangular Pulse Duration, seconds EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 7 7

8 EPC7 I D Drain Current (A) Figure (Q & Q): Safe Operating Area Limited by R DS(on) Pulse Width ms ms µs ms 5 µs µs 5 µs.. V DS Drain-Source Voltage (V) T J = Max Rated, T C = +5 C, Single Pulse I G Gate Current (ma) Figure (Q): Gate-Source Characteristics 5 C 5 C Figure : Typical Application Circuit 5 V Q Q Level Shift Output C Bus Q Gate Driver EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 7 8

9 EPC7 TAPE AND REEL CONFIGURATION mm pitch, 8mm wide tape on 7 reel b d e f g Loaded Tape Feed Direction 7 reel a c 7 YYYY ZZZZ Die orientation dot Pin is under this corner EPC7 (note ) Dimension (mm) target min max a b c (see note) d..9. e..9. f (see note) g Die is placed into pocket solder bump side down (face side down) Note : MSL (moisture sensitivity level ) classified according to IPC/JEDEC industry standard. Note : Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS Die orientation dot Pin is under this corner 7 YYYY ZZZZ Part Number Part # Marking Line Laser Markings Lot_Date Code Marking Line Lot_Date Code Marking Line EPC7 7 YYYY ZZZZ EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 7 9

10 EPC7 DIE OUTLINE Solder Bump View B A d c c d c c Pad is Gate (Q) Pad is Gate (Q) Pad is Gate (Q) Pad 7 is Drain (Q) Pad 5 is Drain (Q) Pad 6 is Drain (Q) Pad is Source (Q) Pad 8 is Source (Q) Pad 9 is Source (Q) DIM MIN Nominal MAX A 5 8 B 5 8 c d 5 e Side View (65) 85 Max Seating plane 65 +/- 7 RECOMMENDED LAND PATTERN (measurements in µm) X The land pattern is solder mask defined Solder mask is μm smaller per side than bump Pad is Gate (Q) Pad is Gate (Q) Pad is Gate (Q) Pad 7 is Drain (Q) Pad 5 is Drain (Q) Pad 6 is Drain (Q) Pad is Source (Q) Pad 8 is Source (Q) Pad 9 is Source (Q) RECOMMENDED STENCIL DRAWING (measurements in µm) 5 Recommended stencil should be mil ( µm) thick, must be laser cut, openings per drawing Intended for use with SAC5 Type solder, reference 88.5% metals content. Additional assembly resources available at Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. egan is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/aboutepc/patents.aspx Information subject to change without notice. Revised July, 7 EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 7