Exponential Step-up/Step-down Type Switched-Capacitor Power Supply with Variable Conversion Ratio

Transcription

1 WSEAS TRANSATIONS on IRUITS and SYSTEMS Exponential Step-up/Step-down Type Switched-apacitor Power Supply with Variable onversion Ratio Tomoya IWANAGA, Shinya TERADA, ei EGUHI, and Ichirou OOTA Department of Information, ommunication and Electronic Engineering Department of ontrol and Information Systems Engineering National Institute of Technology, umamoto ollege 659-, Suya, oushi, umamoto 86-0, apan Department of Information Electronic Fukuoka Institute of Technology -0- Wajirohigashi, Higashi-u, Fukuoka 8-095, apan Abstract: - In this paper, a switched-capacitor(s) power supply which can obtain exponential conversion ratios is proposed ( and are integer). The conversion ratio can be varied between - and + by shifting the clock phase of each switch. oncerning the general proposed circuit, the ideal step-up ratio is analyzed changing and at no-load, and HSPIE simulations are performed under the = and = types. As a result, () at noload, = type can obtain the highest step-up voltage ratio with the same number of elements, () under the load, = type can obtain the highest power conversion efficiency with the same chip-size and the same turn-on/turnoff time of each switch. Furthermore, the inrush current can be decreased by changing conversion ratio at startup. ey-words: - switched-capacitor power supply, exponential step-up/step-down, D-D converter, small-sized and lightweight, inrush current Introduction An existing power conversion circuit converts an input voltage into a high frequency rectangular wave (or a sinusoidal wave, only resonance converter) by a switching circuit, and outputs using a smoothing L circuit. The output voltage is regulated by controlling a duty ratio or a switching frequency of the switching circuit. Although this method is obtained a high power conversion efficiency, deleterious magnetic flux is generated since a high frequency current flows in a magnetic component such as an inductor or a transformer. It is difficult to block the magnetic flux by a shield. Therefore, the power supply and a signal processing circuit needs to be spaced apart slightly for preventing the noise. On the other hand, switchedcapacitor(s) power supplies do not contain any magnetic component and convert an input voltage by changing the connections of capacitors at high speed. The first S power supply is presented in 9 as the ockcroft-walton circuit (W) for a high-voltage generator of a nuclear reaction experiment device[]. Until semiconductor switches are developed in the 980s, S circuits were not utilized as a small and lightweight power supply. After high speed and low on-resistance power MOSFET s are marketed in 990s, various topologies for the S power supply have been proposed[]~[8]. Among others, a digitalselecting type proposed in recent years and its times conversion ratio can obtain higher total conversion ratio with the small number of elements [5]~[7]. In this paper, an exponential step-up/step-down type S expanding the digital-selecting type is proposed. The proposed circuits can obtain at most/least times conversion ratio ( and are integer). The conventional digital-selecting type has the structure that cascade stages. On the other hand, the proposed circuits have the times conversion circuit block per one stage. Therefore, the proposed circuits have the various conversion ratios by changing the combination of and. In section, the value of which can obtain the ideal maximum step-up ratio with the same number of elements is analyzed at no-load. In section, HSPIE simulation results are shown and compared with characteristics of the ideal analysis. In general, S converters flow a large inrush current at start-up since multiple capacitors are charged at the same time. This inrush current causes deterioration of circuit elements and affect external devices. The proposed circuit can reduce the inrush current because the number of charged/discharged capacitors can be varied without changing circuit configurations. times conversion circuit block connected in E-ISSN: -66X 65 Volume 5, 06

2 WSEAS TRANSATIONS on IRUITS and SYSTEMS In section, it is confirmed by simulations that the inrush current can be reduced at start-up by changing conversion ratio, as compared with that of the fixed step-up ratio. Proposed ircuit. In general case ( times step-up) Figure (a) shows the proposed circuit of k stages (k=, ). Table shows the meanings of each symbol. The square symbols ~ in this figure indicate switches. They are driven by the non-overlapping phase clocks ~ as shown in Fig.(b). Also, j (j=~) are driven by j clocks. Figure is the general structure of the proposed circuit consisted of circuit block of Fig. connected in cascade. Furthermore, Fig. shows the instantaneous equivalent circuit of Fig.(a) while the clock j is in a high level. The capacitor j,k is charged up to V j,k in a steadystate, since the upper node of j,k is connected to the output voltage of the former stage and the lower node is connected to the ground. This state is repeated for ~ and each capacitor j,k in the same circuit block (same k) is charged up to the same voltage V j,k in a steady-state. At the same time, all capacitors are connected in series and output to each output node j k+. Therefore, the output voltage is V j,k. Since the step-up ratio per one stage is times and stages circuit blocks are connected in cascade, the exponential times step-up ratio can be obtained.. step-up type ( times step-up) Figure shows the proposed circuit with =, =. In this figure, the switches, are driven by the two phase non-overlapping clocks and, respectively. Figures 5(a) and (b) are the instantaneous equivalent circuits in each state. During the state, the capacitor is connected to the D input voltage V in and charged up to V in. Similarly, during the state, is charged up to V in. In each state, capacitors and of the stage are charged by the series connection of and of the first stage. onsequently, the charged voltage of and is V in. Thus the step-up ratio per stage is. In Fig., since the number of the circuit block is, the step-up ratio m is (=8). This circuit is also named the digitalselecting type since each capacitor is charged by the ratio of each binary digit weight [7]. Symbols j k Table Meanings of symbols. Meanings Order of capacitors in the same circuit block (j=, ) Number of capacitor per one stage Order of circuit blocks (k=~) Number of stages in cascade connected blocks j = k j = k k k k k k - k+ k+ k+ k k+ k+ j = j = k j = Φ Φ Φ Φ T (a)ircuit block S k (b)driving clock Fig. Proposed circuit of stage k. V in S S Fig. General structure of proposed circuit. Fig. Instantaneous equivalent circuit in state j. Fig. step-up type (=, =). (a)state ( : high level) (b)state ( : high level) Fig 5 Instantaneous equivalent circuit of Fig.. S k = k = k = L I out V out I j,k j k j+,k j+,k j-,k j j+ j+ j- j j k+ V j,k V j+,k V j+,k j,k V j-,k V j,k V j j,k+ =V j,k j,k V in j = j = k = Φ Φ L T I out V out V out = V in I out V out V in V in Vin V in V in V in V in R L R L 8V in I out V out V in V in V in V in V V in in V in 8V in E-ISSN: -66X 66 Volume 5, 06

3 WSEAS TRANSATIONS on IRUITS and SYSTEMS. step-up type ( times step-up) Figure 6 shows the proposed circuit with =, =. In this figure, the switches ~ are driven by the three phase non-overlapping clocks ~, respectively. Figures 7(a) and (b) are the instantaneous equivalent circuits of k= during each state. During the states,, and, the capacitors,, and are charged up to V in, respectively. In the same time, all capacitors are connected in series and discharged to the output node j in each state. The output voltage V j, is equal to V in and the number of blocks is. Therefore, the step-up ratio m is (=9).. Method of varying conversion ratio In this section, the operation of obtaining the general - ~ + times conversion ratio without changing the circuit configurations is explained. The values of r k and s k are the number of charged and discharged capacitors at the stage k, respectively. In the stage, since the r k capacitors are charged in series by the input voltage V in, each capacitor voltage is equal to V in/ r k. In the same time, since the s k capacitors are discharged in series to the next stage, the conversion ratio per one stage m k is s k / r k (s k, r k : integer). Therefore, the total conversion ratio is expressed by the following equation. s s s sk m r r r () k r k Figure 8 shows the proposed circuit of the stage and the general stage k. In these figures, the phase of each switch is indicated the equation expressed by s k and r k in each square. These values are repeated cyclically,, when it is over or below. In the stage (k=), in order to the series charge of the r capacitors, the phase of the input switch S j, 0 is expressed by +-r. Similarly, the output switch S j, in the stage is expressed by +-s. The phases of the ground-switch S jg, and the ring-switch S jr, don t depend on s and r in the first stage. Also, the next ground-switch S jg,k+ and the output switch S j,k+ shift due to the former output s k- and the input r k. That shift amount is expressed by the following equation. k p ( s r ) () k l l l As an example, Fig.9 shows the instantaneous equivalent circuit with =, =, r =, s =, r =, s =, p =s - r =. As the stage in these figures, the step-down voltage can be obtained by charging multiple capacitors in series. The proposed circuit can obtain the variable conversion ratio by shifting each clock phase. Therefore, the inrush current at start-up can be reduced by setting low conversion ratio at start-up so that the number of charging capacitors at the same time is reduced. The output voltage V in Iin k = k = Φ Φ j = Φ T I out j = j = V out R L L Fig 6 step-up type (=, =). (a)state ( : high level) (b) State ( : high level) Fig.7 Instantaneous equivalent circuit of k= in Fig.6. stage (k=) stage k Fig.8 Expression of phase using s k and r k. V in V in Vin V in Vin (a)state (b)state V, =V in V in V in Vin V in S,0 +- r +- s V,, Sr, S,0 - r - s V,, Sr, Sg, S,0 S, - r - s V,, Sr, S, Sg, S, Sg, V,k Sr,k V,k - p k V, =V in S,k k j k+ +- s k -p k,k -p k S,k k - s k -p k,k -p k Sr,k - p k S,k k - s k -p k V,k,k -p k Sr,k - p k Sg,k Sg,k Sg,k /V in /V in V =V in k+ k+ V in V in Vin V in V =/V in V in V in Vin V /V in in /V V in =V in V =/V in E-ISSN: -66X 67 Volume 5, 06

4 WSEAS TRANSATIONS on IRUITS and SYSTEMS reaches maximum value by increasing the conversion ratio gradually..5 Number of elements versus step-up ratio In this section, the value of which can obtain the maximum step-up ratio (m = ) with the same number of elements is analyzed by changing and. The ideal step-up ratio is compared at no-load and steadystate. Therefore, the on-resistance of each switch is ignored. From Figs. and, the ideal step-up ratio m, the number of capacitors N except for L, and the number of switches N SW are expressed by the following equations, respectively. () () NSW ( ) (5) Since capacitors are connected stages, N is shown by Eq.(). Also, since three switches are needed per one capacitor and the input switches are connected the input voltage, N SW is shown by Eq.(5). From Eq.(), substitute =N / into the Eq.() under the condition that N is constant. N m (6) Taking the logarithm of Eq.(6) in order to calculate the when m becomes the maximum value at the same N. N N ln m ln ln (7) Differentiating both sides by, dm N N ln d m dm N ln N d m N N dm ln. (8) d At dm/d=0, since m becomes maximum value, e.78 (9) Figure 0 shows the characteristics of Eq.(6) when the value of is continuous. From this figure, m becomes maximum at =e in spite of N. Furthermore, when N is increased, these curves become sharp. Figures and show the characteristics of the step-up ratio m versus the number of capacitors N and the number of switches N SW, respectively. In these figures, is an integer value practically. Both figures indicate that the step-up ratio of = is maximum with the same number of elements since it is closest integer number to e. V in V in Vin V /V in in /V in V =V in V =/V in Step up ratio m Step-up ratio m (c)state Fig.9 Instantaneous equivalent circuit e 0 N =0 6N =6 N = Fig.0 versus step-up ratio. = = = =5 = Nunber of capacitors N Fig. Number of capacitors versus step-up ratio. Step-up ratio m 00 0 = = = = = = =5 =5 =6 = Nunber of switches N SW Fig. Number of switches versus step-up ratio. HSPIE simulation In this section, HSPIE simulations are performed in the case of = and = by considering the on-resistance of each switch. Table shows the circuit parameters used simulations. The on-resistance E-ISSN: -66X 68 Volume 5, 06

5 WSEAS TRANSATIONS on IRUITS and SYSTEMS r on is only considered for the switching elements. = with = (Fig.) and = with = (Fig.6) are selected so that the number of capacitors are equal in each circuit. Moreover, the simulations of = type are performed under the conditions A and B. In the condition A, the values of r on and the clock frequency f c are the same value as those of =, respectively. In the condition B, the chip-size and the minimum turnon/turn-off time of each switch are equal to those of =, respectively. Since r on is getting bigger when the number of switches increases on the same chip-size, the r on of = is slightly smaller than that of = (0/ turn-on/turn-off time of each switch is same, f c is / times that of = since the clock period T c of = is / times times). Moreover, when the minimum. Output voltage waveforms at start-up Figure shows the simulated output voltage waveforms at start-up under the condition that the input voltage V in is.v and no-load. These output voltages V out in both = and = reach a steady-state about 00 s and are converted up to the ideal voltage ( V in). Output voltage V out (V) = (condition B) V in =.V R L = Time t (s) = = (condition A) Fig. Simulated output voltage waveforms at start-up.. Output characteristics Figures and 5 show the characteristics of the power conversion efficiency and the step-up ratio m, respectively when the output power P out is increased to 0W by changing the load resistance R L. From these figures, the power conversion efficiency of = under the condition B is about.6% higher than that of =. Also, the step-up ratio of = is about 0.% higher than that of = under the condition B. Therefore when the on-resistance of each switch and the clock frequency are equal in each circuit, = has the highest efficiency similarly to the ideal analysis. However, in an actual circuit = has the highest efficiency since the voltage ripple of each capacitor is reduced as the clock frequency is higher. Table ircuit parameters. ompared circuit = = onditiona onditionb Number of capacitors per stage Number of cascade stage Ideal step-up ratio m= Number of capacitors N c Number of switches N sw 0 0 Input voltage V in.v.v.v Maximum output voltage V out_m 9.7V 6.V 6.V harge transfer capacitor 0 μf 0 μf 0 μf Smoothing capacitor L 0 μf 0 μf 0 μf On-resistance r on of switch 0mΩ 0mΩ 9.5mΩ lock frequency f c 70kHz 70kHz 556kHz lock period T c.7μs.7μs.8μs Number of clock phase(= ) Efficiency η (%) Step up ratio m V in =.V =( =(condition 条件条件 B) B) B) = = =( =(condition 条件条件 A) A) A) Output power P out (W) Fig. Output power versus efficiency V in =.V = = =( =(condition 条件 B) B) B) =( =(condition 条件 A) A) A) Output power P out (W) Fig.5 Output power versus step-up ratio.. Variation of output voltage at start-up Figures 6 and 7 show the simulated output voltage waveforms and the inrush current waveforms at start-up, respectively under =, = and the parameters of Table. The conversion ratio is varied - ~ + times and compared with the fixed times step-up ratio. Table shows variation of the conversion ratio E-ISSN: -66X 69 Volume 5, 06

6 WSEAS TRANSATIONS on IRUITS and SYSTEMS changing the number of the charging capacitors r k and the discharging capacitors s k at start-up. In this table, m and m are the conversion ratios in stage and stage, respectively. The conversion ratio is changed per 50 clock periods as shown in this table. At first, m is fixed to the minimum and m is increased gradually from the minimum to the maximum. Next, m is increased gradually. From Fig.7, the inrush current is reduced about / of the fixed step-up ratio. Output voltage V out (V) Fig.6 Simulated output voltage waveforms at start-up. Input current (A) times fixed times fixed - ~ + times variable V in =.V R L = = L =0μF Time t (s) V in =.V R L = = L =0μF - ~ + times variable Time t (s) Fig.7 Simulated inrush current waveforms at start-up. onclusion In this paper, an exponential step-up/step-down type switched-capacitor power supply is proposed. Furthermore, the ideal maximum step-up ratio is analyzed in general circuits and HSPIE simulations are performed under the step-up type and the step-up type. As a result, () at no-load simulation, the step-up type is obtained the highest step-up ratio when the same number of elements, () under the load simulation, the step-up type has the highest power conversion efficiency under the same chipsize and the same turn-on/turn-off time of each switch. onsequently, under a light load, the stepup type is the optimum since the step-up ratio is the highest with small drop of the efficiency. oncerning the proposed circuit of the type, the inrush current at start-up can be reduced / by controlling the conversion ratio. In the future, experiment results will be compared with the simulated results. Table Time variation of conversion ratio. Time t m m m=mm r s r s Tc Tc Tc Tc Tc 0. 00Tc Tc 00Tc Tc 6 500Tc 9 References: []. D. ockcroft and E. T. S. Walton, Experiments with high velocity positive ions. I. Further developments in the method of obtaining high velocity positive ions, Proceedings of the Royal Society A, vol.6, pp.69-60, 9. [] On-heong Mak, Yue-hung Wong and A. Ioinovici, "Step-up D power supply based on a switched-capacitor circuit," in IEEE Transactions on Industrial Electronics, vol., no., pp , Feb 995. [] A. Ioinovici, "Switched-capacitor power electronics circuits," in IEEE ircuits and Systems Magazine, vol., no., pp. 7-, Third Quarter 00. [] A. Gherlitz, Y. Berkovich and A. Ioinovici, "Stepup switching-mode converter with high voltage gain using a switched-capacitor circuit," in IEEE Transactions on ircuits and Systems I: Fundamental Theory and Applications, vol. 50, no. 8, pp , Aug. 00. [5] L.-. hang and.-h. Hu, High efficiency MOS charge pumps based on exponential-gain structure with pumping gain increase circuits, IEEE Trans. on Power Electronics, vol., no., pp.86-8, May 006. [6] L.hang and.hu, A discussion on exponential - gain charge pump, IEEE Trans. on power electronics, vol., no., May 006. [7] T.Tanzawa, On two-phase switched-capacitor multipliers with minimum circuit area, IEEE Trans. on ircuits and Systems, vol.57, no0, Oct 00. [8] I. Vaisband, M. Saadat and B. Murmann, "A losed-loop Reconfigurable Switched-apacitor D-D onverter for Sub-mW Energy Harvesting Applications," in IEEE Transactions on ircuits and Systems I: Regular Papers, vol. 6, no., pp. 85-9, Feb. 05. E-ISSN: -66X 70 Volume 5, 06