Duty cycle control algorithm used in digital power factor correction

Transcription

1 ELECTRI C MACHINES AND CONTROL Vol. 14 No. 3 Mar Boost 1 khz. 998 Boost TM 76 A X Duty cycle control algorithm used in digital power factor correction WU Li-hua 1 GUO Wei-guang 1 WANG Xu-dong 2 SONG Xiao-feng 1 1. The Higher Educational Key Laboratory for Measuring & Control Technology and Instrumentations of Heilongjiang Province Harbin University of Science and Technology Harbin 154 China 2. School Electrical and Electronics Engineering Harbin University of Science and Technology Harbin 154 China Abstract Nowadays there are some problems in the digital control power factor correction PFC such as the need of lots of calculations within one switch cycle the limit to increase the switch frequency affected by the processing speed of the digital controller and its finiteness of regulation capability while the load and input voltage change. Therefore a duty cycle control algorithm applied for boost PFC circuit is proposed in this paper. And by using this algorithm the current and the voltage loop can be calculated simultaneously. Furthermore quantity of operations has been reduced sharply. In this algorithm the output voltage ripple and the input voltage feed - forward are introduced to compensate the duty cycle during every switch cycle when the load and the input voltage goes step change in order to ensure the input current a good sinusoid. Then the characteristics of high speed and stability to dynamic response for the PFC system are guaranteed. It is proved by the simulation results that the power factor reached. 998 when the circuit switching frequency was 1kHz. And the power factor correction has been achieved finally. Key words power factor correction duty cycle control algorithm digital control Boost circuit output voltage ripple

2 3 93 PFC PI PFC 6 d n = L i ref n i L n + V ref - V in n T s V ref V ref 1 i ref n + 1 = k PID sin ω line t n d n n i L n n i ref n + 1 n + 1 n k PID sin ω line t n + 1 DSP DSP T s V in n n V ref V o V ref L T s k PID 1 1 power factor correction PFC d n = d 1 n + d 2 n 3 d 1 n = L i ref n i L n 4 T s V ref d 2 n = V ref - V in n 5 DSP V ref 3 ~ 5 d 1 n d DSP 1 PFC PFC 6

3 i ref n i L n L T s d 1 n = V ref - V^ ripple n 9 d 2 n = V ref - V in n - V^ ripple n V ref - V^ ripple n 1 PFC PFC PFC 2. 2 k PID PFC 2 1 PFC V ripple t = P o sin 2ωt 6 2ωCV o ω P o V o d update n = d n + Δd n 11 C 6 d update n MOSFET d n 8 Δd n Δd n = Δv in n 12 V ref v in n = v in n - V in n THD v in n = V inpk sin ω line t n V inpk V o DSP P o = V o i o n i o n n V in n n 7 v in n V^ ripple n = i o n 2ωC sin 2ωnT v 7 Δd n T v 7 T v ω C d 2 n d 2 n = d 2 n + d n = 1 - v in n - 2V in n V ref - V^ ripple n T v ω C 13 d update n 8 1 V ref V o d update n = d 1 n + d 2 n 14 V o V ref = V ref - V^ ripple n d n = d 1 n + d 2 n 8 14 d 1 n d 2 n DSP

4 sin ω line t n PFC n + 1 i ref n d 1 n 7 2 v in n 13 d 2 n DSP 1 MOSFET Fig. 1 V o i L 电压环 PI 调节器 K PI 电流环的计算 V in 驻 V in(n) 电压环前馈电压的计算的计算 d 1(n) d 2(n) 驻 d(n) PWM 波形的产生 d update(n)=d 1(n)+d 2(n) MOSFET 驱动信号 1 T s = 1 1 = = 1 μs f s 1 Diagram of the duty cycle control algorithm T s T duty DSP 3 DSP Boost 2 PFC AC EMI 继电器滤波器延迟 PFC PFC vin(n) 2 DSP ADC ADC2 乘法器 Vin V in n i o i o n 7 V^ ripple n V o V ref = V ref - V^ ripple n DSP ADC3 2 PFC V o V ref Fig. 2 The digital control PFC circuit adopting PID PID a new algorithm k PID i ref n + 1 k PID 4 DSP PWM DSP TMS32LF247A 4 MHz. 25 μs 4 5 T duty = =. 125 μs f S = 1 khz PFC DSP sin[ 棕 linet(n+1)] iref(n+1) V 赞 正弦波形查找表 TMS32LF247A 占空比的计算 V in n 1 khz PFC ripple(n) kpid V ref d(n) il(n) Vin(n) il L2 L1 驱动信号 Q1 PWM PWM1 过零检 ADC 测器 ADC1 纹波 io(n) 检测 ADC2 电压环差值 - Vo PID 调 ADC3 节器 + Q2 il io Vo D1 D2 C + R Matlab /SIMULINK

5 V 3 u(1%v/div),i(1%a/div) 2 u 1 i -1-2 %%%%%%%%%%%%.2%%%%%%%%%.4%%%%%%%%%.6%%%%%%%%%.8%%%%%%%%%%.1 t(.2%s/div) 3 (b) 输入电流 Fig. 3 Input voltage and current waveforms V Fig. 6 Output voltage and input current waveforms for. 998 step load change from half load to full load 4 7 u(1%v/div),i(1%a/div) 2 u 1 i -1-2 %%%%%%%%%%%%.2%%%%%%%%%.4%%%%%%%%%.6%%%%%%%%%.8%%%%%%%%%%.1 t(.2%s/div) 4 36 Fig. 4 Input voltage and current waveforms when input t/%s (a) 输出电压 voltage is destroyed %%%%%%%%%%%%%.5%%%%%%%%%%%%.1%%%%%%%%%%%%.15%%%%%%%%%%%%.2 2 (b) 输入电流 -2 7 (a) 输入电压 5 Fig. 7 Output voltage and input current waveforms for step load change from full load to half load i/a (b) 输入电流 %%%%%%%%%%%%%.5%%%%%%%%%%%%.1%%%%%%%%%%%%.15%%%%%%%%%%%%.2 (c) 输出电压 6 5 Fig. 5 Input current and output voltage waveforms for step input voltage change 13 i/a t/%s (a) 输出电压 -5 %%%%%%%%%%%%%.5%%%%%%%%%%%%.1%%%%%%%%%%%%.15%%%%%%%%%%%%.2 2 V 6 7 i/a DSP PFC 1 khz. 998

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