FPGA BASED IMPLEMENTATION OF WAVELET CONVOLUTION

Transcription

1 The 6 th edition of the Interdisciplinarity in Engineering International Conference Petru Maior University of Tîrgu Mureş, Romania, 2012 FPGA BASED IMPLEMENTATION OF WAVELET CONVOLUTION Sándor Tihamér BRASSAI #1, László BAKÓ #1, László Ferenc MÁRTON #1, Zoltán GERMÁN-SALLÓ #2, Lajos LOSONCZI #1,*3 #1 NSRG - Neural Systems Research Group, Sapientia Hungarian University of Transylvania Sos. Sighisoarei 1.C., Tirgu Mures/Corunca, Romania 1 tiha@ms.sapientia.ro #2 Department of Electrical Engineering, Petru Maior University str Nicolae Iorga, nr.1, Tirgu Mureş, Romania *3 Lambda Comunication L.T.D. Str. Avram Iancu nr. 37,Tirgu Mureş, Romania ABSTRACT The continous Morelet wavelet transform is very commonly used modern method in EEG signal analysis. The objective of the paper is a real time functional hardware implementation of the continuous wavelet transform calculus. The calculation of this wavelet spectrum is realized in the time-frequency domain. The researcher has also preferred to use FFT IP cores as a processing tool, in the FPGA implementation of the continuous wavelet transform. In this paper a parallel-pipeline real-time functional architecture is presented and the wavelet spectrum is calculated in the time-frequency domain. Some figures for different tests and EEG signals with the designed hardware units are also presented. Keywords: Wavelet transform, Hardware implementation, FPGA, embedded design 1. Introduction In the EEG signal analysis a very commonly used method is the continuous wavelet transform using the comple Morlet wavelet function of order 6. The objective of the paper is the real time functioning hardware implementation of the Morlet wavelet transform. The question arising is whether the wavelet-convolution algorithm can be parallelized and implemented in FPGA circuit providing real-time operation of the system. From the study of the Wavelet convolution algorithms [1][14][15][13] and from results and eperience of current research in the field of hardware implementation of artificial neural networks on FPGA circuits led to the conclusion that wavelet spectrum could be implemented with real time operability in FPGA circuits. The eperience gained from the real time functional hardware implementation in FPGA circuits of the Radial Basis Function Neural Network (RBFNN [5][10][11]), Cerebellar Model Articulation Controller (CMAC[7][8][9]), fuzzy inference systems [6][20] and the researcher s results with wavelet hardware implementation [3][19] are successfully applied in the continuous wavelet convolution discrete hardware implementation. The continuous wavelet spectrum, in most cases, is using also the frequency domain based on direct and inverse fast Fourier transform as simplifying tools in calculus [16]. Several implementations is known using the graphics processing unit for real-time brain computer interface feature etraction [2] On the known FPGA implementations of the continuous wavelet transform, it is preferred to use the FFT transform, in other words FFT IP core configured with IP Core Generator [17]. In the hardware version presented in this paper the Fourier transform was not used, a parallel pipelined architecture that provides real-time calculation of the wavelet spectrum in the time domain is proposed. 2. Materials and methods The results of the hardware implementation of the wavelet convolution were tested with real EEG 332

2 signals. For the test signal acquisition a BrainMaster, two channels, 250Hz sampling frequency EEG signal acquisition system were used. The wavelet spectrum calculation was performed by a high level programming language. The result of the hardware implemented wavelet convolution was compared with the software implementation to verify the correct operation of the hardware version. From the wavelet convolution algorithm it is obvious that, in order to work out the convolution product, the required operations are multiplication and addition. From the available FPGA-based development systems in our laboratory, one Virte II Pro and Virte V-type circuits were found to be suitable as hardware support for the mentioned application. In the first phase the wavelet transform system was implemented on VHDL without using any embedded processors. The tests showed the need for an embedded processor, and eternal memory (e. flash memory) for simple and easier introduction of the EEG signals, and interpretation of the results. The design, testing and startup required the use of several software packages. For the wavelet convolution hardware implementations in VHDL-the XILINX ISE Proiect Navigator was applied. During the design a modular, subsequently etensible, scalable and configurable circuit was created, based on the size of the FPGA. The use of the predefined IP cores, such as the multiply and accumulate (MAC) IP module, the memory modules generated from BlockRAM type memories with Block Memory Generator simplified the implementation of some modules. The correct functionality of the prepared VHDL modules was tested with simulation methods using the ISE Simulator. The scalable structure should help to configure the application according to the size of the proposed FPGA circuits, using the FOR GENERATE and IF GENERATE VHDL instructions specific for concurrent components instantiation, specifying the system parameters (number of concurrent modules, number of bits used for data representation). The hardware convolution module implemented in VHDL was integrated to the Processor PLB bus system as a peripheral unit using the Embedded Development Kit. In the testing phase of the system the EEG signals were introduced and the convolution results saved for interpretation with the integrated SD card or Compact Flash card, depending on the used development board. Testing the system proved to be a comple and difficult task because of errors that may have been made in the hardware convolution unit, such as in program running on the embedded processor responsible of the data entry and data save management. The processor program debugging implies the integration of the XPS MDM module. The hardware unit testing proved to be more difficult and time consuming compared to software debugging. For the hardware modules testing and debugging an Integrated Logic Analyzer (ILA) core which can be integrated in FPGA circuit with ChipScope Pro interface, 232 bit Tektroni eternal logic analyzer, and for simple cases oscilloscope was used. In many cases, the behavioral level simulation of the circuit performed proved to be successful, but after the implementation in hardware, the FPGA circuit did not worked as it was epected. The internal logic analyzer proved to be the most useful for the detection of the above mentioned hardware design errors. 3. Results The design and testing of one hardware implemented module/circuit for calculation in realtime of the wavelet spectra of EEG signals for multiple scale values for the two type FPGA circuits previously mentioned was successful. In the following tables the most important characteristics of the two FPGA circuits from the point of view of implementation of the wavelet convolution respectively the designed hardware s most important parameters are presented. Table 1. FPGA circuit parameter Characteristics of the FPGA circuits Type of the used development boards from the point of view of the wavelet convolution implementation XUP Virte- II Pro Developmen t System Opus Virte - 5 Develop ment Board Type of the FPGA circuit Virte-2 Pro XC2VP30 Virte-5 FX30T Embedded 2PowerPc PowerPc processor The used tools for design and testing Number of BlockRAM memories Dedicated hardware multipliers XILINX ISE, EDK, SDK BRAM, of 18kbit bit MUL 1818 XILINX ISE, EDK, SDK 12.4 Converte d to drb of 18kbit BRAM 64 DSP48E 333

3 Table 2. wavelet module parameters Hardware implemented Type of the used development boards wavelet module parameters XUP Virte- II Pro Developmen t System Opus Virte - 5 Develop ment Board Number of channels operating in parallel Dimension of buffer for input signal storing Size of wavelet window Data representation Integer Integer Scale number Working frequency 100 Mhz 400Mhz Spectrum display in real time on the Yes No screen Eternal nonvolatile memory Processing time for 64 n window. 64 number of scale, n number of samples Processing time for 1024 samples (256 Hz sampling time of EEG signal which correspond to 4sec) Input signal encoding Result representation Wavelet function values encoding 1Gb COMPACT Flash e-004 sec (for n=56 points) ( )*6 4*1/ sec (1024/56*( )*64 *1/ ) On 12 bits Complement of two (configurabl e) 24/32 bit unsigned integer 12 bit Complement of two 2Gb SD Flash e- 004 (for n=24 points) ( )*64*1/ se c (1024/24 *( )*64*1 / ) On 12 bits Comple ment of two (configur able) 24/32 bit unsigned integer 12 bit Comple ment of two The wavelet convolution unit was tested with real acquisitioned EEG signals. This paper is focused on the wavelet convolution implementation on FPGA circuit and not on the EEG signal analysis (signal processing). In the following drawings the wavelet spectra results obtained for different EEG signals at different scale ranges are presented (scale value is in a relationship with frequency [18]). In the following two time-frequency diagrams the test results for two sinusoidal signals can be seen on Fig 1 and Fig 2. For the two sinusoidal signal frequencies 10Hz and 20 Hz, the wavelet spectrum was calculated for scale values corresponding to frequencies between 8 and 40Hz. The test signals demonstrate the correct operation/functioning of the system, identifying the two sinusoidal signal frequencies of 10Hz and 20Hz. Fig. 1 wavelet spectra for test signal of 10Hz Fig. 2 wavelet spectra for test signal of 20Hz The results of the wavelet spectrum for two EEG signals measured with BrainMaster acquisitioning system in the Hz bandwidth of the results are presented in the following figures (Fig.3, Fig.4). Fig. 3 EEG signal and wavelet spectrum for frequency between 0.25 and 8.25Hz 334

4 Fig. 4 EEG signal and wavelet spectrum for frequency between 0.25 and 8.25Hz Fig. 7 wavelet spectrum for frequency between 0.25 and 16.25Hz from 29 to 37 seconds At the end of the evaluation of the hardware implemented wavelet convolution unit the wavelet spectra is recalculated on FPGA for signals presented at FENS2012 Shop (Barcelona) [17] where the wavelet spectra was implemented in a high level programming language. It can be observed that the difference is due to the sampling period and the wavelet transform scaling. Fig. 5 wavelet spectrum for frequency between 0.25 and 16.25Hz from 0 to 180 seconds Fig. 8 wavelet spectrum for frequency between 0.25 and 16.25Hz from 54 to 63 seconds In the figures below (Fig.6, Fig. 7, Fig. 8, Fig. 9) the wavelet spectrum for smaller intervals of the entire signal presented in figure (fig 5) is highlighted. The following figures represent the range from 18 to 22 sec (Fig.6), from 29 to37sec (Fig.7) from 54 to 63 sec (Fig. 8) and from 84 to 89 sec (Fig. 9) for scale range coressponding for frequencies between 2.5 and 17.5 Hz. Fig. 9 wavelet spectrum for frequency between 0.25 and 16.25Hz from 84 to 89 seconds Fig. 6 wavelet spectrum for frequency between 0.25 and 16.25Hz from 18 to 22 seconds The test measurements confirm the correct operation of the hardware implemented convolution unit. This is an important result for the planned online use of wavelet transform in EEG signal processings and pattern recognition tasks. 335

5 4. The hardware implementation of the wavelet convolution The block diagram in Fig. 10 presents the proposed parallelized model of the algorithm for wavelet spectrum processing. In the figure only the data echange is presented, without detailing the control signals. The structure has parallel pipeline architecture. In he block diagram four functional parts can be distinguished: One of the four parts is the buffer channel formed from the register Reg (Fig. 10), which ensures that the input signal is carrying to the convolution multiplications modules inputs at the right time. During processing, for each clock signal of the automata controller, a new value of X is shifted into the buffer. The net part is composed of multiplying and adder modules to compute the convolutional product of the input vector and the Morlet wavelet values for a defined scale value. It is true that the calculation of the convolution product is made sequentially, but the convolution product of multiple sampling is done in parallel (Fig. 10). To calculate the wavelet spectrum at one sampling for one scale value two MAC modules are required. S(N) One is required to calculate the real part and the other to perform the imaginary part of the convolution product. At the output of the MAC modules the buffer composed of registers R respectively I is shown. The results of the convolution product are stored in these registers. Registers I (0), I (1), I (N) are of the imaginary part and registers R(0), R (1), R (N) of the real part convolution product result store. N represents the number of points on which the calculation is done in parallel. Accordingly to the proposed first variants of the hardware implementation of the wavelet spectrum [12] after the I and R registers output a pair of twolevel units were applied (with two multiplications and one addition). Because of the high hardware requirements of the previous mentioned version only a single module is used. While the convolution products are calculated for scale value s(k) the wavelet spectrum is calculated for s(k-1) shifting the data in buffers with registers I and R to two multiplier MULs and in the net clock cycle to the adder unit. The wavelet function values are calculated in advance and stored in the BRAM memory. One memory is used for the real part and the other for the imaginary part. MUL MUL + I(N) Reg(N) + R(N) + I(1) Reg(1) + R(1) + I(0) + R(0) Reg(0) R(n-k) X(k) (n-k) Fig. 10 wavelet convolution data paths All Fig. 11 Wavelet convolution unit general block scheme As well the incoming EEG signals are stored in a vector, implemented as a dual port BRAM memory 336

6 From one of the ports the input values are read out and on the other port the new vector values are stored. The general block scheme of the wavelet convolution unit is presented in figure 11. The result is also stored in a memory implemented as a dual port BRAM. Simultaneously the last results can be read out and transferred to the signal identification module, respectively the calculated new wavelet spectrum values are stored in an alternate port of the BRAM Memory. Depending on the type of the development board, if it is equipped with a VGA output, the wavelet spectra on line can be visualized on the monitor attached to the FPGA development board. The visualization module is composed of a VGA controller, and a dual port BRAM memory. At the port A the results are stored in the memory and on the other port B the results is read out by the VGA controller. As it was mentioned, the input and result memory were implemented with dual port memories. Port A of the memories are connected to the BRAM controller connected to the Processor Local Bus of the processor system. The architecture of the system is presented in figure 12. The peripheral units are connected to the PLB bus of the processor. The hardware implemented wavelet convolution unit is connected to the PLB bus with a General purpose input output interface. On this interface is the internal register of the control unit of the wavelet module is initialized, respectively the status register is also read back on this interface. From the program running on the PowerPC processor the input memory is initilaized with the input vector through the BRAM controller connected to the input memory. From the program the result memory is read back through the BRAM Controller connected to the result memory. The Virte II Pro development board uses a Compact Flash memory respectively the Virte V development board has an SD card connected. The acquisitioned signals are stored in the mentioned flash memories, from which the internal memories are initialized. The result is written to the flash memory. 5. Conclusions In conclusion, it was epected, the hardware implemented wavelet spectrum computing module has been realized in the FPGA circuit with a real time operability. The number of the spectrum points which can be processed in parallel depends on the FPGA circuit capacity, and is greatly affected by the number of hardware multipliers. Specific to the presented implementation is that the computation is made in the time domain. Furthermore, using the embedded hardcore processors (PowerPCs) available in the Xilin Virte circuits [4] gives an etra advantage, by enabling easy data echange between the FPGA and the EEG signal acquisition hardware. The parametrized architecture gives the advantage to configure the hardware module according to the used FPGA circuit resources. The BlockRAM memory was used for input and results storage. Acknowledgement This work is part of the project funded by the Romanian National Authority for Scientific Research, grant No. 347/ Fig. 12 Integration of the convolution module, and other important modules to the embedded processor bus system References [1] Germán-Salló, Z., Mózes F.-E., Wavelet transform based ECG signal filtering implemented on FPGA, Scientific Buletion of the Petru Maior University of Târgu Mureş, Vol. 8, (XXV), no. 2, 201, pp

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