Inter-Ing INTERDISCIPLINARITY IN ENGINEERING SCIENTIFIC INTERNATIONAL CONFERENCE, TG. MUREŞ ROMÂNIA, November 2007.

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1 Inter-Ing 007 INTERDISCIPLINARITY IN ENGINEERING SCIENTIFIC INTERNATIONAL CONFERENCE, TG. MUREŞ ROMÂNIA, November 007. SIMULIN MODELING OF IMAGE REJECTION ALGORITHMS irei Botond Sandor, Topa Marina, Dornean Irina, Fazakas Albert Technical University from Cluj-Napoca ey words: implementation plan, low-if receiver, I/Q imbalance, image rejection Abstract: Nowadays the manufacture of value-added products is the main interest of every branch of industry. An implementation plan is one of the necessary requirements for obtaining a valueadded product. In this paper the implementation plan of an image rejection algorithm in digital domain is presented. The RF signal demodulation in low-if receivers takes place in two steps. First the RF signal is translated to an intermediary frequency. This down conversion can introduce interferences between the desired signal and the signal in the adjacent band. The elimination of the interfered signal is called image rejection. The implementation uses a Simulink model, as a prove of the theory. A hardware implementation scheme, built on the Simulink model, is given also. Finally, conclusions are drawn and further developments will be discussed. 1. Introduction The creation of value-added products is the main scope of every branch of industry. If marketing identifies the customer s wish for an additional task or better performance, then further developments including substantial research and project scheduling have to be carried out. This paper deals with the key aspects in the implementation plan for image rejection in wireless communication receivers. Several methods are used for the reception of wireless signals. The direct down conversion receivers [1] imply the use of precise electronic components, resulting in high costs. The low-if receivers are cost effective and more flexible []. Section describes the applied methodology of implementation for a value-added product. Section 3 presents the architecture of the low IF receivers [1] and explains the phenomenon of I/Q imbalance. The state of the art I/Q imbalance compensation algorithm is based on statistical calculations. Recent efforts invested in developing the block level representation of the image rejection filter is given in Section 4. Starting from it a Simulink model was developed and presented. The proposal for hardware implementation is presented in Section 5. Finally conclusions shall be drawn. IV-5-1

2 . Implementation plan In the era of technical competition it is not enough to manufacture a product, but it has to become a serious competitor on the market. This can be achieved by considering different aspects in delivering a product. The methodology of development similar to [3] is depicted in Fig. 1. An important step in the creation of a product is to make the specifications. This is influenced by the feasibility, the need of the market, the competitors and in this case by wireless standards. The feasibility of the product influences the specification directly (a fuel-engine can not be made at the size of a matchbox). The market research can help to find out the need of customers and of course to measure up the competitors. The state of the art products must be considered in order to place the product in the front-end. The block level representation (system model) is necessary to form an idea about the structure of the product. This is useful for the project schedule and helps to assemble the team of developers. Using the block level representation a design-ware tool can be used to prove that the product can work theoretically. In this phase software simulations can be performed and the first results are obtained. The design-ware tool used for the image rejection filter is MATLAB/Simulink. A well structured Simulink model is a great help in hardware implementation. From this model automated tools can perform the implementation on different platforms (DSPs or FPGAs). Then the hardware is tested on development boards or if necessary a prototype can be manufactured also. A convenient implementation plan responding for the highest standards helps the marketing department to sell the product. Having a readable development plan, the customers are convinced about the success of the product. Wireless standards Market research Specification / Feasibility study Block level representation Simulink model Software simulations Hardware implementation Hardware tests Marketing State-of-the-art products Fig. 1. Image rejection implementation flow chart 3. The I/Q imbalance in Low-IF receivers The wireless signal demodulation in low-if receiver takes place in two steps. First the radio frequency (RF) signal is shifted to an intermediary frequency (IF) in the analogue domain, then the IF signal is sampled. The necessary signal processing is done in the digital domain. The disadvantage of this architecture is the need of image rejection, but the programmability offered by the digital domain makes it flexible and reconfigurable. IV-5-

3 In Fig. the low-if receiver s architecture is depicted. In the analogue domain the signal collected from the antenna, having the expression given in (1.), is filtered by a bandpass filter in order to clear the noise. + jπflot jπflot rt () = zt () e + z() t e (1.) where z (t) is the conjugate of z(t). The complex signal z(t) is formed by the desired s(t) and image i(t) signals (from an adjacent band). z( t) + jπf IFt jπf IFt = s( t) e + i( t) e (.) MIX d(n) s(n) BPF Analogue domain r(t) LNA MIX X LO r IF (t) _ r IF (t) ADC _ r IF (n) Digital domain IF MIX v(n) Image rejection i(n) Fig.. The low-if receiver architecture The filtered signal is amplified by a line amplifier (LNA) and is mixed with the signal generated by a local oscillator (x LO (t)): xlo ( t) = cos(π f LOt) j g sin(πf LOt + ϕ) (3.) where g is the amplitude and ϕ the phase mismatch. Due to the imperfections of the electronic components the local oscillator introduces the I/Q imbalance errors: 1 1+ g e = 1 g e = jϕ + jϕ. (4.) Using the I/Q imbalance parameters we can write the expression of r IF (t) sampled by the ADC: r () t = { r ()} t = {() r t x } = z() t + z () t (5.) IF IF LO 1 where stands for lowpass filtering. After sampling, the signal is down-converted into the baseband. This operation is performed in the digital domain and the provides the following signals: j πfif nt 1 dn ( ) = r { ( n) e } = sn ( ) + i( n) IF + j πfif nt 1 vn ( ) = r { ( n) e } = in ( ) + s( n) IF (6.) A simplified representation of these operation is obtained using the matrix form: dn ( ) sn ( ) 1,where v ( n) = i ( n) = 1 (7.) IV-5-3

4 The recovery of the desired signal from the interfered signals in mathematical therms is just a matrix product. The task is to find out the inverse matrix of. 4. Image rejection algorithm Image rejection in the digital domain is based on statistical calculations [], [4]. The algorithm calculates the product of I/Q imbalance parameters 1 and. From this product the amplitude and phase errors can be deduced according to the following equations: = 1 N dn ( ) vn ( ) n= 0 N dn ( ) + v( n) n= 0 g = 1 4 Re{ 1 } ϕ = arcsin Im{ 1 } g The proposed block level design for the filter is shown in Fig. 3. The analogue-digital converter provides the samples of IF signal. The baseband transition is done in the digital domain using two multipliers and a digital oscillator. After a complex low-pass filtering the samples go to the Error parameter estimation block to perform the statistical computation, the result being the inverse matrix of. (8.) Baseband downconversion d(n) v(n) Matrix product s(n) i(n) X Analog Signal Analog/ digital converter Digital oscillator Error parameter estimation -1 X 1 g, phi 1, Fig. 3. Block level representation Starting from the block level representation from Fig. 3, the Simulink model of the algorithm was created. The models for the Baseband down-conversion and Matrix product are easy to be computed. The focus will be on the Error parameter estimation block depicted in Fig. 4. IV-5-4

5 Fig. 4. Simulink model for error parameter estimation The input signals d(n) and v(n) given by the expressions (6) are the result of baseband conversion. The samples of these signals are used then in the sub-modules 1 product, Error parameters to compute the equations (8). The sub-modules Computation of 1 and Computation for provide the values of 1 and according to (4). Matrix is formed as in (7) and the elements of the inverse matrix are calculated in the block Inverse matrix computation. 5. Proposed hardware implementation The implementation of the image rejection algorithm can be done on different platform (DSPs, FPGAs). Usually the algorithm is developed in a commonly used language like C and tested in DSP platforms. The Simulink model presented in Section 5 was developed for FPGA implementation of the image rejection filter. In this section a proposed hardware implementation is given, the block diagram being depicted in Fig. 5 The proposed hardware contains the image rejection filter, the serial reception/ transmission interface and buffer zones between these two. The buffer zones are dual frequency FIFOs and are used to ensure a constant flow to/from the filter. By using a buffer zone the serial transmission protocols can be replaced with other industry standard busses (I C, SPI, GPIO, PCI etc.) PLL clk clk1 txd Serial transmission re empty Buffer we full rxd Serial reception full we Buffer re empty Image rejection IV-5-5

6 Fig. 5. Proposed hardware implementation 6. Conclusions The creation of value-added products (the customer willing to pay for it; must be perfect at the delivery; the possibility of further developments) is the main scope of research and development. To make the product a serious competitor on the marked several aspects have to be considered in every phase of implementation. Choosing the right marketing, research and development strategy, the time-to-market can be minimized. Following the implementation plan for the presented image rejection filter, the block level representation, Simulink model and proposed hardware implementation architecture were given. This implementation plan allows further developments that can be achieved. By improving the Simulink model the system performance can be tuned or adapted for other applications. Hardware implementation can be done on different platforms (microprocessors, DSPs, FPGAs, ASICs). This paper gives a proposal for FPGA implementation with the possibility of interfacing the filter with different I/O protocols. References 1. S. Chunlei, I. Mohammed, Data Converters For Wireless Standards, luwer Academic Publishers, Dordrecht, 00.. M. Windisch, G. Fettweis, Blind I/Q Imbalance Parameter Estimation And Compensation In Low-If Receivers, Proceedings of 1st International Symposium on Control, Communications and Signal Processing (ISCCSP '04), Hammamet, Tunisia, March J. Lima, R. Menotti, J. M. P. Cardoso, E. Marques, "A Methodology to Design FPGAbased PID controllers", Systems, Man and Cybernetics, IEEE International Conference on, Volume 3, pp , Gye-Tae Gil, Young-Doo im, Yong H. Lee, Non-Data-Aided Approach to I/Q Mismatch Compansation in Low-IF Receivers, Signal Processing, Transaction on, Vol. 55, No. 7, Page(s) , July B. S. irei, I. Dornean, A. Fazakas, M. Topa, Comparing Verilog and VHDL, MicroCAD 007 International Scientific Conference, Proceedings of, pp , 007. IV-5-6