EU FP7 project Multibase. Some Research Projects. related to DSP Design. Motivation. Multibase: January 2008 April 2011

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1 Some Research Projects at EIT related to EU FP7 project Multibase Multibase: January 2008 April 2011 Viktor Öwall Scalable Multi-tasking Baseband for Mobile Communications 1. Multi-streaming radio (concurrent execution of multiple standards) 2. Scalable programmable/reconfigurable multi-processor technology 3. Algorithm/architecture co-design for maximum energy efficiency LU Focus: Synch and Channel Estimation, algorithms and architectures. Digital Front-End Receiver: DFE Rx Contributors: I. Diaz 1, L. Hollevoet 2, T. Olsson 3, J. Rodrigues 1, J. Svensson 3, L. Van Der Perre 2, L. Wilhelmsson 3, C. Zhang 1, and V. Öwall 1 1 Lund University 2 IMEC 3 Ericsson Motivation Design a multi-standard digital front-end receiver including: Automatic Gain and Resource Activity Controller Compensation Filtering and resampling Synchronization Support for concurrent data streams Supported standards: LTE, DVB-H and IEEE n

2 The standards All three standards are OFDM based, however with different FFT-size: LTE: DVB-H: 2048, 4092 (and 8192) IEEE n: and different sample rates: LTE: Msps DVB-H: Msps IEEE n: 20 or 40 Msps n LTE DVB Preamble based Pilot based The multi stream DFE-Rx Two concurrent data streams in hardware. More data streams possible since they do not transmit all the time. Hierarchical wakeup: principle Example: reception of WLAN Component Baseband Activation probability Low Power consumption High Channel Power consumption Preamble DATA Noise Sync AGRAC High Low AGRAC (signal detection) Coarse time sync Baseband processing time False trigger, no power wasted because baseband engine not activated

3 The multi stream DFE-Rx Two concurrent data streams in hardware. What is Synchronization? Finding the start of a symbol. WLAN Preamble Signal Data More data streams possible since they do not transmit all the time. All standards OFDM Copy Symbol CP Data CP Synchronization Architecture Synchronization Hardware Size of FFT Size of CP or preamble Mapped onto a reconfiguarble processing array: flexibility since multi-standard hardware reuse since sync only part of the time

4 Multi-standard OFDM time synchronization Run-time resource management 2x2 array Scenario-aware adaptive resource allocation Expandable to more streams Scenario 1: Single data stream Corr Input FIFO arg Corr FIFO & Buffer Peak Viktor Öwall: FTW 2010 Run-time resource management (II) Run-time resource management Run-time resource management (III) Scenario 1: Single data stream Scenario 1: Single data stream Scenario 2: Concurrent multi-standard data streams Computation resources: timemultiplexed. STD 1 (Corr) 1 2 Scenario 2: Concurrent multi-standard data streams Computation resources: timemultiplexed. STD 2 STD 1 (Corr) (Corr ) 1 2 Data memories: sacrificed data precision. 1 2 STD 2 (Peak) Data memories: sacrificed data precision. 1 2 STD STD 2 1 (Peak) (Pea

5 The Chip Infineon 65nm CMOS process Total area 5mm 2 and core 3.5mm 2 Pad limited: 144 Pads System infrastructure and features An array of resource cells. Heterogeneous cell array: Processing cell Memory cell Accelerator (e.g. no configuration) Hierarchical cell array. Dynamic reconfiguration Coeff. gen Addr. gen R R R R R Viktor Öwall: FTW 2010 Currently looking at channel estimation MIMO for LTE-A and Mapping strategies Alternative: ti Sign-Bit Synchronization together with Leif Huge complexity reduction at a cost of performance degradation Area improvement for memories 97% when compared to 8-bits Area improvement for logic 70% when compared to 8-bits Total Area improvement 93% when compared to 8-bits Sign-Bit Synchronization: Performance Performance Degradation. Deemed OK for coarse synchronization.

6 Multi-mode MIMO in LTE-A Different antenna configurations and modulation schemes Space Division Multiple A ccess: Increase cell spect rum efficiency Objective: unified multi-mode signal detector Needed d Resources Unified MIMO detector supporting multiple modes Integrate multiple detectors into a single module area efficiency Operations Matrix decomposition MIMO Technologies SM SDMA SD Matrix-permutation Node Selection Interference Cancellation Euclidean Distance Sorter SM using Imbalaced fixed-complexity sphere decoder SDMA using Matrix permutated fixed-complexity sphere decoder SD using Real-valued succesive interference calculation

7 Example: SDMA Unified at the architecture design level Multi-stage architecture corresponding to antennas Activate different stages according to antenna configuration 4 4 Mode Results Proposed work 65nm CMOS, other 0.13 m CMOS technology Supports the largest number ofmimo modes Consumes the least hardware and energy 2 2 Mode SoS@STMicroelectronics Life after OFDM: Faster-than-Nyquist than (FTN) FTN Signaling Original concept by J.E. Mazo in 1975 (Bell Syst. Tech. J). Main idea transmit info beyond Nyquist s criterion for ISI free transmission. Stack closer in time and/or freq induce intentional interference. Signaling Tranceivers f Viktor Öwall: FTW 2010

8 FTN Signaling Original concept by J.E. Mazo in 1975 (Bell Syst. Tech. J). Main idea transmit info beyond Nyquist s criterion for ISI free transmission. Stack closer in time and/or freq induce intentional interference. FTN Signaling Original concept by J.E. Mazo in 1975 (Bell Syst. Tech. J). Main idea transmit info beyond Nyquist s criterion for ISI free transmission. Stack closer in time and/or freq induce intentional interference. Investigate OFDM-systems due to their popularity Reuse as much as possible from a standard system Viktor Öwall: FTW 2010 f Motivation: Bandwidth efficient systems Alternative to higher order modulation Study hardware feasability Viktor Öwall: FTW 2010 FTN vs. Orthogonal system f Oth Orthogonal symbol FTN vs. Orthogonal system f Orthogonal symbol FTN symbol T F =1 T F =1 t T F <1 t

9 FTN vs. Orthogonal system f Orthogonal symbol FTN symbol FTN vs. Orthogonal system f Orthogonal symbol FTN symbol T F =1 T F =1 T F <1 t T F <1 t FTN vs. Orthogonal system f Orthogonal symbol FTN symbol Multicarrier demodulation FTN symbol reconstruction Receiver Iterative decoding T F =1 T F <1 t Viktor Öwall: FTW 2010

10 Multicarrier demodulation FTN symbol reconstruction Receiver Iterative decoding Results: Receiver performance Receiver Performance at various time spacings. Increased Bandwith efficiency, T =0.5 2x improvement from matched filter Same ER BE BER-performance is degraded from Interleaver to de-interleaver Same as in Transmitter We try to keep as much as possible from a traditional system. SNR in db Results: pre-optimization. Chip area: 05mm in ST65 nm standard cell CMOS Power: 44mW (80% in the memories) Throughput: 3.2Mbps at 300MHz. Tape-out: November 2010 FTN-signaling is deemed feasable from a hardware perspective. Complexity overhead. Memory : same order as a max-log-map implementation, (7,5) conv code. Logic: ~5 times Analog Decoding Accepted for publication in: IEEE Transactions of Circuits and System I (TCAS-I)

11 Channel decoding Channel decoding is usually performed in the digital domain: Compare to Matthias Kamuf s work. Many different types of codes,e.g. convolutional, block, turbo, LDPC, and decoding algorithms Viterbi, BCJR, Alternative: Analog decoding First introduced by Joachim Hagenauer, TU Münich, in 1998 Why analog decoders: very low power consumption less silicon area high throughput due to parallel computations Analog Decoding Detection & Synch. What does technology scaling do? Alternative Decoding Approaches D-to-A Analog Decoding Antenna Interface RF Front -End Sigma Delta A-to-D Converter Digital it Baseband Digital it Decoding Antenna Interface RF Front -End Sigma Delta A-to-D Converter Digital it Baseband Digital it Decoding System Level Control System Level Control Motivation Design the analog decoding cores for various codes. Analog decoder: analog in/digital out Most prior work has been designated as proof of concept and not system level aspects. We will investigate system level aspects of analog decoding, e.g. Can we make it fit in a traditional digital system? What is needed to do everything in analog domain? Analog Decoding Alternative Decoding Approaches Detection & Synch. D-to-A Analog Decoding Antenna Interface RF Front-End Sigma Delta A-to-D Converter Digital Baseband Digital Decoding System Level Control

12 Analog Core Module for BCJR Analog Core The structure of the core will decide the code, e.g. Hamming or tailbitingconvolutional (7,5) Short on BCJR L. R. Bahl, J. Cocke, F. Jelinek, and J. Raviv, Optimal decoding of linear codes for minimizing symbol error rate, IEEE Trans. Inform. Theory, vol. 20, no. 3, pp , Mar Example: in a circular trellis make one forward,, and one backward,, recursion. Analog Core Module used for BCJR calculations. Analog Core Module for BCJR Analog Core Module for BCJR Forward metric calculations in BCJR algorithm. Backward in the same way. Equivalent analog circuit. Forward metric calculations in BCJR algorithm. Backward in the same way. Equivalent analog circuit, Values represented as currents.

13 Analog Core Module for BCJR Analog Core Module for BCJR Forward metric calculations in BCJR algorithm. Backward in the same way. Equivalent analog circuit. Forward metric calculations in BCJR algorithm. Backward in the same way. Equivalent analog circuit. Analog Core Module for BCJR Alternative structure: digital in/digital out Forward metric calculations in BCJR algorithm. Backward in the same way. Equivalent analog circuit.

14 Decoder Output for a Single Bit Results: Analog Hamming Decoder Input interface still to be optimized. decision level 1 0 Cadence netlist simulations: Less than 4 µs is needed to decode the transmitted codeword Decision: i when circuit it converges to an steady state t Decoder Structures (8,4) Hamming block code Grand Slam at SSF! LTH have been very succesful this year and attracted three large SSF Grants: DARE Digitally Assisted Radio Evolution PI Pietro Andreani (7,5) convolutional tailbiting code Distrant - Distributed Antenna Systems PI Fredrik Tufvesson HiPEC - High Performance Embedded Computing PI Kris Kuchcinski Vi bedömer strategiskt relevans och vetenskaplig kvalitet på ansökningarna och där låg Lund bäst till i denna utlysning., Joakim Amorin, SSF

15 This last part will NOT be in the exam! Just a flavor on what we re working on