RT9611A/B. Synchronous Rectified Buck MOSFET Drivers. Features. General Description. Applications. Ordering Information

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1 Synchronous Rectified Buck MOSFET Drivers General Description The is a high frequency, synchronous rectified, single phase dual MOSFET driver designed to adapt from normal MOSFET driving applications to high performance CPU VR driving capabilities. The can be utilized under both V CC = 5V or V CC = 12V applications. The also builds in an internal power switch to replace external boot strap diode. The can support switching frequency efficiently up to 500kHz. The has the driving circuit and the driving circuit for synchronous rectified DC/DC converter applications. The driving rise/ fall time capability is designed within 30ns and the shoot through protection mechanism is designed to prevent shoot through of high side and low side power MOSFETs. The has tri-state shut down and input shut down functions which can force driver output into high impedance. The difference of the RT9611A and the RT9611B is the propagation delay, t pdh. The RT9611B has comparatively large t pdh than RT9611B. Hence, the RT9611A is usually recommended to be utilized in performance oriented applications, such as high power density CPU VR or GPU VR. The comes in a small footprint with 8-pin packages. The choice of packages type includes SOP-8, SOP-8 (Exposed Pad) and WDFN-8EL 3x3. Features Drive Two N-MOSFETs Adaptive Shoot Through Protection Embedded Bootstrap Diode Support High Switching Frequency Fast Output Rise Time Tri-State Input for Bridge Shutdown Disable Control Input Small SOP-8, SOP-8 (Exposed Pad) and 8-Lead WDFN Packages RoHS Compliant and Halogen Free Applications Core Voltage Supplies for Desktop, Motherboard CPU High Frequency Low Profile DC/DC Converters High Current Low Voltage DC/DC Converters Ordering Information Note : Richtek products are : Package Type S : SOP-8 SP : SOP-8 (Exposed Pad-Option1) QW : WDFN-8EL 3x3 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) Z : ECO (Ecological Element with Halogen Free and Pb free) Long Dead Time Short Dead Time RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 1

2 Pin Configurations (TOP VIEW) BOOT BOOT SOP-8 SOP-8 (Exposed Pad) BOOT WDFN-8EL 3x3 Marking Information RT9611xGS RT9611x GSYMDNN RT9611xGS : Product Number x : A or B RT9611xGSP RT9611x GSPYMDNN RT9611xGSP : Product Number x : A or B RT9611xZS RT9611x ZSYMDNN RT9611xZS : Product Number x : A or B RT9611xZSP RT9611x ZSPYMDNN RT9611xZSP : Product Number x : A or B RT9611AGQW 02= : Product Code RT9611BGQW 04= : Product Code 02=YM DNN 04=YM DNN RT9611AZQW 02 : Product Code RT9611BZQW 04 : Product Code 02 YM DNN 04 YM DNN 2

3 Typical Application Circuit ATX_12V C6 1000µF x 3 C7 10µF x 4 V IN ATX_12V R1 10 5V C1 1µF 4 BOOT R2 1 C2 1µF R3 2.2 R4 0 Q1 Q2 L1 1µH R5 2.2 C3 3.3nF + C4 2200µF x 2 C5 10µF x 2 V CORE Timing Diagram t pdl 90% 1.5V t pdl 1.5V 90% 1.5V 1.5V t pdh t pdh 3

4 Functional Pin Description SOP-8 Pin No. SOP-8 (Exposed Pad) / WDFN-8EL 3x3 Pin Name Pin Function 1 1 BOOT Floating Bootstrap Supply Pin for Upper Gate Driver. 2 2 Input Signal for Controlling the Driver V Supply Voltage , 9 (Exposed Pad) Output Disable. When low, both and are driven low and the normal operation is disabled. Lower Gate Driver Output. Connected to gate of low side power N-MOSFET. Ground. The exposed pad must be soldered to a large PCB and connected to for maximum power dissipation. Connect this pin to the source of the high side MOSFET and the drain of the low side MOSFET. Upper Gate Driver Output. Connected this pin to gate of high side power N-MOSFET. Function Block Diagram Internal 3.6V 15k 15k Input Disable POR Bootstrap Control Shoot-Through Protection 12k BOOT Turn Off Detection 12k Shoot Through Protection 12k 4

5 Absolute Maximum Ratings (Note 1) Supply Voltage, V to 15V BOOT to V to 15V to DC V to 15V < 200ns V to 30V DC ( 0.3V) to (V CC + 0.3V) < 200ns V to (V CC + 0.3V) (V 0.3V) to (V BOOT + 0.3V) < 200ns (V 2V) to (V BOOT + 0.3V) Input Voltage ( 0.3V) to 7V ( 0.3V) to 7V Power Dissipation, P T A = 25 C SOP W SOP-8 (Exposed Pad) W WDFN-8EL 3x W Package Thermal Resistance (Note 2) SOP-8, θ JA C/W SOP-8 (Exposed Pad), θ JA C/W SOP-8 (Exposed Pad), θ JC C/W WDFN-8EL 3x3, θ JA C/W WDFN-8EL 3x3, θ JC C/W Lead Temperature (Soldering, 10 sec.) C Junction Temperature C Storage Temperature Range C to 150 C ESD Susceptibility (Note 3) HBM (Human Body Model) kV Recommended Operating Conditions (Note 4) Supply Voltage, V ±10% Junction Temperature Range C to 125 C Ambient Temperature Range C to 85 C 5

6 Electrical Characteristics ( = 12V, TA = 25 C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Power Supply Voltage V CC V Power Supply Current I V BOOT = 12V, = 0V ma Power On Reset POR Threshold V POR V CC Rising V Hysteresis V CC_hys V Input Maximum Input Current I = 0V or 5V μa Floating Voltage V _fl V CC = 12V V Rising Threshold V _rth V Falling Threshold V _fth V Output Disable Input Rising Threshold V _rth V Hysteresis V _hys V Timing Rise Time t r V CC = 12V, 3nF load ns Fall Time t f V CC = 12V, 3nF load ns Rise Time t r V CC = 12V, 3nF load ns Fall Time t f V CC = 12V, 3nF load ns Propagation Delay Output Drive Source RT9611A t pdh V RT9611B BOOT V = 12V See Timing Diagram t pdl t pdh See Timing Diagram t pdl I sr V BOOT V = 12V V V PHAS E = 12V ns A Drive Sink R sk V BOOT V = 12V Ω Drive Source I sr V CC = 12V, V = 2V A Drive Sink R sk V CC = 12V Ω Note 1. Stresses beyond those listed Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θ JA is measured at T A = 25 C on a high effective thermal conductivity four-layer test board per JEDEC θjc is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. 6

7 Typical Operating Characteristics Drive Enable Drive Disable (20V/Div) (20V/Div) VIN = 12V, No Load VIN = 12V, No Load Time (1μs/Div) Time (1μs/Div) Rising Edge Falling Edge (20V/Div) (20V/Div) VIN = 12V, No Load VIN = 12V, No Load Time (20ns/Div) Time (20ns/Div) Dead Time Dead Time VIN = 12V, Rising, No Load Time (20ns/Div) VIN = 12V, Falling, No Load Time (20ns/Div) 7

8 Dead Time Dead Time VIN = 12V, Rising, Full Load Time (20ns/Div) VIN = 12V, Falling, Full Load Time (20ns/Div) Short Pulse Time (20ns/Div) VIN = 12V, Start Up 8

9 Application Information The is a High frequency, synchronous rectified, single phase dual MOSFET driver containing Richtek's advanced MOSFET driver technologies. The is designed to be able to adapt from normal MOSFET driving applications to high performance CPU VR driving capabilities. The can be utilized under both V CC = 5V or V CC = 12V applications which may happen in different fields of electronics application circuits. In the efficiency point of view, higher equals higher driving voltage of UG/LG which may result in higher switching loss and lower conduction loss of power MOSFETs. The choice of V CC = 12V or V CC = 5V can be a tradeoff to optimize system efficiency. The are designed to drive both high side and low side N-MOSFET through external input control signal. It has power on protection function which held and low before the voltage rises to higher than rising threshold voltage. After the initialization, the signal takes the control. The rising signal first forces the signal turns low then signal is allowed to go high just after a non-overlapping time to avoid shoot through current. The falling of signal first forces to go low. When and signal reach a predetermined low level, signal is allowed to turn high. The signal is acted as High if the signal is above the rising threshold and acted as Low if the signal is below the falling threshold. Any signal level enters and remains within the shutdown window is considered as tristate the output drivers are disabled and both MOSFET gates are pulled and held low. If left the signal floating, the pin will be kept around 1.8V by the internal divider and provide the controller with a recognizable level. pin will also turn off both high/low side MOSFETs when tied to. The builds in an internal bootstrap power switch to replace external bootstrap diode, and this can facilitate PCB design and reduce total BOM cost of the system. Hence, no external bootstrap diode is required in real applications. The difference of the RT9611A and the RT9611B is the propagation delay, t pdh. The RT9611B has comparatively large t pdh to further prevent from shoot through when high side power MOSFETs are going to be turned on. The long propagation delay of the RT9611B sacrifices efficiency for compromise of system safety. Hence, the RT9611A is usually recommended to be utilized in performance oriented applications, such as high power density CPU VR or GPU VR. Non-overlap Control To prevent the overlap of the gate drives during the pull low and the pull high, the non-overlap circuit monitors the voltages at the node and high side gate drive (-). When the input signal goes low, begins to pull low (after propagation delay). Before can pull high, the non-overlap protection circuit ensures that the monitored voltages have gone below 1.1V. Once the monitored voltages fall below 1.1V, begins to turn high. For short pulse condition, if the pin had not gone high after pulls low, the has to wait for 200ns before pull high. By waiting for the voltages of the pin and high side gate drive to fall below 1.1V, the non-overlap protection circuit ensures that is low before pulls high. Also to prevent the overlap of the gate drives during pull low and pull high, the non-overlap circuit monitors the voltage. When go below 1.1V, is allowed to go high. Driving Power MOSFETs The DC input impedance of the power MOSFET is extremely high. When V gs1 or V gs2 is at 12V or 5V, the gate draws the current only for few nano-amperes. Thus once the gate has been driven up to ON level, the current could be negligible. However, the capacitance at the gate to source terminal should be considered. It requires relatively large currents to drive the gate up and down 12V (or 5V) rapidly. It is also required to switch drain current on and off with the required speed. The required gate drive currents are calculated as follows. 9

10 V IN d1 Cgd1 Igd1 Ig1 D1 g1 Igs1 g2 s1 V g1 V +12V V g2 Cgs1 12V Ig2 Igd2 Igs2 Cgd2 Cgs2 d2 s2 L D2 V OUT Figure1. Equivalent Circuit and Associated Waveforms In Figure 1, the current I g1 and I g2 are required to move the gate up to 12V. The operation consists of charging C gd1, C gd2, C gs1 and C gs2. C gs1 and C gs2 are the capacitors from gate to source of the high side and the low side power MOSFETs, respectively. In general data sheets, the C gs1 and C gs2 are referred as C iss which are the input capacitors. C gd1 and C gd2 are the capacitors from gate to drain of the high side and the low side power MOSFETs, respectively and referred to the data sheets as C rss the reverse transfer capacitance. For example, t r1 and t r2 are the rising time of the high side and the low side power MOSFETs respectively, the required current I gs1 and I gs2, are shown as below : dvg1 Cgs1 x 12 Igs1 = Cgs1 = (1) dt tr1 dvg2 Cgs1 x 12 Igs2 = Cgs1 = (2) dt tr2 Before driving the gate of the high side MOSFET up to 12V (or 5V), the low side MOSFET has to be off; and the high side MOSFET is turned off before the low side is t t turned on. From Figure 1, the body diode D 2 had been turned on before high side MOSFETs turned on. dv 12 Igd1 = Cgd1 = C gd1 (3) dt tr1 Before the low side MOSFET is turned on, the C gd2 have been charged to V IN. Thus, as C gd2 reverses its polarity and g 2 is charged up to 12V, the required current is : dv Vi + 12 I C C gd2 = gd2 = gd2 (4) dt tr2 It is helpful to calculate these currents in a typical case. Assume a synchronous rectified buck converter, input voltage V IN = 12V, V g1 = V g2 = 12V. The high side MOSFET is PHB83N03LT whose C iss = 1660pF, C rss = 380pF, and t r = 14ns. The low side MOSFET is PHB95N03LT whose C iss = 2200pF, C rss = 500pF and t r = 30ns, from the equation (1) and (2) we can obtain : I I gs1 gs x 10 x 12 = = (A) x x 10 x 12 = = 0.88 (A) x 10 from equation. (3) and (4) x 10 x 12 Igd1 = = (A) x 10 ( ) x 10 x Igd2 = = 0.4 (A) x 10 (5) (6) (7) (8) the total current required from the gate driving source can be calculated as following equations : ( ) I = I + I = = (A) (9) g1 gs1 gd1 ( ) I = I + I = = 1.28 (A) (10) g2 gs2 gd2 By a similar calculation, we can also get the sink current required from the turned off MOSFET. Select the Bootstrap Capacitor Figure 2 shows part of the bootstrap circuit of the RT9611A/ B. The V CB (the voltage difference between BOOT and on ) provides a voltage to the gate of the high side power MOSFET. This supply needs to be ensured that the MOSFET can be driven. For this, the 10

11 capacitance C B has to be selected properly. It is determined by following constraints. V CC BOOT Figure 2. Part of Bootstrap Circuit of In practice, a low value capacitor C B will lead to the over charging that could damage the IC. Therefore, to minimize the risk of overcharging and to reduce the ripple on V CB, the bootstrap capacitor should not be smaller than 0.1μF, and the larger the better. In general design, using 1μF can provide better performance. At least one low ESR capacitor should be used to provide good local de-coupling. It is recommended to adopt a ceramic or tantalum capacitor. Power Dissipation To prevent driving the IC beyond the maximum recommended operating junction temperature of 125 C, it is necessary to calculate the power dissipation appropriately. This dissipation is a function of switching frequency and total gate charge of the selected MOSFET. BOOT V IN C B Figure 3. Test Circuit + V CB - Figure 3 shows the power dissipation test circuit. C L and C U are the and load capacitors, respectively. The bootstrap capacitor value is 1μF. C BOOT 10 1µF 12V 12V 1µF 5V C L 3nF 2N7002 2N7002 C U 3nF 20 Figure 4 shows the power dissipation of the as a function of frequency and load capacitance. The value of C U and C L are the same and the frequency is varied from 100kHz to 1MHz. Power Dissipation vs. Frequency Power Dissipation (mw) C 800 U = C L = 3nF C U = C L = 2nF C U = C L = 1nF Frequency (khz) Figure 4. Power Dissipation vs. Frequency The operating junction temperature can be calculated from the power dissipation curves (Figure 4). Assume V CC = 12V, operating frequency is 200kHz and C U = C L = 1nF which emulate the input capacitances of the high side and low side power MOSFETs. From Figure 4, the power dissipation is 100mΩ. Thus, for example, with the SOP-8 package thermal resistance θ JA is 120 C/ W. The operating junction temperature is calculated as : T J = (120 C/W x 100mW) + 25 C = 37 C (11) where the ambient temperature is 25 C. Thermal Considerations For recommended operating condition specifications of the, the maximum junction temperature is 125 C and T A is the ambient temperature. The junction to ambient thermal resistance, θ JA, is layout dependent. For SOP-8 packages, the thermal resistance, θ JA, is 120 C/ W on a standard JEDEC 51-7 four-layer thermal test board. For SOP-8 (Exposed Pad) packages, the thermal resistance, θ JA, is 75 C/W on a standard JEDEC 51-7 four-layer thermal test board. For WDFN-8EL 3x3 packages, the thermal resistance, θ JA, is 70 C/W on a standard JEDEC 51-7 four-layer thermal test board. The 11

12 maximum power dissipation at T A = 25 C can be calculated by the following formulas : P D(MAX) = (125 C 25 C) / (120 C/W) = 0.833W for SOP-8 package P D(MAX) = (125 C 25 C) / (75 C/W) = 1.333W for SOP-8 (Exposed Pad) package P D(MAX) = (125 C 25 C) / (70 C/W) = 1.429W for WDFN-8EL 3x3 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θ JA. The derating curves in Figure 5 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. Maximum Power Dissipation (W) SOP-8 Four-Layer PCB SOP-8 (Exposed Pad) WDFN-8EL 3x Ambient Temperature ( C) Figure 5. Derating Curve of Maximum Power Dissipation Layout Consideration Figure 6 shows the schematic circuit of a synchronous buck converter to implement the. The converter operates from 5V to 12V of input Voltage. V IN 12V V CORE C3 L1 + + C1 Q1 L2 Q2 C2 1 BOOT 4 CB PHB83N03LT 5 6 PHB95N03LT Figure 6. Synchronous Buck Converter Circuit 12V When layout the PCB, it should be very careful. The power circuit section is the most critical one. If not configured properly, it will generate a large amount of EMI. The junction of Q1, Q2, L2 should be very close. Next, the trace from, and should also be short to decrease the noise of the driver output signals. signals from the junction of the power MOSFET, carrying the large gate drive current pulses, should be as heavy as the gate drive trace. The bypass capacitor C4 should be connected to directly. Furthermore, the bootstrap capacitors (C B ) should always be placed as close to the pins of the IC as possible. 5V R1 C4 12

13 Outline Dimension A H M J B F I C D Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A B C D F H I J M Lead SOP Plastic Package 13

14 A H M EXPOSED THERMAL PAD (Bottom of Package) J Y X B F I C D Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A B C D F H I J M Option 1 Option 2 X Y X Y Lead SOP (Exposed Pad) Plastic Package 14

15 D D2 L E E2 1 SEE DETAIL A e b A A1 A3 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A A A b D D E E e L W-Type 8EL DFN 3x3 Package (0.5mm Lead Pitch) Richtek Technology Corporation 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863) Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. 15