Diode Bridge Rectifier with Improved Power Quality Using Capacitive Network

Transcription

1 Diode Bridge Rectifier with Improved Power Quality Using Capacitive Network Sagar Gupta Cypress Semiconductor Technology India Pvt. Ltd. Karnataka, India Nimesh V, Vinod John Department of Electrical Engineering Indian Institute of Science Bangalore, Karnataka, India Abstract Widely distributed single-phase power electronic rectifier loads are increasing source of harmonics in power distribution system. These harmonics have many well known adverse impacts on the power system. So it is necessary to improve the power quality of the rectifiers. This paper presents a novel single phase rectifier in which capacitors are used in parallel with diodes in one leg of the rectifier. A general analytical model of the proposed topology is obtained. The closed form expressions for the rectifier waveforms helps in parameter selection that leads to optimal performance in terms of input current THD. A comparative study of different topologies of rectifiers are done in terms of input voltage, current waveform distortion, output dc voltage ripple, and desired target for dc output voltage. The proposed topology reduces the total harmonic distortion from 45 percent in normal rectifier to 63 percent while maintaining voltage ripple less then.3 percent. The proposed topology keeps dc bus ripple small while simultaneously providing better THD. The passive components considered for improving harmonic injection are small capacitors. The additional cost required for the proposed rectifier is low, the proposed rectifier also has a higher efficiency than the other commonly used topologies. I. INTRODUCTION Non-linear loads such as controlled and uncontrolled, single phase and three phase rectifiers injects considerable amount of lower order harmonics into the grid and distorts the voltage at point of common coupling [], []. Harmonics cause excessive heating, pulsating and reduced torque in motors and generators, increased heating and voltage stresses in capacitor, malfunction of switch gears and relays and reduces the life of products [3], [4]. It is therefore necessary to reduce harmonic in electric power system. Also in case of dc loads it is important to get low ripple in output dc voltage for its proper functioning [5]. So it is necessary to provide dc output at low ripple keeping the harmonics injected in the line to a reasonable low value. Passive Front End (PFE rectifiers followed by Power Factor Correction (PFC stage, and Active Front End (AFE rectifiers maintains dc bus voltage at desired level and harmonics injected, at switching frequency, can be filtered out using first order filters [6], [7], [8]. Using the above mentioned topologies, for low power applications such as LED lighting, increases the cost as it requires active switches such as MOS- FET or IGBT and additional sensors, for controlling dc bus This work was supported by CPRI, Ministry of Power, Government of India, under the project Power conversion, control, and protection technologies for microgrid /6/$3. 6 IEEE Fig.. Rectifier topologies Diode rectifier with capacitive output filter Voltage doubler rectifier Split capacitor full bridge rectifier. TABLE I IEC 6-3- HARMONIC LIMITS FOR CLASS C EQUIPMENTS FOR INPUT POWER < 5 W Harmonic (n Limit(% of the fundamental input current voltage and input current[9]. So for lower power applications PFE rectifier circuits, diode rectifier with capacitive filter, as shown in Fig., and voltage doubler rectifier with two split capacitances, as shown in Fig., are preferred. It is well known that diode rectifier with capacitive filter, as shown in Fig., has negligible output voltage ripple but injects significant amount of lower order harmonics into the grid. Voltage doubler, shown in Fig., has low harmonic injection when C s is kept small but ripple in output voltage is considerably high. According to IEC 6-3-, equipments are classified in 4 categories, Class A, Class B, Class C and Class D. Lighting equipments, whose front end is a rectifier, falls into Class C and harmonic standards for these equipments is summarized in Table I. In this paper a new Split Capacitor Full Bridge (SCFB rectifier is proposed. The proposed SCFB rectifier shown in Fig. is suited for low power applications. SCFB rectifier is a combination of diode rectifier with capacitive filter and voltage doubler topology. Initial simulation studies comparing the three topologies shown in Fig. is summarized in section

2 TABLE II VALES AND PARAMETERS CONSIDERED FOR THE STUDY (A BASE VALUES (B RECTIFIER PARAMETERS Parameter V b P b f b I b Z b L b C b Base Value 34 V 5 W 5 Hz ma 464 Ω 4.7 H nf Parameter Value(per unit V g 4 V (.7 P o 5 W ( R L 5 kω (.8 L mh (36 µ R g 5 Ω (.8 m II. The analytical closed form expressions for waveforms are covered in section III and Appendix. The equations for waveforms of SCFB rectifier that are derived in this paper are used for circuit optimization. This leads to circuit parameters that meet tight dc voltage ripple requirement while simultaneously having minimum input voltage distortion. Section IV details analytical, simulation and experimental results. This section also covers the effects of line inductance and load capacitance in optimal values split capacitor and THD of line current drawn, section V concludes the paper. II. SIMULATION STUDIES Initially simulations on all three topologies, shown in Fig. was carried to check the performance of the proposed model. Per unit values and design specifications of the converter used for simulation are given in Table II and II respectively. P o, V g, f s = 5 Hz, R L L g, R g are rated power, grid voltage rms, grid frequency, line impedance and load resistance, respectively. With line impedance neglected, effects of variations in values of load capacitance, C L, and split capacitance, C s, in grid current THD and ripple in output voltage is studied. Summary of the results in tabulated in Table. III. It can be observed that the proposed SCFB topology has the advantages of both the normal rectifier with low output voltage ripple, and voltage doubler circuit with lesser distortion in line current drawn. III. ANALYSIS OF SCFB RECTIFIER Fig. shows the split capacitor full bridge (SCFB rectifier and its operating modes. The grid is modeled as a sinusoidal voltage source v g in series with line impedance consisting of R g and L in series. The load is modeled as a resistor(r L. For modeling of the topology different modes of operation are identified and the governing equations of these modes are covered in this section. The analysis is carried out for positive half cycle of v g. Conducting elements of in each mode is shown as dark black shade and the non-conducting elements are in light black shades, as shown in Fig.. The main assumptions for this analysis are: Diodes are assumed ideal. ESR of the capacitances have been ignored. 3 Ratio V o /V o. A. Mode-I from t < t < t In Mode-I, during positive half cycle of the grid supply diode D starts conducting, at t = t. At t = t, v c (t = V = V g (t, v c (t = V, i L (t = and v (t = v c (t + v c (t. The governing equations for circuit shown in Fig. can be written as, v g (t = i L R g + L di L i dt + V ( v (t = i R R L = C L dt + C s i c dt + V + V ( During this mode, upper split capacitor (v c (t charges from grid and lower split capacitor(v c (t discharges into load and grid. This mode ends when either diode D stops conducting, current drawn from grid goes to zero, or v c (t has fallen to zero. B. Mode-II from t < t < t 3 Mode-II starts at t when diode D starts conducting that is v c (t = and D is already conducting. Let v c (t = V mii and i L (t = I L. Fig. shows the equivalent circuit and the equations for this mode can be written as, v g (t = i L R g + L di L i dt + V mii (3 v (t = i R R L = C L dt + C s i c dt + V mii (4 As diode D is conducting, this ensures that the lower split capacitor does not charge in opposite direction, so v C (t in this mode will remain zero. This mode ends when diode D stops conducting, that is current drawn from the grid dies down to zero. C. Mode-III from t 3 < t < t 4 Mode-III occurs when the current i L reaches zero at the end of Mode-I with v c (t and v c (t >. In this case time t 3 equals to the instant t which is the end of Mode-I. In this mode, no diodes are conducting, therefore the current from the grid is zero and load is supplied by the energy stored in capacitors, C L C s. At t = t 3, let v C (t 3 = V miii and TABLE III COMPARISON OF STANDARD RECTIFIER, VOLTAGE DOUBLER AND SCFB RECTIFIER WITH VARIATION OF C s AND CL Topology (Normal Rectifier Topology (Voltage Doubler Topology 3 (SCFB Rectifier C s(µf(pu C L (µf(pu V o(v(pu V (V(pu THD(% V o(v(pu V (V(pu THD(% V o(v(pu V (V(pu THD(% (3.6 ( (..9 (8.5 m (.3 4 ( (. 3.5 ( ( ( (..4 (4. m (.4 78 ( (.. (5.9 m 34 (.5 k ( (..8 (7.5 m (.7 35 (.7 34 (..4 (4. m 63 (3.3 k (9. 34 (..3 (.9 m (. 3 ( (..6 (4.7m 65 x 6 (3.3 M ( (..9 (8.5 m (..4 (4. m (..3 (3.8 m 458

3 Fig.. Different modes of operation for the SCFB rectifier Mode-I, Mode-II, Mode-III, and (d Mode-IV. (d Fig. 3. Circuit performance as a function of load capacitance and split capacitance showing Percentage total harmonic distortion Output voltage ripple V o and Average output voltage V o. v C (t 3 = V miii. Equivalent circuit for this mode is shown in Fig., governing equations for this mode is, v (t = i R R L = v C (t + v C (t (5 v (t = (V miii + V miii e (t t3/τ (6 τ = C L + C s / R L (7 D. Mode-IV from t 4 < t < T + t Mode-IV occurs at the end of Mode-II when i L reaches with v C (t =. Hence time t 4 matches with time t 3 of Mode-II. In this diode D is conducting and load is supplied by energy stored in capacitors C L C s. Let Mode-IV start at t 4 and v C = V miv, the equivalent circuit is shown in Fig. (d and the governing equations are given by, v (t = i R R L = v C (t (8 v (t = V miv e t t 4 τ (9 τ = C L + C s R L ( The solutions of above mentioned differential equations for mode-i and mode-ii is given in the Appendix. Analytical expressions in (6, (9, (, (6 and (8 provide expressions for the capacitor voltage waveforms in terms of the circuit parameters. All remaining voltages and currents in the circuit can be obtained from these capacitor voltages. For an input voltage of V g = 4 V and load resistance of R L = 5 kω(load power of around W, the effect of variations in C L and C s on THD, V o and V o is shown in Fig. 3. From these results it is seen that minimum THD is obtained when C s =.647 µ F for a particular value of C L and the value of C L is chosen such that V o is less than V and it is 47 µ F. It can also be observed, from Fig. 3 that the minimum of the THD is not significantly affected by C L. It can also be seen from Fig.3 that low values of C L leads to high ripple in the dc bus voltage. Also Fig. 3 shows that larger values for C s lead to increase in the average dc bus voltage. From Fig. 3, it can be concluded that by choosing a specific value of split capacitance(c s,minimum THD injection can be obtained of a particular load. Also Fig. 3 shows that output voltage ripple are mainly controlled by load capacitance(c L, so THD and output voltage ripple can be controlled independently. For small value of split capacitor(c s < µf, v c (t falls to zero before diode D stops conducting in positive half cycle of supply then we get Mode-I followed by Mode-II and finally Mode-IV. In this case Mode I starts at t =. For this mode, v g and i L, v c and v c, and

4 (d (e (f Fig. 4. Analytical Results for different modes of operation, Cs = µf (a, b, c and for Cs = 3 µf (d, e, f: (a, d Grid voltage, vg and current drawn from grid, il (t, in per unit. (b, e Voltage across upper split capacitor, vc (t and lower split capacitors, vc (t. (c, f Output voltage Vo. Fig. 5. Comparison of input voltage and current waveforms Results from analytical model Results obtained from simulation Experimental measurements: Grid voltage(ch: V/div, 5: probe and current(ch: ma/div. Vo are shown in Figs. 4,,, respectively. For large value of split capacitor(cs > µf, diode D stops conducting before vc (t falls to zero in positive half cycle of supply. In this case Mode-I followed by Mode-III. Also, in this case the start of Mode-I is at t 6=. For this case, vg and il, vc and vc, and Vo are shown in Figs. 4(d, (e, (f, respectively. It is observed from analysis, simulation and experiments that selection of capacitance parameters such that the initiation of Mode-III immediately after Mode-I leads to minimum source current THD. Fig. 5 shows the supply voltage and supply current for L = mh Rg = 5Ω Cs =.65µF CL = 47µF RL = 5Ω. For RL = 5Ω, Cs =.65µ is the lowest point of THD injection. IV. A NALYTICAL, S IMULATION AND E XPERIMENTAL R ESULTS Analysis, simulation and detailed experimental studies are performed the proposed topology shown in Fig.. Design ratings of the converter are covered in section II. Effects of line inductancel and load capacitance CL in optimal split capacitance Cs and THD in line current is also discussed in this section. Fig. 5 shows the grid voltage and current drawn from the grid. Analytical results, shown in Fig.5, simulation TABLE IV H ARMONIC A NALYSIS OF L INE C URRENT OF SCFB R ECTIFIER FOR Pout = 3 W Harmonic Order Fundamental(5 Hz 3rd 5th 7th 9th th 3th 5th 7th 9th Total THD Analytical (.56A Experimental (.575A results, shown in Fig. 5, and experimental results, shown in Fig. 5, matches closely. THD of the current drawn from the grid for analytical, simulation and experimental are 66.7%, 66.7% and 6.5% respectively. Table. IV summarizes the harmonics, up to 95 Hz. This meets the IEC 6-3 requirements specified in Table. I. The small deviation in experimental measured THD is due to the non zero resistances of the diodes and rectifier, which also shows in terms of the reduced oscillations in the waveform. Efficiency of SCFB

5 (d Fig. 6. Variation of C s with L, Variation of THD with L, Variation of C s with C L, (d Variation of THD with C L. rectifier is measured to be 99.36% and that of diode rectifier in Fig. is 98.9% in experimental studies. A. Effect of Line Inductance Values of line inductance(l varies from few µh to few mh. Effect of variations in L on C s is shown in Fig. 6. It can be seen that values C s decreases with increase in L. For a particular value of C s =.65µF, effect of L on line current THD is shown in Fig. 6. In the circuit shown in Fig., line current THD decreases with increase in L, but in SCFB rectifier the increase in L affects slowly and increase in THD level. B. Effect of Load Capacitance The ripple in output voltage decreases as the optimal load capacitance C L increases. Effect of variations in C L on C s is shown in Fig. 6. It can be seen that this value of C s remains a constant for C L greater than µf. For a particular value of C s =.65µF, the effect of C L in line current THD is shown in Fig. 6(d. As opposed the topology shown in Fig., in SCFB rectifier the line current THD remains almost a constant for higher values of load capacitance C L. So the value of C L is chosen to be 47 µf to so that voltage ripple is within a desirable limit. V. CONCLUSION In this paper a SCFB rectifier is proposed to reduce the harmonic injection in the line by using capacitive components. Two capacitances(x rated are used to affect the input line current so that input line current harmonics are reduced. The analytical modeling of the new topology is systematically performed. The results are verified with simulation results and experimental results. The analytical model is used to find the value of capacitances(c s for which minimal line current THD can be obtained for a particular load. Also it is shown that ripple in output voltage can be independently controlled by load capacitance(c L. The proposed rectifier circuit also operates with a higher efficiency compared to standard rectifiers. A. Mode-I from t < t < t The equations ( & and ( in Section III A form a fourth order system. The roots of the characteristic equation are solved assuming well separated circuit poles[5]. v c (t = V m ωny[a 4 e yt + B 4 cosωt + C 4 ω t + ( D e ξωnt 4 sin(ω dt + φ + E 4 d t ] ξ ω d ( +V e yt yωnv B [A 5 e yt +e ξωnt 5 sin(ω dt + φ ξ where, ω n = y = R L (C s + C L + C s R g R L LC s (C s + C L + C 5 ω d d t ] ( ( R L (C s + C L + C s R g (3 LC s + RC s R g (C s + C L ξ = LC s R L (C s + C L [R L (C s + C L + C s R g ] (4 ω d = ω n ξ, φ = tan ξ (5 ξ and, A 4 B 4 C 4 D 4 E 4 = P C L R L t C L R L ωcosωt + t ωcosωt A 5 B 5 = N LC s C 5 C s R g C L R L APPENDIX For a rectifier most important thing to be known are its output voltage for it output characteristics, and line current to know it input performance. Equations which are obtained by analysis in Mode-I and Mode-II are solved here to get V and i L.

6 ξω n ξω n + y y P = ω + ωn ωn + ξω n y ξω n + y ω y ξω n ω ωny ωn + ξω n y ωny ω ωnω ωny ωny A B = N ξω n LC s ωny C ωn( yc s R g A 3 = N B 3 C 3 ξω n LC s ω ny ω nyr L C L where, N is given by N = ξω n y ωn y i L (t R g + L di(t dt = v g (t v o (t + v C (t (7 The solutions for v o (t in ( and v c (t in (6 is used to evaluate i L (t in (7. B. Mode-II from t < t < t 3 v o (t = V m(r L + R g R L L(C L + C s [A 6cosωt + B 6 ω t + C 6 e pt + D 6 e qt ]+ i L (t (R L + R g [ e pt e qt ] + V mii R L (q p(c L + C s R g e pt + e (p + q qt + L (e pt e qt (q p (8 where, v (t = R L C s V m ωny[a e yt + B cosωt + C ω t + p = L + R LR g (C L + C s + ( LR L (C L + C s D e ξωnt sin(ω dt + φ + E d t ] ξ ω d ( L + R LR g (C L + C s [ ] LR L (C L + C s R L + R g LR L (C L + C s +V A e yt + e B ξωnt sin(ω dt + φ + C d t ξ ω d [ ] q = L + R LR g (C L + C s +V A e yt + e B ξωnt sin(ω dt + φ + C LR L (C L + C s d t ξ ω d ( L + R LR g (C L + C s (6 LR L (C L + C s R L + R g LR L (C L + C s where, A6 A B6 B C D = P C6 = Q t t D6 ωcosωt ωcosωt where, E where Q = p + q q p pq p + q ω ω pq ω q ω p i L (t R g + L di(t dt = v g (t v o (t (9 Knowing the grid voltage and V o (t in (8, the input current i L (t is solved in Mode-II. The expressions for source current and output voltage are used to obtain THD and voltage design trade off relationship shown in Fig. 3. REFERENCES [] T. M. Blooming and D. J. Carnovale, Application of ieee std harmonic limits, in Pulp and Paper Industry Technical Conference, 6. Conference Record of Annual. IEEE, 6, pp. 9. [] B. Singh et al., A review of single-phase improved power quality AC- DC converters, IEEE Trans. Ind. Electron., vol. 5, no. 5, pp , Oct. 3. [3] A. Mansoor, W. Grady, A. Chowdhury, and M. Samotyi, An investigation of harmonics attenuation and diversity among distributed single-phase power electronic loads, in Transmission and Distribution Conference, 994., Proceedings of the 994 IEEE Power Engineering Society. IEEE, 994, pp. 6. [4] M. Chen, Z. Qian, and X. Yuan, Frequency-domain analysis of uncontrolled rectifiers, in Applied Power Electronics Conference and Exposition, 4. APEC 4. Nineteenth Annual IEEE, vol.. IEEE, 4, pp [5] R. W. Erickson and D. Maksimovic, Fundamentals of power electronics. Springer Science & Business Media, 7. [6] J. Rodríguez et al., PWM regenerative rectifiers: State of the art, IEEE Trans. Ind. Electron., vol. 5, no., pp. 5, Feb. 5. [7] A. Prasad et al., An active power factor correction technique for threephase diode rectifiers, IEEE Trans. Power Electron., vol. 6, no., pp. 83 9, Jan. 99. [8] B. Ooi et al., An integrated AC drive system using a controlled-current PWM rectifier/inverter link, IEEE Trans. Power Electron., vol. 3, no., pp. 64 7, Jan [9] D. C. Lee and D. S. Lim, AC voltage and current sensorless control of three-phase PWM rectifiers, IEEE Trans. Power Electron., vol. 7, no. 6, pp , Oct..