Strain Gauge and Load Cell Amplifier/Data-Acquisition with Ethernet, USB, and Serial (DCSGB1000)

Transcription

1 Strain Gauge and Load Cell Amplifier/Data-Acquisition with Ethernet, USB, and Serial (DCSGB1000) 1 APPLICATIONS Strain gauge measurement Load cell measurement Bridge sensor amplifier Thermistor measurement General differential amplifier 2 FEATURES Flexible interface options: Serial (RS- 232), USB, and Ethernet - all standard Free Tacuna Systems interface software Easy system configuration Tabular and graphical display Data logs to.csv file 24 bit sigma delta ADC Offset drift: 5 nv/ C Precision gain (up to 0.001% tolerance after calibration) Gain drift: 1 ppm/ C Adjustable excitation: V Optional AC excitation to remove DCinduced offset errors Programmable gain (1 to 128x) Output data rate up to 4.8 khz (single channel only) Simultaneous 50 Hz/60 Hz rejection Programmable calibration offset Programmable noise elimination filters Flexible on-board bridge completion resistor options (sold separately) Through hole Surface mount (0805 package) Prototyping DIP socket (pluggable) Profile (5.5 x 3.5 ) Rev. 1.1 Preliminary 1 August 17, 2012

2 3 DESCRIPTION The DCSGB1000 is a low noise, complete analog front end for high precision measurement applications - specifically designed for strain measurement. Featuring Ethernet capabilities, the DCSGB1000 is an accurate and precise solution to your single point measurement and acquisition needs. This device provides a data access point for measuring up to two channels of strain gauges, load cells, thermistors, or generic analog inputs. The DCSGB1000 is capable of interfacing with Ethernet, USB, or RS232. The DC- SGB1000 accepts or completes a maximum of two Wheatstone bridges arranged in quarter, half, or full bridge configuration. In full bridge mode, it can also accept a standard load cell. Gain, offset adjustment, and noise filtering are controlled programmably via an outlined protocol. Additionally, this board can be interfaced directly with LabVIEW or other data acquisition system for simplified control and graphical interface. The DCSGB1000 uses an on-board programmable differential amplifier, 24bit analog to digital converter, and digital filtering to offer industry leading precision and accuracy. Furthermore, the DCSGB1000 is unique because it can optionally employ AC bridge excitation. When active, this feature virtually eliminates dc-induced offset error providing exceptional accuracy. 4 ELECTRICAL SPECIFICATIONS The electrical specifications for the DCSGB1000 are listed in the table below. Table 1: Electrical Specifications Parameter Min Typ Max Unit Supply Voltage (DC) V Supply Current 500 ma ADC Resolution 24 bit Output Data Rate (1Ch) 4800 Hz Output Data Rate (2Ch) 2400 Hz Gain Error % CMMR db Excitation (Adjustable) V Rev. 1.1 Preliminary 2 August 17, 2012

3 5 PINOUT Input Signal Header Connectors J2 and J6 are used for pluggable screw terminals to connect a strain gauge network or load cell. Table 2: Pinout - Input Signal Header Pin Name Description Ch:0 Ch:1 - - J6:1 J2:1 Shield GND connection for shield termination J6:2 J2:NC REF IN(+) 6 Wire Load Cell Reference Supply (referenced to Ch 0) J6:3 J2:NC REF IN(-) 6 Wire Load Cell Reference Return (referenced to Ch 0) J6:4 J2:4 V E (+) Excitation Supply J6:5 J2:5 V E (-) Excitation Return J6:6 J2:6 S+ Positive sense J6:7 J2:7 S- Negative sense J6:8 J2:8 3Wire Third wire for quarter bridge config Auxiliary Signal Header Connector P1 is used for auxiliary functions, such as interfacing to a microcontroller, extra analog inputs, and alternate power configurations. Rev. 1.1 Preliminary 3 August 17, 2012

4 Table 3: Pinout - Auxiliary Signal Header Pin Name Description 1 LL TX TTL level TX from internal microcontroller. Used to interface to another serial device s RX line with 0-5 V levels. 2 LL RX TTL level RX from internal microcontroller. Used to interface to another serial device s TX line with 0-5 V levels. 3 LL CTS TTL level CTS from internal microcontroller. Used to interface to another serial device s RTS line with 0-5 V levels. This is only used for optional hardware handshaking. 4 LL RTS TTL level RTS from internal microcontroller. Used to interface to another serial device s CTS line with 0-5 V levels. This is only used for optional hardware handshaking. 5 +Power This line is connected directly to the input power connector center pin V This line is connected directly to the +5 V voltage regulator. This line can power a low current external device (<100 ma). Alternatively, this pin can accept a regulated +5 V power source to power the board. 7 AN3 This is an optional 10 bit ADC input. 8 AN4 This is an optional 10 bit ADC input. 9 AinCOM This is an optional common reference to the 10 bit ADC. 10 GND Connected directly to board ground. Rev. 1.1 Preliminary 4 August 17, 2012

5 Rev. 1.1 Preliminary 5 August 17, BLOCK DIAGRAM Ch. 0 Differential Inputs Ch. 1 Differential Inputs Bridge Excitation AA Filter AA Filter AA Filter AA Filter Temp Sensor DC/AC Adjustable Excitation MUX PGA Internal/ External Ref In Sigma-Delta ADC Figure 1: DCSGB1000 Functional Block Diagram Level Converter Serial Interface and Microcontroller RS-232 Interface Logic Level RS-232 Interface Mini-USB Interface Ethernet Interface

6 7 PROGRAMMABLE CONTROL Data, gain, filtering, and other features are accessed and controlled via Ethernet, USB, or serial command interfaces. All commands are simple text based commands outlined in Section 7.1. These commands allow the DCSGB1000 to respond to single sample requests or stream (burst mode) data to the host PC or microcontroller (PC console shown in Figure 2). For most applications, the user will not need in-depth knowledge of each feature or mode of the unit, but for more demanding applications, the user has access to the full host of registers on the DCSGB1000. These registers are covered in Section 7.2. Figure 2: DCSGB1000 With Terminal Commands In the most basic scenario, the user should be able to plug in the amplifier and collect data using the default settings. The recommended terminal interface is PuTTY ( See Section 7.3 for interface connection options. Once installed and configured to connect to the DCSGB1000, the console application will accept simple text commands. Data will be returned by the DCSGB1000 according to the command given. The console commands and return values for this most basic scenario are outlined as follows: R0# Rev. 1.1 Preliminary 6 August 17, 2012

7 This basic command instructs the amplifier read channel 0. The amplifier returns with a value of with a status value of 0. The status 0 means no errors for channel 0 (while the status 1 means no errors for channel 1). See Section for status register definition. Another example is to collect continuous samples on the enabled channels until told to stop. In this example we will set more values of the amplifier (described below). The commands and return values for this scenario are outlined as follows: C2# G4# F0480# B1# B0# First, enable both channels with C2# (setting channels is required by burst mode not for read mode). G4# sets gain to 16x. F0480# sets the filter to 480 which produces clean signals with a data rate of 2.5 Hz (see Section for filter rate calculations). B1# enables burst mode. The amplifier returns data with the last integer reporting the status and channel for the sample. Burst mode is stopped by sending B0#. Most console applications allow the user to capture a log of the output. This can be employed to obtain a text based output of the session data. Tacuna Systems also offers a free Ethernet based GUI for use with the DCSGB1000. Please see the product page for more information. Alternatively, the user can program their own microcontroller or PC interface. 7.1 DCSGB1000 Command Set The DCSGB1000 uses the following basic commands to configure and operate the various functions provided. Variables Reg, Data, Ch, and Status designate decimal numbers with the number of characters sent or returned in parenthesis. Rev. 1.1 Preliminary 7 August 17, 2012

8 Table 4: DCSGB1000 Setting Command Set Function Syntax Description AC Excitation AData(1)# Sets amplifier in AC excitation and chop mode according to Data (0=Off, 1=On). Example: A1# will turn on AC excitation and chop, A0# will turn it off. Burst BData(1)# Sets amplifier in burst (streaming) mode according to Data (0=Off, 1=On). When set in burst mode, data will continuously be sent from the amplifier at the OutputDataRate according to section Example: B1# will turn on burst mode, B0# will turn it off. Channel Select CData(1)# Sets amplifier active channels for burst mode (Single channel reads, eg.r0#, are not impacted by this setting). Data = 0, turns on channel 0. Data = 1, turns on channel 1. Data = 2, turns on both channels. When both channels are active, data is streamed from the amplifier alternating channels. Example: C2# will turn on both channel 0 and 1. Filter Select FData(4)# Sets amplifier filter and corresponding OutputDataRate according to section Example: F1023# will turn on maximum filtering. Gain GData(1)# Sets amplifier gain according to the gain register in table 9. Example: G4# set the amplifier with 16x gain. Set Register SReg(1)Data(8)# Sets amplifier register with corresponding Data in decimal. This can be used as an alternative to the other commands if the user wishes to set more than one feature at a time. See Table 7 for register and Data length details. Example: S # will set the amplifier with the sinc 4 filter, 60Hz filter, and FS=1023 (maximum filtering). Filter Type TData(1)# Sets sinc 3 filter on. When Data = 0, sinc 4 filter is active. Example: T1# will turn on sinc 3 filter, T0# will turn on sinc 4 filter. Calibrate XData(1)# Performs device calibration depending on Data. Data = 0 performs internal zero-scale calibration, Data = 1 performs internal full-scale calibration, Data = 2 performs system zero-scale calibration, Data = 3 performs systems full-scale calibration. See section 7.4 for more information. Example: X0# will perform internal zero-scale calibration. Rev. 1.1 Preliminary 8 August 17, 2012

9 Table 5: DCSGB1000 Reading Command Set Function Syntax Return Format Description Read AUX/Ex ADC ICh(1)# Data(4) Returns channel reading of excitation voltage or one of the auxiliary ADC inputs. Data = 0, returns ADC value of excitation voltage. Data = 1 or 2 returns AUX ADC input ADC values. These values are 10 bit numbers (0-1023) with a 6.6 V reference. To convert to a voltage, use ADCV oltage = (Data/1024) 6.6V Example: I0# will return the bridge excitation voltage. An example return value would be 0781: ADCV oltage = (781/1024) 6.6V = 5.034V. These values are provided as a convenience. To ensure utmost accuracy, excitation voltage should be read by a quality DVM to be used in strain calculations. Read Data RCh(1)# Data(8)Status(1) Returns channel reading and status in decimal. Example: R0# will return the reading on channel 0 with the status of the reading appended (see Section 7.1.1). An example return value would be , which is a data value of with a status of 0. Query Register (0-2) QReg(1)# Data(8) Returns contents of amplifier register in decimal. With the exception of register 3 which is shown below. Example: Q1# will return the contents of register 1. The default return value would be Query Register (3) QReg(1)# Data(8)Status(1) Returns contents of amplifier data register and status in decimal. Example: Q3# will return the contents of the data register with the status of the reading appended (see Section 7.1.1). Rev. 1.1 Preliminary 9 August 17, 2012

10 7.1.1 Data Status When data is sent from the DCSGB1000, the status of the data is appended to the end of the reading in the form of a decimal number (0-9). To extract the ADC data from the status numeral, simply integer divide the number by 10 or use a left(8) function. This will leave the ADC data without the status numeral. The remaining number should treated as a binary status indicator. ie. Convert the number to binary to read the status of each bit. Multiple status bits can be enabled at once, eg. Channel 0 and Input buffer overrun bits can be set indicating there is a buffer overrun on Channel 0. The meaning of the status numeral is shown in Table 6 below in binary. Table 6: DCSGB1000 Status Numeral Codes Status Numeral Bit Description 0 Channel indicator: 0 = Channel 0, 1 = Channel 1 1 Input buffer overrun. 0 = No error, 1 = Input buffer overrun. ADC ready to send data, microcontroller busy. Note: output data will have missing samples. The data sent is valid, however some samples were lost, causing a temporal gap. 2 Output buffer overrun. 0 = No error, 1 = Output buffer overrun. Microcontroller ready to send data, interface busy. Note: output data will have missing samples. The data sent is valid, however some samples were lost, causing a temporal gap. 3 Timing mismatch. 0 = No error, 1 = Timing mismatch. When both channels are enabled, samples sent alternate between channels. If the microcontroller detects successive samples from the same channel, one or more samples were lost. The data sent is valid, however some samples were lost, causing a temporal gap. 7.2 DCSGB1000 Registers The DCSGB1000 has several user configurable registers to set gain, data rate/filtering, ac excitation, and chop mode. The register summary is shown in Table 7 with default values in parenthesis. Further detail is shown in the subsequent tables. Rev. 1.1 Preliminary 10 August 17, 2012

11 Table 7: DCSGB1000 Register Summary Register Reg Default Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit Mode SINC3(0) REJ60(1) FS9(1) FS8(1) FS7(1) FS6(1) FS5(1) FS4(1) FS3(1) FS2(1) FS1(1) FS0(1) CHOP(0) ACX(0) Config CH1(0) CH0(1) G2(0) G1(0) G0(0) D23 D22 D21 D20 D19 D18 D17 D16 Data 3 - D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Each register is described in detail in the following tables. Rev. 1.1 Preliminary 11 August 17, 2012

12 Table 8: DCSGB1000 Mode Register Detail Bit Location Bit Name Description Mode 23 to Mode 21 0 These bits must be programmed with a Logic 0 for correct operation. Mode 20 to Mode 19 1 These bits must be programmed with a Logic 1 for correct operation. Mode 18 to Mode 16 0 These bits must be programmed with a Logic 0 for correct operation. Mode 15 SINC3 Sinc 3 filter select bit. When this bit is cleared, the sinc 4 filter is used (default value). When this bit is set, the sinc 3 filter is used. The benefit of the sinc 3 filter compared to the sinc 4 filter is its lower settling time. For a given output data rate, f ADC, the sinc 3 filter has a settling time of 3/f ADC while the sinc 4 filter has a settling time of 4/f ADC when chop is disabled. The sinc 4 filter, due to its deeper notches, gives better 50 Hz/60 Hz rejection. At low output data rates, both filters give similar rms noise and similar no missing codes for a given output data rate. At higher output data rates (FS values less than 5), the sinc 4 filter gives better performance than the sinc 3 filter for rms noise and no missing codes. Mode 14 to Mode 11 0 These bits must be programmed with a Logic 0 for correct operation. Mode 10 REJ60 This bit enables a notch at 60 Hz when the first notch of the sinc filter is at 50 Hz. When REJ60 is set, a filter notch is placed at 60 Hz when the sinc filter first notch is at 50 Hz. This allows simultaneous 50 Hz/ 60 Hz rejection. Mode 9 to Mode 0 FS9 to FS0 Filter output data rate select bits. The 10 bits of data programmed into these bits determine the filter cut-off frequency, the position of the first notch of the filter, and the output data rate for the part. In association with the gain selection, they also determine the output noise (and, therefore, the effective resolution) of the device (see Table 6 through Table 17). See Section for further details. Rev. 1.1 Preliminary 12 August 17, 2012

13 Table 9: DCSGB1000 Config Register Detail Bit Location Bit Name Description Config 23 CHOP Chop enable bit. When the CHOP bit is set, chop is enabled. When chop is enabled, the offset and offset drift of the ADC are continuously removed. However, this increases the conversion time and settling time of the ADC. For example, when FS = 96 decimal and the sinc 4 filter is selected, the conversion time with chop enabled equals 80 ms and the settling time equals 160 ms. With chop disabled, higher conversion rates are allowed. For an FS word of 96 decimal and the sinc 4 filter selected, the conversion time is 20 ms and the settling time is 80 ms. However, at low gains, periodic calibrations may be required to remove the offset and offset drift. When ac excitation is enabled, chop must be enabled also. Config 22 ACX AC excitation enable bit. If the signal source to the amplifier is ac excited, this bit must be set to 1. For dc-excited inputs, this bit must be 0. The bit CHOP must be set to 1 when ac excitation is enabled. Config 21 to Config 10 0 These bits must be programmed with a Logic 0 for correct operation. Config 9 to Config 8 CH1 to CH0 Channel select bits. These bits are used to select which channels are enabled on the amplifier. More than one channel can be selected. Config 7 0 This bit must be programmed with a Logic 0 for correct operation. Config 6 0 This bit must be programmed with a Logic 0 for correct operation. Config 5 0 This bit must be programmed with a Logic 0 for correct operation. Config 4 1 This bit must be programmed with a Logic 1 for correct operation. Config 3 0 This bit must be programmed with a Logic 0 for correct operation. Gain select bits. Sets gain and range as follows: G2 G1 G0 Gain ADC Input Range ±5 V Reserved Config 2 to Config 0 G2 to G Reserved ±625 mv ±312.5 mv ±156.2 mv ± mv ±39.06 mv Rev. 1.1 Preliminary 13 August 17, 2012

14 7.2.1 Filtering and Data Rates The DCSGB1000 uses a digital filter to eliminate measurement noise. Two filters are available on the unit, sinc 3 and sinc 4. The distinction between the two is that the sinc 4 filter offers greater noise attenuation at the cost of lengthier conversion time when both channels are enabled. When converting on a single channel with chop disabled, there is no difference between data rates when using either filter. When using high output data rates (FS values less than 5), the sinc 4 filter gives better performance than the sinc 3 filter for rms noise and no missing codes. Additionally, the sinc 4 filter provides better 50 Hz/60 Hz noise rejection. The 3 db frequency for the sinc 3 filter is equal to: f 3dB = F S (1) The 3 db frequency for the sinc 4 filter is equal to: f 3dB = F S (2) As previously mentioned, the output data rate is tied to the filter selection value (F S). The OutputDataRate is the maximum rate at which data can be sent from the DCSGB1000 while streaming or reading individual samples. When streaming, the unit will send continuous samples at the frequency specified by OutputDataRate. When reading individual samples, 1000 Hz is the fastest the DCSGB1000 will respond to read requests. If OutputDataRate is slower than 1000 Hz, the unit will only respond to read requests as fast as OutputDataRate allows. The method to calculate OutputDataRate is shown below. When chop is disabled, OutputDataRate = 4800 F S N (N CH 1) F ILT (3) where F S is the decimal equivalent of the code in Bit FS0 to Bit FS9 and is in the range 1 to N CH is the number of channels enabled and N F ILT is the order of the filter (Sinc 3 : N F ILT =3, Sinc 4 : N F ILT =4. This results in an output data rate from 4.69 Hz to 4.8 khz. With chop disabled, the first notch frequency is equal to the output data rate when converting on a single channel. Rev. 1.1 Preliminary 14 August 17, 2012

15 When chop is enabled, OutputDataRate = 4800 F S N F ILT N CH (4) again, where F S is the decimal equivalent of the code in Bit FS0 to Bit FS9 and is in the range 1 to N CH is the number of channels enabled and N F ILT is the order of the filter (Sinc 3 : N F ILT =3, Sinc 4 : N F ILT =4. With chop enabled, the first notch frequency is equal to N F ILT OutputDataRate. The chopping introduces notches at odd integer multiples of (OutputDataRate/2). 7.3 Interface Connection Options Serial Interface The serial interface uses RX and TX lines with no flow control by default. It operates at bps and can be used with many terminal applications made for Windows, Linux, and Mac OS. Additionally, it can be connected to a microcontroller with RS-232 levels or TTL levels (see Auxiliary Signal Header Table 3) USB Interface The USB interface uses a serial port emulator for Windows. The driver is available at... Once the driver is installed and the board connected, Windows will recognize the device as a standard serial port. Any baud configurations available are valid. Use any terminal application to communicate with the DCSGB Ethernet Interface To be completed Calibration The DCSGB1000 provides four calibration modes. These modes are internal zero-scale calibration, internal full-scale calibration, system zero-scale calibration, and system full-scale calibration. A calibration consists of first a zero-scale followed by a full-scale calibration. They must proceed in this order. A calibration can be performed when the device is not in burst mode. An internal calibration is automatically performed when the gain is changed. However, for increased accuracy, the user may perform a system calibration after each gain change or upon system startup. Rev. 1.1 Preliminary 15 August 17, 2012

16 After each conversion, the ADC conversion result is scaled using the ADC calibration registers before being written to the data register. The offset calibration coefficient is subtracted from the result prior to multiplication by the full-scale coefficient. During an internal zero-scale or full-scale calibration, the respective zero input and fullscale input are automatically connected internally to the ADC input pins. A system calibration, however, expects the system zero-scale (V E ) and system full-scale (V E +) voltages to be applied to the ADC pins (S and S+ respectively) before initiating the calibration mode. In this way, errors external to the ADC are removed. 8 OUTPUT CODING To use the DCSGB1000, the user will record the raw digitized values then convert these values to meaningful units. The raw data from the DCSGB1000 is the result of the 24 bit analog to digital converter. This digital number depends on the reference voltage, input voltage, and amplification. This section will explain the relationships such that the user can calculate the output for strain gauge applications. The DCSGB1000 relates the input voltage to a digital number as: ( ) Data Out = 2 23 Vin Gain + 1 V ref (5) This relationship allows the unit to output values for positive and negative relative inputs. For example, with the inputs shorted: ( ) 0 1 Data Out = = (6) 5 the output is at half of the full scale output of 2 24 or With an input of +(V ref /2), the output of the amplifier is at full scale: ( ) Data Out = = (7) 5 Obviously, to convert this output value to a signed number (centered at 0), simply subtract from the output. 9 BRIDGE CONFIGURATION The bridge can be configured in many ways and can be completed by on board bridge completion resistors. To complete the bridge you can use 0805 surface mount resistors or standard through hole resistors placed in the DIP socket shown in the board diagram. Rev. 1.1 Preliminary 16 August 17, 2012

17 Rev. 1.1 Preliminary 17 August 17, 2012

18 The simplified schematic of the bridge completion circuit is shown below, the two types of resistors (surface mount and through hole are wired in parallel). Shielded wire should be used to minimize EM noise. 9.1 Interal/External Reference The DCSGB1000 offers the ability to use an internal or external bridge excitation reference on Channel 0 (Channel 1 uses the same reference as Channel 0). The significance of an external reference is that the amplifier can detect the excitation voltage level at the sensor (full bridge or load cell), compensating for voltage drop errors in the excitation lines. This feature increases overall system accuracy at the expense of adding two additional signal wires. However, if this feature is not required, the unit has the option of using the internal excitation voltage as a reference source. Using the internal reference, no wires should be connected to pins J6:6 or J6:7. To enable/disable this feature, both jumpers, P2 and P3 must be configured as shown in Figure 3. (a) Internal Reference (b) External Reference Figure 3: Internal and external excitation reference jumper locations. Rev. 1.1 Preliminary 18 August 17, 2012

19 The following subsections outline the various bridge configurations and contain simplified output equations. These equations do not take into account bridge nonlinearity, temperature effects, etc. More detailed analysis can be found through manufacturer s websites, such as Vishay Precision Group. 9.2 Quarter Bridge Quarter bridge utilizes the three wire configuration to minimize the effect of wire resistance. In addition all three bridge completion resistors are required. V S, quarter = V EGF ɛ 4 (8) Rev. 1.1 Preliminary 19 August 17, 2012

20 9.3 Half Bridge Half bridge only uses the two left side bridge completion resistors. V S, half = V EGF ɛ 2 (9) Rev. 1.1 Preliminary 20 August 17, 2012

21 9.4 Full Bridge A load cell or a full bridge require no completion resistors. V S, half = V E GF ɛ (10) Rev. 1.1 Preliminary 21 August 17, 2012

22 10 TROUBLSHOOTING No LED power indication Check power requirements, the supply voltage requires a minimum voltage of 7 V and a maximum of 15 V along with a minimum of 500 ma of current. Saturated low or high output signal Saturated high Check that Wheatstone bridge is well balanced, if not use shunting resistors to correct any errors. Check if amplification gain is too high, using correct MSB to LSB orientation. Progressively high gain requires a further balanced Wheatstone to prevent saturation. Saturated low Check that Wheatstone bridge is well balanced, if not use shunting resistors to correct any errors. Check if amplification gain is correct, using correct MSB to LSB orientation. Progressively high gain requires a further balanced Wheatstone to prevent saturation at low or high rails. Rev. 1.1 Preliminary 22 August 17, 2012

23 11 NOTES Tacuna Systems and the Tacuna Systems logo are trademarks of Tacuna Systems LLC. All other trademarks are the property of their respective owners. Tacuna Systems reserves the right to make changes or discontinue without notice to any product, documentation and/or services at any time. Parameters and information provided by and through Tacuna Systems can vary in different applications and actual performance may vary over time. All parameters, including typicals must be validated for each customer application by customer s technical experts. No representation or warranty is given and no liability is assumed by Tacuna Systems with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Tacuna Systems assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using Tacuna systems products or products sold by Tacuna systems. No license is granted by implication or otherwise under any patent or patent rights, copyrights, or intellectual property rights of Tacuna Systems. Tacuna Systems products are not designed, intended, or authorized for use in medical applications or other applications intended to support or sustain life, or for any other application in which the failure of the Tacuna Systems product could create a situation where personal injury or death may occur. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety related requirements concerning their products and any use of Tacuna Systems products in such safety critical applications, notwithstanding any applications related information or support that may be provided by Tacuna Systems. Buyer shall indemnify and hold Tacuna Systems and its owners, officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Tacuna Systems was negligent regarding the design or manufacture of the part. Tacuna Systems products are neither designed nor intended for use in military/aerospace applications or environments. Buyers acknowledge and agree that any such use of Tacuna Systems products is solely at the Buyer s risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. Tacuna Systems products are neither designed nor intended for use in automotive applications or environments. Buyers acknowledge and agree that any such use of Tacuna Systems products is solely at the Buyer s risk, and that they are solely responsible for compliance with all requirements in connection with such use. Rev. 1.1 Preliminary 23 August 17, 2012