Rajesh S. Bansode Assistant professor, TCET Kandivali, Mumbai

Transcription

1 ISSN: X All Rights Reserved 2014 IJARECE 1142 Implementation of MIMO- 8x8 OFDM simulink model to enhance channel capacity and its realization using FPGA veritex 5 Devashree H. Patil ME Student, TCET Kandivali, Mumba Rajesh S. Bansode Assistant professor, TCET Kandivali, Mumbai Geeta H. Karande ME Student, TCET Kandivali, Mumbai ABSTRACT Orthogonal frequency division multiplexing (OFDM) which is multi carrier communication technique can be used for wireless communication as it has the property to overcome channel fading. While multiple inputs multiple outputs (MIMO) is the technique of implementing multiple antennas at the transmitter as well as receiver side to increase the data rates as well as efficiency of the system. The MIMO-OFDM is combined in order to increase spectrum efficiency, speed, channel capacity, reliability of the wireless communication system. In this paper 8 8 SM-OFDM system models are designed. The performance of the systems is measured with respect to BER and Throughput results & the applications of this system is also demonstrated using QPSK modulations by processing text message as an input. The modeling of the MIMO-OFDM system was carried out in MATLAB followed by Verilog HDL implementation. The VHDL code is written and simulated in XILINX 14.7 and tested using FPGA VIRTEX 5 XC5VLX50T. Keywords Orthogonal frequency division multiplexing (OFDM), Multiple input multiple output (MIMO), Spatial Multiplexing (SM), Field programmable gate array (FPGA), Register transistor level (RTL). 1. INTRODUCTION Orthogonal Frequency Division Multiplexing (OFDM) is a transmission technique which ensures efficient utilization of the spectrum by allowing overlap of carriers. OFDM is a combination of modulation and multiplexing that is used in the transmission of information and data. With the increasing traffic for the wireless communication the need for the more efficient use of the spectrum available holds the key. The 4G communication system are also peeping their head out in developed countries like USA and UK. It is expected to have higher data rates, high spectral efficiency. To achieve this data rate careful selection of multicarrier modulation scheme is required. Many multiple access techniques like FDMA, TDMA, CDMA, WCDMA, OFDMA, etc have come up. Among this OFDM is the new technique which has many applications, advantages has compared to other technique. But has biggest drawback of peak to average power ratio (PAPR).This drawback can be reduced using various PAPR reduction methods [1]-[3]. MIMO can be used to overcome the channel fading problem as well as to increase the gain. The spatial multiplexing is used to increase the transmission rate as well as increases the number of transmit-receive antenna pairs. By taking the advantage of MIMO and OFDM, a transceiver can be implemented using FPGA virtex-5. Simulation results are obtained using MATLAB. 1.1 Implementation of simulink model of OFDM with FPGA OFDM has been recognized as an outstanding method for high-speed cellular data communication where its implementation relies on very high-speed digital signal processing. OFDM system can be implemented using various techniques like ASIC, one of the fastest method. But have the disadvantage of inflexibility and longer time to market. Another method is by using microprocessor, but it requires larger peripherals. One of the best techniques among the other two is by using FPGA. In this paper, by taking the advantage of OFDM & MIMO a system has been implemented to get the data rates up to several hundred Mbps. The first step will be verification of each block using matlab. After the algorithm is verified, the hardware implementation will be obtained by constructing block diagram in Simulink. Then a VHDL code will be imported into Simulink via Xilinx system generator block set which will generate bit true and cycle accurate hardware model. The resultant hardware model will be programmed into FPGA virtex-5 prototyping board [4]. The maximum digilent USB JTAG cable frequency that can be fed to the Virtex-5 FPGA board is 30 MHz. The number of subcarriers chosen is Cyclic prefix chosen is 25% of the number of subcarriers used. Modulation schemes used are QPSK along with rician modulation techniques. The data rate achieved is 960 Mbps. The Virtex-5 is rated at clock speeds of 550 MHz [5].

2 ISSN: X All Rights Reserved 2014 IJARECE Simulink model for OFDM system Simulink model of OFDM system this model implements a simple OFDM transmitter and receiver. The simulink model of OFDM system is shown above in Fig.1 Data Source:-This block is used to generate frame based input data where no. of subcarriers transmitted are Modulator/Mapper: - This block is used to modulate the input data stream using QPSK. The signal constellation specified for the QPSK is [1,-1,j,-j]. The modulated output is then demultiplexed by serial to parallel converter. OFDM Modulator:-This block basically consists of IFFT block that computes inverse fast fourier transform of the input data. The IFFT operation is mathematically identical to OFDM operation. Hence it could be said that this is the block that actually implements OFDM. Before feeding the data samples to the IFFT block, the input data stream should be formatted so that the total numbers of input samples are a power of 2 as is required by the IFFT block. Transmission Channel: - In order to model the actual transmission channel both the Rician and Rayleigh fading channels are connected in series. The signal to noise ratio of the Rician channel can be adjusted by varying the SNR parameter value. The rayleigh fading block provides additional parameters like Doppler shift, path delay gain etc to make the channel resemble the actual channel as closely as possible. OFDM Demodulator:-This operation performed by this block is basically opposite to that performed by the OFDM modulator block. At first the cyclic prefix is removed by using a remove cyclic prefix block and then FFT block is used to find the fast fourier transform of the data samples. Finally select rows block is once again used to remove the pilot samples added and output the exact data samples. Fig.1: Block diagram of OFDM transreceiver Simulink model I-Q Demapper / Demodulation:- This block demodulates the input data using quadrature amplitude demodulation method. The constellation for this block was set to [ i i i i]. Finally the ouput integer samples are converted to bits using an integer to bit converter block to facilitate the computation of BER. Data Detector / Output:- The data is sent to a data detector. But in actual block this will be processed by the Communication systems. The sink block computes the BER and displays them. It also displays the time domain signal and frequency domain signal of OFDM through vector scope and spectrum scope respectively [6]-[7]. 3. Introduction to FPGA An FPGA is a type of integrated circuit (IC) that can be programmed for different algorithms after fabrication. Modern FPGA devices consist of up to two million logic cells that can be configured to implement a variety of software algorithms. Although the traditional FPGA design flow is more similar to a regular IC than a processor, an FPGA provides significant cost advantages in comparison to an IC development effort and offers the same level of performance in most cases. Another advantage of the FPGA when compared to the IC is its ability to be dynamically reconfigured. This process, which is the same as loading a program in a processor, can affect part or all of the resources available in the FPGA fabric. The architecture of the modern SRAM-based FPGA devices comprises logic blocks (LB) symmetrically organized in a matrix of rows and columns, with routing channels round it [8]. These channels contain a certain number of programmable links, interconnecting the logic blocks are shown in Fig.2

3 ISSN: X All Rights Reserved 2014 IJARECE 1144 performance compared to previous generations of programmable logic. Block RAM modules provide flexible 36 Kbit true dual port RAM that are cascadable to form larger memory blocks. In addition, Virtex-5 FPGA block RAMs contain optional programmable FIFO logic for increased device utilization. Each block RAM can also be configured as two independent 18 Kbit true dual-port RAM blocks, providing memory granularity for designs needing smaller RAM blocks. Fig.2 FPGA architecture of matrix structure 3.1 Architecture of Xilinx Virtex-5 FPGA The architecture constitutes of several blocks such as Clock management, block select RAM source, I/O blocks enabled multiplier, programmable interconnect and configurable logic blocks.these blocks are now explained one by one. Refer to Fig Cascadable embedded DSP48E slices with 25 x 18 two s complement multipliers and 48- bitadder/subtracter/accumulator provide massively parallel DSP algorithm support. In addition, each DSP48E slice can be used to perform bitwise logical functions. Clock Management Tile (CMT) blocks provide the most flexible, highest-performance clocking for FPGAs. Each CMT contains two Digital Clock Manager (DCM) blocks (selfcalibrating, fully digital), and one PLL block (self calibrating, analog) for clock distribution delay compensation, clock multiplication/division, coarse- /fine-grained clock phase shifting, and input clock jitter filtering[8]-[9]. 4. Design Methodology 4.1 Software and hardware Tools used MATLAB Simulink 2013, Xilinx ISE 14.7 Model Sim 6.3 are required to build the system model to check for its operation and performance evaluation. Virtex-5 FPGA genesys prototyping board, JTAG USB cable. Power supply. 4.2 Matlab simulink Fig.3: Xilinx FPGA Architecture Virtex-5 devices are user-programmable gate arrays with various configurable elements and embedded cores optimized for High-density and high-performance system designs. Virtex-5 devices implement the following functionality. I/O blocks provide the interface between package pins and the internal configurable logic. Most popular and leading-edge I/O standards are supported by programmable I/O blocks (IOBs). The IOBs can be connected to very flexible Chip Sync logic for enhanced source-synchronous interfacing. Source-synchronous optimizations include per-bit deskew (on both input and output signals), data serializers/deserializers, clock dividers, and dedicated I/O and local clocking resources. Configurable Logic Blocks (CLBs), the basic logic elements for Xilinx FPGAs, provide combinatorial and synchronous logic as well as distributed memory and SRL32 shift register capability. Virtex-5 FPGA CLBs are based on real 6-input look-up table technology and provide superior capabilities and The MATLAB environment is a high-level technical computing language for algorithm development, data visualization, data analysis and numerical computing. One of the key features of this tool is the integration ability with other languages and third-party applications. MATLAB also included the Simulink graphical environment used for control theory, digital signal processing, multi-domain simulation and model-based design. Signal processing designers take advantage of Simulink as it offers a good platform for preliminary algorithmic exploration and optimization. Simulink is integrated with MATLAB and data can be easily transferred between the programs. 4.3 Methodology The below figure depicts a methodology diagram which shows the design flow starting with matlab and lastly downloaded on FPGA virtex-5. The first step is to develop algorithm of each block by using Matlab. Then it design the architecture for MIMO-OFDM model using simulink library and Xilinx design tools. The next step is to generate code using system generator. RTL and HDL code design is carried out accordingly. Moreover, the module operation is tested by functional co-simulation by combining Simulink with Model Sim. VHDL code can also be imported into Simulink via the Xilinx System Generator block set, which gives flexibility to the design flow. Simulink and Xilinx System Generator create bit-true and cycle-accurate

4 ISSN: X All Rights Reserved 2014 IJARECE 1145 hardware models which can be programmed into FPGA prototyping boards. The device is then configured and downloaded to FPGA. Hardware-in-the loop co-simulation is carried out by combining Simulink with System Generator so as to execute final hardware debugging and verification. The Xilinx Integrated Software environment (ISE) is used as the synthesizer in the design flow diagram. Model Sim can also be used to verify the hardware simulation of the blocks by using test vectors generated by the System Generator or HDL test benches. The complete test bench can be build up in a shorter period of time with traditional HDL Fig.6: QPSK mapper The output of encoder/interleaver module is applied as input to the Mapper. The data_in is passed through serial to parallel then that parallel data is provided to ROM-Imag, ROM_Real and BER_Tx. All this blocks are combined altogether to form QPSK mapper. The ROM_Imag provides the value on imaginary axis while ROM_Real provides the value on real axis. This is giving up the points on different quadrants. The Scope is provided at output to measure BER. 5.1 Variation in data rate Fig.4:Methodology Diagram 5. Design implementation and analysis The main purpose of this project is implementing a MIMO OFDM model and to achieve higher data rates in accordance with increase in sampling frequency Fs. Data rates up to 960 Mbps have been achieved. The hardware co-simulation, RTL Schematics, Test Bench and VHDL codes, are also obtained for the implemented 8 x8 MIMO OFDM model to verify the same. 1. Fs and Ts variables appear at the MATLAB workspace. Fs and Ts are the sampling frequency and Sample period at the input side respectively. Sampling rate at the transmitter side can be changed by using these two parameters as shown below. Fig.5: Transmitter module The transmitter subsystem is shown in Fig. 5-2.This subsystem consists of data _in, encoder, Rician Fading, Mapper, parser, and OFDM output blocks. Fig. 7: Fs and Ts values in MATLAB Workspace

5 ISSN: X All Rights Reserved 2014 IJARECE At the input, by default the sampling frequency is 4Khz as shown in workspace and Sample period is Ts = 1/Fs The data rate at the transmitter can be seen with the help of sample time block as shown below. SR,No. Table 1 Increase in Data Rate with increase in sampling frequency Input Sampling Frequency Transmitter sampling frequency Data rate 1 700K 20 MHz 168 Mbps 2 890K 27 MHz 213 Mbps 3 1.1M 33 MHz 264 Mbps 4 1.8M 54 MHz 432 Mbps M 69 MHz 552 Mbps M 84 MHz 672 Mbps 7 3 M 90 MHz 720 Mbps M 95 MHz 768 Mbps 9 4M 120 MHz 960 Mbps Fig. 8: Sample Time Block The simulink model for input text message is shown in Fig.1 The Text message is as follows: My name is Devashree Hemant Patil. After running the simulink model for input text message the matlab window will display output as shown in Fig.11 Fig. 9: Ts display on probe in Sample Time Block 3. The sample time at the transmitter as shown in Figure 6.3 is Ts = e-009. The sampling frequency at the transmitter is Fs = 1/Ts = 1/ e-009 = 120 MHz i.e. 120 Mbps 4. To change the Sampling frequency at the transmitter to 120 MHz set the Fs = 7MHz And put Ts = 1/Fs at the input side in the MATLAB workspace and run the model as shown below. Fig.11: Output of enter text message on Matlab window Fig.10: Setting Fs and Ts values Fig. 12: Received and Original text message Signal

6 ISSN: X All Rights Reserved 2014 IJARECE RTL Schematic In digital circuit design, register-transfer level (RTL) is a design abstraction which models a synchronous digital circuit in terms of the flow of digital signals (data) between hardware registers and the logical operations performed on those signals. Register-transfer-level abstraction is used in hardware description languages (HDLs) like Verilog and VHDL to create high-level representations of a circuit, from which lower-level representations and ultimately actual wiring can be derived. Design at the RTL level is typical practice in modern digital design. Fig. 14: RTL Schematic inside mimo8_cw Test benches After developing algorithm through system model matlab and simulink library.xilinx software use high level tool like USB- JTAG FPGA configuration circuitry for designing high performance as well as provides system modelling and automatic code genereation. This generated VHDL codes will generate test benches when downloaded on FPGA virtex- 5.The Virtex - 5 FPGA Genesys Kit board is shown below Fig. 13: RTL Schematic When designing digital integrated circuits with a hardware description language, the designs are usually engineered at a higher level of abstraction than transistor level or logic gate level. In HDLs the designer declares the registers (which roughly correspond to variables in computer programming languages), and describes the combination logic by using constructs that are familiar from programming languages such as ifthen-else and arithmetic operations. This level is called register-transfer level. The term refers to the fact that RTL focuses on describing the flow of signals between registers. Double click on the image to see inside it. Fig.15: Virtex- 5 FPGA genesys board After running program of JTAG co - simulation for text message shown in above figure and cabling digilent USB of JTAG with JTAG co simulation of simulink library. After burning of kit the red LED glows which indicate successful run of program with respect to kit. The successful test benches will be generated on monitor. The test benches are depicted in below Fig. 17

7 Fig. 16: JTAG Co simulation for input text message Fig. 17: Test Bench generated for text message transmitted through the simulink model 5.4 VLSI implementation results on ISE design suite 14.7 The design is implemented on Xilinx Virtex 5 genesys Prototyping board. The synthesis report is shown below. The device utilization summary is mentioned in below Table 2. It indicates number of slice register is required in larger number as compared to LUTs, IOB etc. and Table 3. Shows mimo8x8_cw project status. The design summary shows that the proposed design utilizes 1543 (5%) number of slice registers, 436 (1%) number of slice LUTs, 317 (19%) number of LUTs-FF pairs, 140 (29%) number of bounded IOBs, 1 (3%) number of BUFG and 2 (4%) number of DSP48Es are the estimated values for Xilinx ISE 14.7 design suite. ISSN: X All Rights Reserved 2014 IJARECE 1148

8 Table 2 Device Utilization summary Xilinx ISE is a complete FPGA logic-synthesis and optimization tool. Xilinx ISE can create optimized FPGA netlists from VHDL code. Synthesis is the process of converting the abstract circuit behavior, described by a VHDL (or any HDL) code, into a hardware implementation in terms of logic gates. The below Table 3 gives information regarding project status like module name, product version,design goal, parser errors etc. Project File: Module Name: Target Device: Table 3 mimo8x8_cw project status mimo8x8_cw Project Status mimo8x8_c w.xise mimo8x8_c w xc5vlx50t- 3ff1136 Parser Errors: Implement ation State: Errors: No Errors Synthesized No Errors ACKNOWLEDGMENTS This work is in part supported by my project guide Prof. Rajesh Bansode. I thank him for his helpful suggestions and comments, which improved the quality of work. I would also like to express my gratitude to ME co-ordinator Prof. Vinitkumar Dongre for his guidance. CONCLUSION OFDM systems are the solution to our ever increasing data rate needs. The simulink model developed is further modeled using Verilog HDL, the developed model is simulated using ModelSim and synthesized using Xilinx ISE for FPGA implementation. A more complete testbench can be build up in a shorter period of time with traditional HDL. When the HW module is verified, a final synthesis report for the HDL codes will be generated by Design Compiler. As all the process can be performed in Matlab/Simulink, the developing cost is reduced and time is saved. Product Version: ISE 14.7 Warnings: 1134 Warnings (727 new) References Design Goal: Balanced Routing Results: [1] L.J. Cimini, Analysis and Simulation of a Digital Mobile Channel Using Orthogonal Frequency Division Multiplexing, IEEE Transactions On Communications, Vol. com-33, NO. 7, July 1985, ~ Design Strategy: Xilinx Default (unlocked) Timing Constraint s: [2] University of Alberta, MIMO History. Retrieved on September28, 2009 from Environment: System Settings Final Timing Score: [3] K. Baum, B. Classon and P. Sartori, Principles of Broadband OFDM Cellular SystemDesign, Hoboken, NJ: John Willey & Sons, [4] K. C. Chang, G E Sobelman, FPGA Based Design of a Pulsed-OFDM system," in IEEE Jour /2006. [5] K. F. Lee, D B William, "A space-frequency transmitter diversity technique for OFDM systems," in Proc. Globecom 03, San Francisco, USA, vol.3, pp.24-28, ISSN: X All Rights Reserved 2014 IJARECE 1149

9 [6] Foschini G J, Gans M J, On limits of wireless communication in a fading environment when using multiple antennas, Wireless Personal Communication, vol. 6, no 3, Sep 1998, pp [10] Shahid Abbas, Student Member, IEEE, Waqas Ali Khan, Talha Ali Khan and Saba Ahmed OFDM Baseband Transmitter Implementation Compliant IEEE Std d on FPGA2009 [7] L.Hanzo, M.Munster, B.J.Choi and T.Keller, OFDM and MC-CDMA for Broadband Multiuser Communication, WLANs and Broadcasting, IEEE press, Wiley. [8] I. Kuon and J. Rose. Measuring the gap between FPGAs and ASICs. IEEE Transactions On Computer-Aided Design of Integrated Circuits and Systems, 26(2): , Feb [9] Virtex-5 Xtreme DSP Design Considerations User Guide. Xilinx, Inc., San Jose, CA, ISSN: X All Rights Reserved 2014 IJARECE 1150