Contribution to the Smecy Project

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Reynard Sparks
5 years ago
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1 Alessio Pascucci

2 Contribution to the Smecy Project Study some performance critical parts of Signal Processing Applications Study the parallelization methodology in order to achieve best performances on present and future Multicore Architectures Intel Multicore Processors Many Core processors proposed by SMECY Partners (ST P2012) IBM Cell Processor Define a General Parallelization Methodology for the study of applications parallelization on multicore architectures

3 STAP Signal processing technique applied to Radar signal in order to simultaneously cancel Clutter and Jammer signal interferences Clutter: interfering unwanted echoes due to the surface of the sea or land and weather. Clutter is rejected by means of signal processing techniques operating in time domain. Jammer: intentional and deliberate transmission of signals for the purpose of degrading the reception of radar signals. Jamming is rejected by means of signal processing operating in space (phased array antennas) domain. Space-Time Adaptive Processing (STAP), operating in space-time domain, allows the simultaneous cancellation of clutter and jamming via the computation of a 2D cancellation filter.

4 Optimum weight In order to best detect the presence of a signal S, samples expected by the target, we must design a filter which is "tuned to" S in order to minimize the effects of noise and interference. We must maximize the signal-to-noise ratio that is equivalent to a maximization of the probability of detection. Output of the STAP filter is the scalar y = W o * X. Where W o are the optimum weights which maximize the output signal to noise ratio. S / N E y M E NN H 2 Var y W H S W H MW Where M is the Noise Covariance Matrix 2 Maximizing the signal to noise ratio, we obtain the optimum weights: W o = M -1 S

5 Application of STAP to phased array RADAR RADAR has an array of L antennas. K echoes from a transmitted train of K coherent pulses PRT (Pulse Repetition Time) Antennas elements 1 2 L CUT 1 2 K PRT DATA CUBE X Range cells Doppler Processing (FFT) Covariance matrix M estimation (M) The output signal is provided by the linear combination of the LK echoes x with weights w. Linear combination of weights and signals from the cell under test (CUT)) Weight calculation W = M -1 S Adapted Output X (dimension LKx1) is the collection of the LK echoes in a range cell. S, the space-time steering vector, is the collection of the LK samples expected by the target. Data Cube X is tipically composed by about 1000 matrices 512x512

6 Weights Computation Phase Requires the resolution of a linear system in form Ax = b A = Covariance Matrix previously computed b = Steering Vector x = weights vector

7 Linear System Resolution Matrix Factorization: split the original square matrix in 2 triangular matrices and then solve the 2 linear systems Cholesky Factorization for Hermitian Positive Definite Matrix Different versions of sequential algorithm available Different versions of the algorithms may express different performances on a parallel architecture

8 1. for (j=0; j<n; j++) { The Traditional Algorithm 2. sum = 0; 3. for (k=0; k<j; k++) { 4. sum += (L[j][k]) 2 ; 5. } 6. L[j][j] = sqrt( A[j][j]-sum ); 7. for (i=j+1; i<n; i++) { 8. sum=0; 9. for (k=0; k<j; k++) { 10. sum += L[i][k]*L[j][k]; 11. } 12. L[i][j] = (A[i][j] - sum)/l[j][j]; 13. } 14. }

9 Block Version of the Algorithm for K = 1, NB L(K,K) = Chol( A(K,K) ) for I = K+1, NB L(I,K) = A(I,K) * L(K,K) -T endfor LAPACK_CPOTF2 BLAS_CTRSM for J = K+1, NB * L(J,K) T endfor L(J,J) = L(J,J) - L(J,K) * L(J,K) T for I = K+1, J A(I,J) = A(I,J) - L(I,K) BLAS_CHERK BLAS_CGEMM endfor endfor

10 Differences between the versions Differences in memory access pattern Different performances in terms of sequential completion time but Different performances on Parallel Architectures in terms of scalability

11 Parallelization of the algorithm Main goal: reducing the completion time for the entire input cube Stream Computation Stream parallel paradigms to reduce Service Time (load balanced computation) Data Parallel paradigms used to reduce both Service Time and latency of the computation, in order to decrease the response time of the whole system (load balancing issue) A composite parallel paradigm can assure the right performance level in terms of latency and service time

Factorization Function on the worker modules

12 Stream Parallel Paradigm: Task Farm Emitter Worker 1... Worker N Collector Replication of the entire Factorization Function on the worker modules Performance improvements assured until the Emitter module is not a bottleneck

13 Reference Architecture: Cell BE Asymmetric NUMA Multicore Complex Memory Hierarchy Processing Elements own a small local memory (not cache) Dynamic memory management accessing the main memory for large Data Structures

14 Reference Architecture: Cell BE Processor 0 Processor 1 Processor 7 Local memory Local Memory Local Memory Interconnection Network PowerPC Processor PowerPC Memory

15 Farm Paradigm applied to Cell BE

16 Service Time Scalability Performances obtained on Cell BE (IBM QS 20 Cell Blade) Traditional algorithms (512x512 complex matrices) Service Time (milliseconds) Scalability Parallelism Degree Parallelism Degree

17 Service Time Scalability Performances obtained on Cell BE Block Algorithm (512x512 Complex Matrix) Service Time (milliseconds) Scalability Parallelism Degree Parallelism Degree PERFECT SCALABILITY

18 Service Time Scalability Performances obtained on Intel Multicore Processor (Intel XEON E5420) Block Algorithm (512x512 Complex Matrix) Service Time (milliseconds) Scalability Parallelism Degree Parallelism Degree

19 Data Parallel Paradigm Adopted only for Block version of the algorithm Based on partitioning of data structure and functional replication Adopted the Virtual Processors approach for parallel program design Each block of the main matrix is assigned to a Virtual Processor Detect data ownership applying owner computes rule and the Data Dependancies to understand the Stencil Form

20 Virtual Processor parallelization

21 Mapping Virtual Processors on the Real Processors Applied a uniform reduction of parallelism degree Map a set of Virtual Processors on a computation node (e.g. a core of a Multicore Architecture) Different mapping may express different performances due to the load balancing of the computation

22 Mapping Example Linear mapping of the VP Rows on the real processors Poor performances due to load unbalancing

23 Latency Scalability Experimental Results on Cell BE Unbalanced mapping 250 Latency (milliseconds) 16 Scalability Parallelism Degree Parallelism Degree

24 Partially balanced mapping example Coupling the rows in order to balance the computation executed by a core

25 Latency Scalability Experimental Results on Cell BE Latency Scalability Parallelism Degree Parallelism Degree

26 Composite parallel paradigm Applied in order to reduce Service Time and latency of a parallel application Farm paradigm with Parallel Workers (implemented with Data Parallel Paradigm) May assure optimal performances needed by real time applications in Signal Processing

27 Titolo asse Service Time Experimental Results on Cell BE for composite patterns Service Time Data Parallel Parallelism Degree Worker Worker Farm Parallelism Degree 4 Worker 8 Worker Farm Scalability Titolo asse

28 Results, actual and future work Good performances obtained applying formal methodology for parallelism Low parallelism degree available in the actually used multicore architectures Apply this methodology using future General Purpose multicore architectures with higher parallelism degree (e.g. Multicore Processors available in IT Center) Test this kind of solutions on the new Multicore Architectures proposed in the Smecy Project High parallelism degree available on these new architectures but quite simple architecture for the singular core and interconnection network design (2D mesh tipically)

29 Future work All these solutions has been implemented using low level tools Test the new development tools proposed by the Smecy partners Implementation of the runtime support and high level development tools for parallel applications on some of the available architectures is an ongoing activity of the collaboration between Parallel Architecture Research Group and Selex SI

30 Any question??

31 Optimum weight (2/2) M is the space-time covariance matrix. In practice, one generally does not know a priori the clutter and interference situation. For practical applications, the covariance matrix M is unknown and must be estimated from data samples (M ). If the interference field changes by the presence of clutter, antenna errors, interference, and jamming, we must continually update or adapt the weight vector W O to meet the varying conditions.

A COMPREHENSIVE MULTIDISCIPLINARY PROGRAM FOR SPACE-TIME ADAPTIVE PROCESSING (STAP)

AFRL-SN-RS-TN-2005-2 Final Technical Report March 2005 A COMPREHENSIVE MULTIDISCIPLINARY PROGRAM FOR SPACE-TIME ADAPTIVE PROCESSING (STAP) Syracuse University APPROVED FOR PUBLIC RELEASE; DISTRIBUTION