EVB to 930MHz Receiver Evaluation Board Description

Transcription

1 EVB722 Features Programmable PLL synthesizer 8-channel preconigured or ully programmable SPI mode Double super-heterodyne receiver architecture with 2 nd mixer as image rejection mixer Reception o FSK, FM and ASK modulated signals Low shut-down and operating currents AGC automatic gain control On-chip IF ilter Fully integrated FSK/FM demodulator RSSI or level indication and ASK detection 2 nd order low-pass data ilter Positive and negative peak detectors Data slicer (with averaging or peak-detector adaptive threshold) 32-pin Quad Flat No-Lead Package (QFN) EVB programming sotware is available on Melexis web site Ordering Inormation Part No. (see paragraph 6) EVB C EVB C *SPI mode is deault population, ABC mode according to paragraph 5 **EVB722-XXX-C with XXX = Reception requency (35 or or or 95MHz). ***The evaluation board is supplied with a SMA connector. Application Examples General digital and analog RF receivers at 300 to 930MHz Tire pressure monitoring systems (TPMS) Remote keyless en try (RKE) Low power telemetry systems Alarm and security systems Active RFID tags Remote controls Garage door openers Home and building automation EVB C EVB C Evaluation Board Example General Description The MLX722 is a multi-channel RF receiver IC based on a double-conversion super-heterodyne architecture. It is designed to receive FSK and ASK modulated RF signals either in 8 predeined requency channels or requency programmable via a 3-wire serial programming interace (SPI). The IC is designed or a variety o applications, or example in the European bands at 433MHz and 868MHz or or the use in North America or Asia, e.g. at 35MHz, 447MHz or 95MHz Page o 32 EVB Description

2 EVB722 Document Content Theory o Operation...4. General EVB Data Overview Block Diagram Enable/Disable in ABC Mode Demodulation Selection in ABC Mode Programming Modes Preconigured Frequencies in ABC Mode Functional Description Frequency Planning Calculation o Counter Settings Calculation o LO and IF requency or Low Frequency Bands Calculation o LO and IF requency or High Frequency Bands Counter Setting Examples or SPI Mode Counter Settings in ABC Mode 8+ Preconigured Channels PLL Counter Ranges SPI Description General Read / Write Sequences Serial Programming Interace Timing Register Description Register Overview Control Word R Control Word R Control Word R Control Word R Control Word R Control Word R Control Word R Control Word R7 (Read-only Register) Application Circuits or SPI Mode Averaging Data Slicer Conigured or Bi-Phase Codes Peak Detector Data Slicer Conigured or NRZ Codes Board Component Values List (SPI mode) Application or 8-Channel Preconigured (ABC) Mode Averaging Data Slicer Conigured or Bi-Phase Codes Board Component Values List (ABC mode) Page 2 o 32 EVB Description

3 EVB722 6 Evaluation Board Layouts Package Description Soldering Inormation Reliability Inormation ESD Precautions Disclaimer Page 3 o 32 EVB Description

4 EVB722 Theory o Operation. General The MLX722 receiver architecture is based on a double-conversion super-heterodyne approach. The two LO signals are derived rom an on-chip integer-n PLL requency synthesizer. The PLL reerence requency is derived rom a crystal (XTAL). The PLL synthesizer consists o an integrated voltage-controlled oscillator with external inductor, a programmable eedback divider chain, a programmable reerence divider, a phaserequency detector with a charge pump and an external loop ilter. In the receiver s down-conversion chain, two mixers MIX and MIX2 are driven by the internal local oscillator signals LO and, respectively. The second mixer MIX2 is an image-reject mixer. As the irst intermediate requency (IF) is very high (typically above 00 MHz), a reasonably high degree o image rejection is provided even without using an RF ront-end ilter. At applications asking or very high image rejections, cost-eicient RF ront-end iltering can be realized by using a SAW ilter in ront o the LNA. The receiver signal chain is set up by a low noise ampliier (LNA), two down-conversion mixers (MIX and MIX2), an on-chip IF ilter (IFF) as well as an IF ampliier (IFA). By choosing the required modulation via an FSK/ASK switch (at pin MODSEL), either the on-chip FSK demodulator (FSK DEMOD) or the RSSI-based ASK detector is selected. A second order data ilter (OA) and a data slicer (OA2) ollow the demodulator. The data slicer threshold can be generated rom the mean-value o the data stream or by means o the positive and negative peak detectors (PKDET+/-). In general the MLX722 can be set to shut-down mode, where all receiver unctions are completely turned o, and to several other operating modes. There are two global operating modes that are selectable via the logic level at pin SPISEL: 8-channel preconigured mode (ABC mode) ully programmable mode (SPI mode). In ABC mode the number o requency channels is limited to eight but no microcontroller programming is required. In this case the three lines o the serial programming interace (SPI) are used to select one o the eight predeined requency channels via simple 3-bit parallel programming. Pins ENRX and MODSEL are used to enable/disable the receiver and to select FSK or ASK demodulation, respectively. SPI mode is recommended or ull programming lexibility. In this case the three lines o the SPI are conigured as a standard 3-wire bus (SDEN, SDTA and SCLK). This allows changing many parameters o the receiver, or example more operating modes, channels, requency resolutions, gains, demodulation types, data slicer settings and more. The pin MODSEL has no eect in this mode..2 EVB Data Overview Input requency ranges: 300 to 930MHz Power supply range: 3.0 to 5.5V Temperature range: -40 to +05 C Shutdown current: 50nA Operating current: 2mA (typ.) Internal IF2: 2MHz with 230kHz 3dB bandwidth Maximum data rate: 00kbps NRZ code, 50kbps bi-phase code Minimum requency resolution: 0kHz Total image rejection: > 65dB (with external RF ront-end ilter) FSK/FM deviation range: ±2 to ±50kHz Spurious emission: < -70dBm Linear RSSI range: > 50dB FSK input requency acceptance range: 80kHz (3dB) Crystal reerence requency: 0MHz Input Sensitivity: at 4 kbps NRZ, BER = Frequency 35 MHZ 433 MHz 868 MHz 95 MHz FSK: ±20 khz deviation -06dBm -04dBm -0dBm -0dBm ASK -08dBm -08dBm -06dBm -06dBm Page 4 o 32 EVB Description

5 EVB722.3 Block Diagram VEELNA 2 VCCANA 3 LNAO 4 VEEIF MIXN MIXP RSSI ASK 9 MODSEL 28 DF DF2 200k 200k 29 OA DFO 27 LNAI 3 VEEVCO LNA VCCVCO 4 DIV VCO TNK 2 3 TNK2 MIX MIX2 IFF IF IF2 N / A counter 23 MFO PFD LF CP RO 5 LF LO R counter 24 ROI IFA SPISEL Control Logic C/SDEN B/SDTA A/SCLK FSK FSK DEMOD SLCSEL BIAS RBIAS SW ENRX 200k SW2 VEEDIG M M VCCDIG 30 VEEANA PKDET+ PKDET _ OA2 25 PDP PDN 26 DTAO 22 SLC 32 Fig. : MLX722 block diagram The MLX722 receiver IC consists o the ollowing building blocks: PLL synthesizer (PLL SYNTH) to generate the irst and second local oscillator signals LO and, parts o the PLL SYNTH are the voltage-controlled oscillator (VCO), the eedback dividers N/A and R, the phase-requency detector (PFD), the charge pump (CP) and the crystal-based reerence oscillator (RO) Low-noise ampliier (LNA) or high-sensitivity RF signal reception First mixer (MIX) or down-conversion o the RF signal to the irst IF (intermediate requency) Second mixer (MIX2) with image rejection or down-conversion rom the irst to the second IF IF Filter (IFF) with a 2MHz center requency and a 230kHz 3dB bandwidth IF ampliier (IFA) to provide a large amount o voltage gain and an RSSI signal output FSK demodulator (FSK DEMOD) Operational ampliiers OA and OA2 or low-pass iltering and data slicing, respectively Positive (PKDET+) and negative (PKDET-) peak detectors Switches SW to select between FSK and ASK as well as SW2 to chose between averaging or peak detector data slicer Control logic with 3-wire bus serial programming interace (SPI) Biasing circuit with modes control For more detailed inormation, please reer to the latest MLX722 data sheet revision Page 5 o 32 EVB Description

6 EVB722.4 Enable/Disable in ABC Mode ENRX Description 0 Shutdown mode Receive mode Pin ENRX is pulled down internally. Device is in shutdown by deault, ater power supply on. I ENRX = 0 and SPISEL = then operating modes according to OPMODE bit (reer to control word R0). I ENRX = then OPMODE bit has no eect (hardwired receive mode)..5 Demodulation Selection in ABC Mode MODSEL Description 0 FSK demodulation ASK demodulation Pin MODSEL has no eect in SPI mode (SPISEL = ). We recommend connecting it to ground to avoid a loating CMOS gate..6 Programming Modes SPISEL Description 0 ABC mode (8 channels preconigured) SPI mode (programming via 3-wire bus).7 Preconigured Frequencies in ABC Mode A B C Receive Frequency FSK: MHz 0 0 FSK5: MHz 0 0 FSK2: 37. MHz 0 FSK4: MHz 0 0 FSK3: MHz 0 FSK7: MHz 0 FSK6: 39.5 MHz FSK8: MHz As all pins, pins A, B, and C are equipped with ESD protection diodes that are tied to VCC and to VEE. Thereore these pins should not be directly connected to positive supply (a logic ) beore the supply voltage is applied to the IC. Otherwise the IC will be supplied through these control lines and it may enter into an unpredictable mode. In case the user wants to apply a positive supply voltage to these pins beore the supply voltage is applied to the IC, a protection resistor should be inserted in each control line Page 6 o 32 EVB Description

7 EVB722 2 Functional Description 2. Frequency Planning Because o the double conversion architecture that employs two mixers and two IF signals, there are our dierent combinations or injecting the LO and signals: LO high side and high side: receiving at RF (high-high) LO high side and low side: receiving at RF (high-low) LO low side and high side: receiving at RF (low-high) LO low side and low side: receiving at RF (low-low) As a result, our dierent radio requencies (RFs) could yield one and the same second IF (IF2). Fig. 2 shows this or the case o receiving at RF (high-high). In the example o Fig. 2, the image signals at RF (lowhigh) and RF (low-low) are suppressed by the bandpass characteristic provided by the RF ront-end. The bandpass shape can be achieved either with a SAW ilter (eaturing just a couple o MHz bandwidth), or by the tank circuits at the LNA input and output (this typically yields 30 to 60MHz bandwidth). In any case, the high value o the irst IF (IF) helps to suppress the image signals at RF (low-high) and RF (low-low). The two remaining signals at IF resulting rom RF (high-high) and RF (high-low) are entering the second mixer MIX2. This mixer eatures image rejection with so-called single-sideband (SSB) selection. This means either the upper or lower sideband o IF can be selected. In the example o Fig. 2, high-side injection has been chosen to select the IF2 signal resulting rom RF (high-high). RF Fig. 2: RF LO The our receiving requencies in a double conversion superhet receiver RF RF It can be seen rom the block diagram o Fig. that there is a ixed relationship between the LO signal requency LO and the signal requency. DIV = LO = N () The LO signal requency LO is directly synthesized rom the crystal reerence oscillator requency RO by means o an integer-n PLL synthesizer. The PLL consists o a dual-modulus prescaler (P/P+), a program counter N and a swallow counter A. R RO LO = (N P + A) = PFD(N P + A) = PFD N tot (2) Page 7 o 32 EVB Description

8 EVB722 Due to the double superhet receiver architecture, the channel requency step size CH is not equal to the phase-requency detector (PFD) requency PFD. For high-side injection, the channel step size CH is given by: CH N N RO = = PFD (3) R N N While the ollowing equation is valid or low-side injection: CH N + N + RO = = PFD (4) R N N 2.2 Calculation o Counter Settings Frequency planning and the selection o the MLX722 s PLL counter settings are straightorward and can be laid out on the ollowing procedure. Usually the receive requency RF and the channel step size CH are given by system requirements. The N and A counter settings can be derived rom N tot or LO and PFD by using the ollowing equations. N tot N tot N = loor( ) = loor( ) ; A = N tot N P = N tot N 32 (5) P Calculation o LO and IF requency or Low Frequency Bands High-high injection must be used or the low requency bands. First o all choose a PFD requency PFD according to below table. The R counter values are valid or a 0MHz crystal reerence requency RO. The PFD requency is given by PFD = RO /R. Injection Type CH [khz] PFD [khz] R h-h h-h h-h h-h h-h h-h h-h The second step is to calculate the missing parameters LO, IF, N tot, N and A. While the second IF ( IF2 ), the N divider ratio and the prescaler divider ratio P are bound to IF2 = 2MHz, N = 4 (or 8) and P =32. LO = N 4 ( RF IF2) ( N 3 2MHz) LO = RF (6) IF = RF N N IF2 8MHz 3 RF IF = (7) Finally N and A can be calculated with ormula (5) Page 8 o 32 EVB Description

9 EVB Calculation o LO and IF requency or High Frequency Bands Typical ISM band operating requencies like and 95MHz can be covered without changing the crystal nor the VCO inductor. Low-low injection should be used or the high requency bands. First o all choose a PFD requency PFD according to below table. The R counter values are valid or a 0MHz crystal reerence. The PFD requency is given by PFD = RO /R. Injection Type CH [khz] PFD [khz] R l-l l-l l-l l-l l-l l-l The second step is to calculate the missing parameters LO, IF, N tot, N and A. While the second IF ( IF2 ), the N divider ratio and the prescaler divider ratio P are bound to IF2 = 2MHz, N Lo2 = 4 (or 8) and P =32. LO IF = N 4 ( RF IF2) ( N + 5 2MHz) LO RF = RF + N N + Finally N and A can be calculated with ormula (5). IF2 = (8) + 8MHz 5 RF IF = (9) Counter Setting Examples or SPI Mode To provide some examples, the ollowing table shows some counter settings or the reception o the wellknown ISM and SRD requency bands. The channel spacing is assumed to be CH = 00kHz. In below table all requency units are in MHz. Inj RF IF LO N tot N P A PFD R REF IF2 h-h h-h h-h h-h l-l l-l l-l l-l Page 9 o 32 EVB Description

10 EVB Counter Settings in ABC Mode 8+ Preconigured Channels In ABC mode (SPISEL=0), the counter settings are hard-wired. In below table all requency units are in MHz. CH Inj RF IF LO N tot N P A PFD R REF IF2 h-l h-l h-l h-l h-l h-l h-l h-l h-l List o Mathematical Acronyms A divider ratio o the swallow counter (part o eedback divider) requency at the eedback divider output FB loor (x) The loor unction gives the largest integer less than or equal to x. For example, loor(5.4) gives 5, loor(-6.3) gives -7. PFD PFD requency in locked state RO = R R reerence requency o the PLL RO requency o the crystal reerence oscillator VCO requency o the VCO (equals the LO signal o the irst mixer) N tot = N P + A total divider ratio o the PLL eedback path N divider ratio o the program counter (part o eedback divider) N DIV divider ratio, to derive the signal rom LO (N = 4 or 8) P divider ratio o the prescaler (part o eedback divider) R divider ratio o the reerence divider R Page 0 o 32 EVB Description

11 EVB PLL Counter Ranges In order to cover the requency range o about 300 to 930MHz the ollowing counter values are implemented in the receiver: PLL Counter Ranges A N R P 0 to 3 (5bit) 3 to 2047 (bit) 3 to 2047 (bit) 32 Thereore the minimum and maximum divider ratios o the PLL eedback divider are given by: N totmin = = 024 N totmax = = SPI Description 2.3. General Serial programming interace (SPI) mode can be activated by choosing SPISEL = (e.g. at positive supply voltage V CC ). In this mode, the input pins 7, 8 and 9 are used as a 3-wire unidirectional serial bus interace (SDEN, SDTA, SCLK). The internal latches contain all user programmable variables including counter settings, mode bits etc. In addition the MFO pin can be programmed as an output (see section 3..4) in order to read data rom the internal latches and it can be used as an output or dierent test modes as well. At each rising edge o the SCLK signal, the logic value at the SDTA terminal is written into a shit register. The programming inormation is taken over into internal latches with the rising edge o SDEN. Additional leading bits are ignored, only the last bits are serially clocked into the shit register. A normal write operation shits 6 bits into the SPI, a normal read operation shits 4 bits into the SPI and reads additional 2 bits rom the MFO pin. I less than 2 data bits are shited into SDTA during the write operation then the control register may contain invalid inormation. In general a control word has the ollowing ormat. Bit 0 is the Read/Write bit that determines whether it is a read (R/W = ) or a write (R/W = 0) sequence. The R/W bit is preceding the latch address and the corresponding data bits. Control Word Format MSB LSB MSB LSB Bit 0 Data Latch Address Mode D D0 D9 D8 D7 D6 D5 D4 D3 D2 D D0 A2 A2 A0 R/W There are two control word ormats or read and or write operation. Data bits are only needed in write mode. Read operations require only a latch address and a R/W bit. Due to the static CMOS design, the serial interace consumes virtually no current. The SPI is a ully separate building block and can thereore be programmed in every operational mode Page o 32 EVB Description

12 EVB Read / Write Sequences Fig. 6 Typical write sequence diagram Fig Serial Programming Interace Timing SDEN Typical read sequence diagram t CWH t CR t EW t EH t CWL t CF SCLK t CS t CH t ES t DES t DSO SDTA MFO Fig. 8 SPI timing diagram Page 2 o 32 EVB Description

13 EVB722 3 Register Description The ollowing tables are to describe the unctionality o the registers. Sec. 3. provides a register overview with all the control words R0 to R7. The subsequent sections. 3.. to 3..8 show the content o the control words in more detail. Programming the registers requires SPI mode (SPISEL = ). Deault settings are or ABC mode. 3. Register Overview CONTROL DATA WORD MSB LSB LATCH ADDRESS Bit No MSB LSB deault R0 DTAPOL SLCSEL SSBSEL DEMGAIN IFFGAIN [ :0 ] MIX2GAIN MIXGAIN LNAGAIN [ : 0 ] OPMODE [ : 0 ] Bit No MSB read/ write deault R SHOWLD PRESCUR VCOBUF VCOCUR VCORANGE RSSIGAIN LDTIME [ :0 ] LDERR PFDPOL CPCUR [ : 0 ] read/ write Bit No MSB LSB deault LSB R2 N [ 6 : 0 ] A [ 4 : 0 ] read/ write Bit No MSB LSB deault R3 MFO [ 3 : 0 ] AGCDEL [ : 0 ] AGCEN DIV N [ 0 : 7 ] read/ write Page 3 o 32 EVB Description

14 EVB722 CONTROL DATA WORD MSB LSB LATCH ADDRESS Bit No MSB LSB deault R4 AGCMODE R [ 0 : 0 ] read/ write Bit No MSB LSB deault R5 MODSEL RIFF [ 0 : 0 ] read/ write Note: Bit No MSB LSB deault R6 ROCUR [ :0 ] IFFTUNE IFFHLT IFFPRES [ 7 : 0 ] read/ write Bit No MSB LSB deault R7 RSSIH LDRSSIL IFFSTATE [ :0 ] IFFVAL [ 7 : 0 ] readonly depends on bit in R4, 0 = RSSIL, = LD Page 4 o 32 EVB Description

15 EVB Control Word R0 Name Bits Description OPMODE [:0] LNAGAIN [3:2] MIXGAIN [4] 0 MIX2GAIN [5] 0 IFFGAIN [7:6] DEMGAIN [8] 0 SSBSEL [9] 0 SLCSEL [0] 0 DTAPOL [] operation mode shutdown receive mode reerence oscillator & BIAS only synthesizer only LNA gain lowest gain low gain high gain highest gain (deault 20dB) (deault 6dB) (deault 2dB) (deault 0dB) gain values are relative to gain at deault st Mixer gain high gain (4dB) low gain (0dB) 2 nd Mixer gain high gain (9dB) low gain (-2dB) intermediate requency ilter gain lowest gain (-4dB) low gain (-6dB) high gain (0dB) highest gain (+6dB) demodulator gain low gain (~ 2mV/kHz) high gain (~ 4.5mV/kHz) single side band selection upper side band lower side band low-side inj. (IF = + IF2) high-side inj. (IF = IF2) Internal IF2 = 2MHz slicer mode select averaging Data Slicer mode peak detector Data Slicer mode data output polarity OA2 0 inverted or space at ASK or min at FSK, 0 or mark at ASK or max at FSK normal 0 or space at ASK or min at FSK, or mark at ASK or max at FSK Page 5 o 32 EVB Description

16 EVB Control Word R Name Bits Description CPCUR [:0] PFDPOL [2] 0 LDERR [3] 0 LDTIME [5:4] RSSIGAIN [6] 0 VCORANGE [7] 0 VCOCUR [8] 0 VCOBUF [9] 0 PRESCUR [0] SHOWLD [] charge pump current setting 00µA 400µA 400µA static down 400µA static up PFD output polarity negative positive lock detector time error 5ns 30ns lock detection time 0 0 2/ R 4/ R 8/ R 6/ R minimum time span beore lock in R is the reerence oscillator requency RO divided by R, see section 3..5 (R4) low gain high gain 3V supply 5V supply VCO range setting or dierent VCCs. 450µA 520µA 900µA 040µA 20µA 30µA sensitivity o RSSI voltage (~39mV/dB) (~5mV/dB) VCO range VCO core current VCO buer current prescaler 32/33 reerence current 30µA may be used or RF = 868/95MHz unction o LDRSSIL bit RSSIL (RSSI low lag) LD (lock detection lag) select output data o LDRSSIL, see section 3..8 (R7) Page 6 o 32 EVB Description

17 EVB Control Word R2 Name Bits Description swallow counter value A [4:0] 000 value is 20 swallow counter range: 0 to 3 program counter value (bits 0 6) N [:5] N value is 20 N counter range: 3 to Control Word R3 N [3:0] DIV [4] 0 AGCEN [5] 0 AGCDEL [7:6] MFO [:8] program counter range (bits 7 0) N value is divide by 4 divide by 8 disabled enabled no delay 3/ IFF 5/ IFF 3/ IFF N counter range: 3 to 2047 divider ratio AGC enable mode AGC delay settings IFF is the reerence oscillator requency RO divided by RIFF, see section 3..6 (R6) MFO is in Z state MFO is SPI read-out MFO = 0 MFO = MFO is analog RO output MFO is IFF output MFO is lock detector output multi unctional output Page 7 o 32 EVB Description

18 EVB Control Word R4 Name Bits Description R [0:0] AGCMODE [] reerence divider range value is 75 0 R counter range: 3 to 2047 AGC delay mode gain decrease and increase with delay gain decrease without delay, gain increase with delay selects AGC delay mode in combination with AGCDEL bits, see section 3..4 (R3) 3..6 Control Word R5 Name Bits Description RIFF [0:0] MODSEL [] 3..7 Control Word R6 reerence divider value or IFF adjustment value is IFF counter range: 4 to 2047 demodulation selection FSK demodulation ASK demodulation selects modulation type when chip is controlled via SPI mode Name Bits Description IFFPRES [7:0] IFFHLT [8] IFF preset value 00 0 value is 9 0 IFFTUNE [9] 0 ROCUR [:0] IFF DAC preset at start o automatic tuning auto tuning running auto tuning halted suspends IFF automatic tuning IFF halt IFF tuning disable and load DAC with IFFPRES enable reerence Oscillator core current 85µA 70µA 270µA 355µA Page 8 o 32 EVB Description

19 EVB Control Word R7 (Read-only Register) Name Bits Description IFFVAL [7:0] IFFSTATE [9:8] LDRSSIL [0] RSSIH [] 0 see also IFFPRES in section 3..7 (R6) IFF adjustment value IFF automatic tuning state ilter tuned or auto-tuning disabled tuning up the ilter requency tuning down the ilter requency master oscillator o ilter does not work lock detector or RSSI low lag PLL not locked or RSSI value in lower region PLL locked or RSSI value above lower region depends on SHOWLD in section 3..2 (R) RSSI high lag RSSI value below upper region RSSI value in upper region Page 9 o 32 EVB Description

20 EVB722 4 Application Circuits or SPI Mode 4. Averaging Data Slicer Conigured or Bi-Phase Codes DFO MFO 2 3 DTAO 2 CB3 VCC RS2 RS MFO GND SCLK SDTA SDEN XTAL CX RB RS L 3 C SAWFIL 4 6 L2 C8 C9 C2 25 PDP 26 PDN 27 DFO 28 DF 29 DF2 30 VEEANA 3 LNAI 32 SLC C0 ROI MFO DTAO VEELNA VCCDIG VEEDIG A/SCLK B/SDTA MLX722 LNAO VEEIF MIXN MIXP SPISEL L3 C5 C6 ENRX 6 LF 5 VCCVCO 4 TNK2 3 TNK 2 VEEVCO RBIAS 0 MODSEL CB VCCANA C4 C/SDEN RSSI 8 C7 9 L0 RF RBS RSSI 2 CF2 CB0 CF CB2 VCC GND VCC 2 Fig. 6: Application circuit or SPI Mode (averaging data slicer option) Note EVB722 deault population is SPI mode Page 20 o 32 EVB Description

21 EVB722 Board size is 49mm x 35.6mm Melexis DFO GND MFO GND DTAO GND VCC MFO A GND RF_input RF_input EVB722_002 3 XTAL GND RSSI FSK/ASK Fig. 7: C CX L L2 C2 C8 C0 CB L3 C4 RB0 C5 C7 0 RS B RS2 C CB3 RS3 C6 SPI mode selected L0 CF2 RF CF RBS PCB Top-side view (averaging data slicer option) CB2 0 CB0 SCLK SDTA SDEN ENRX MODSEL VCC GND Page 2 o 32 EVB Description

22 EVB Peak Detector Data Slicer Conigured or NRZ Codes DFO MFO 2 3 DTAO 2 CB3 VCC RS2 RS MFO GND SCLK SDTA SDEN XTAL CX RB0 RS3 50 L 3 C SAWFIL 4 6 L2 C C2 C8 C9 C2 25 PDP 26 PDN 27 DFO 28 DF 29 DF2 3 LNAI 24 ROI 30 VEEANA SLC VEELNA 23 MFO 22 DTAO 2 VCCDIG 20 9 MLX722 LNAO VEEIF VEEDIG MIXN MIXP 8 B/SDTA SPISEL L3 CB VCCANA C4 C5 A/SCLK C6 7 C/SDEN ENRX 6 LF 5 VCCVCO 4 TNK2 3 TNK 2 VEEVCO RBIAS 0 MODSEL RSSI 8 C7 9 L0 RF RBS RSSI 2 CF2 CB0 CF CB2 VCC GND VCC 2 Fig. 8: Application circuit or SPI Mode (peak detector option) Note EVB722 deault population is SPI mode Page 22 o 32 EVB Description

23 EVB722 Board size is 49mm x 35.6mm Melexis DFO GND MFO GND DTAO GND VCC MFO A GND RF_input RF_input C L EVB722_002 3 XTAL C2 GND RSSI FSK/ASK Fig. 9: L2 C C2 C8 CX CB L3 C4 RB0 C5 C7 0 RS B RS2 C CB3 RS3 C6 SPI mode selected L0 CF2 RF CF RBS PCB Top-side view (peak detector option) CB2 0 CB0 SCLK SDTA SDEN ENRX MODSEL VCC GND Page 23 o 32 EVB Description

24 EVB Board Component Values List (SPI mode) Below table is or the application circuits show in Figures 6 and 8 Part Size 35 MHz MHz MHz 95 MHz Tol. Description C 0603 NIP NIP 3.3 pf NIP ±5% matching capacitor C NIP NIP NIP NIP ±5% matching capacitor C pf 3.3 pf 2.7 pf 2.2 pf ±5% LNA output tank capacitor C pf 00 pf 00 pf 00 pf ±5% MIX negative input matching capacitor C pf 00 pf 00 pf 00 pf ±5% MIX negative input matching capacitor C nf nf nf nf ±0% RSSI output low pass capacitor, this value or data rate o 4 kbps NRZ C pf 220 pf 220 pf 220 pf ±0% data low-pass ilter capacitor, this value or data rate o 4 kbps NRZ C pf 50 pf 50 pf 50 pf ±0% data low-pass ilter capacitor, this value or data rate o 4 kbps NRZ 33 nf 33 nf 33 nf 33 nf data slicer capacitor, C ±0% this value or data rate o 4 kbps not required in Figure 8 NRZ C nf 33 nf 33 nf 33 nf peak detector positive iltering ±0% not required in Figures 6 capacitor C nf 33 nf 33 nf 33 nf peak detector negative iltering ±0% not required in Figures 6 capacitor decoupling capacitor, CB μf 0 μf 0 μf 0 μf ±0% low-noise power supply recommended CB pf 470 pf 470 pf 470 pf ±0% decoupling capacitor CB nf 33 nf 33 nf 33 nf ±0% decoupling capacitor CB nf 33 nf 33 nf 33 nf ±0% decoupling capacitor CF nf 2.2 nf 2.2 nf 2.2 nf ±5% loop ilter capacitor CF pf 220 pf 220 pf 220 pf ±5% loop ilter capacitor CX pf 27 pf 27 pf 27 pf ±5% crystal series capacitor RB Ω 0 Ω 0 Ω 0 Ω ±5% protection resistor RF kω 27 kω 47 kω 47 kω ±5% loop ilter resistor RBS kω 30 kω 30 kω 30 kω ±2% reerence bias resistor RS RS3 0 kω 0 kω 0 kω 0 kω ±5% protection resistor L nh 5 nh 8.2 nh 8.2 nh ±5% VCO tank inductor L Ω 56 nh 22 nh 0 Ω ±5% matching inductor L nh 82 nh 22 nh 8.2 nh ±5% matching inductor L nh 22 nh 5.6 nh 5.6 nh ±5% LNA output tank inductor XTAL SAW FIL Note: SMD 5x3.2 SMD 3x3 SAFDC35MS M0T00 (35 MHz) MHz / ±20ppm cal., ±30ppm temp. undamental-mode crystal SAFCC433MB L0X00 ( MHz) SAFCC868MS L0X00 (868.3 MHz) - NIP not in place, may be used optionally SAFCH95MA L0N00 (95 MHz) low-loss SAW ilter rom Murata or equivalent part Page 24 o 32 EVB Description

25 EVB722 5 Application or 8-Channel Preconigured (ABC) Mode 5. Averaging Data Slicer Conigured or Bi-Phase Codes DFO DTAO 2 3 A 2 2 CB3 VCC 2 3 B VCC 50 C L C2 C8 C9 C3 XTAL 32 SLC C0 CX 25 PDP 26 PDN 27 DFO 28 DF 29 DF2 24 ROI 30 VEEANA 3 LNAI VEELNA 23 MFO 22 DTAO 2 VCCDIG 20 9 MLX722 LNAO VEEIF VEEDIG MIXN MIXP 8 SPISEL CB VCCANA L3 C5 C4 RB0 A/SCLK C6 7 B/SDTA C/SDEN 2 3 ENRX 6 LF 5 VCCVCO 4 TNK2 3 TNK 2 VEEVCO RBIAS 0 MODSEL RSSI 8 C7 9 C L0 RF RBS RSSI 2 CF2 CB0 CF CB2 VCC ENRX 2 3 MODSEL 2 3 GND VCC 2 Fig. 0: Application circuit or ABC Mode Note ABC mode population can be easily modiied rom deault SPI mode population by changing the connection at SPISEL rom VCC to ground Page 25 o 32 EVB Description

26 EVB722 Board size is 49mm x 35.6mm Melexis DFO GND MFO GND DTAO GND VCC MFO A GND RF_input RF_input C L EVB722_002 3 XTAL 0 C2 C8 CX C3 C0 CB L3 C4 RB0 C5 CB3 RF C6 GND RSSI SCLK B SDTA C SDEN FSK/ASK ENRX MODSEL VCC GND ABC mode selected L0 CF2 RBS Fig. : PCB Top-side view (ABC Mode) C7 CF CB2 0 CB Page 26 o 32 EVB Description

27 EVB Board Component Values List (ABC mode) Below table is or the application circuit shows in Figures 0 Part Size 369 MHz to 396 MHz Tol. Description C 0603 NIP ±5% matching capacitor C NIP ±5% matching capacitor C pf ±5% LNA input iltering capacitor C pf ±5% LNA output tank capacitor C pf ±5% MIX negative input matching capacitor C pf ±5% MIX negative input matching capacitor C nf ±0% RSSI output low pass capacitor, this value or data rate o 4 kbps NRZ C pf ±0% data low-pass ilter capacitor, this value or data rate o 4 kbps NRZ C pf ±0% data low-pass ilter capacitor, this value or data rate o 4 kbps NRZ C nf ±0% data slicer capacitor, this value or data rate o 4 kbps NRZ CB μf ±0% decoupling capacitor, low-noise power supply recommended CB pf ±0% decoupling capacitor CB nf ±0% decoupling capacitor CB nf ±0% decoupling capacitor CF nf ±5% loop ilter capacitor CF pf ±5% loop ilter capacitor CX pf ±5% crystal series capacitor RB Ω ±5% protection resistor RF kω ±5% loop ilter resistor RBS kω ±2% reerence bias resistor RS RS kω ±5% protection resistor L nh ±5% VCO tank inductor L nh ±5% matching inductor L nh ±5% LNA output tank inductor XTAL SMD 5x MHz / ±20ppm cal., ±30ppm temp. undamental-mode crystal Note: - NIP not in place, may be used optionally Page 27 o 32 EVB Description

28 EVB722 6 Evaluation Board Layouts Board layout data in Gerber ormat is available, board size is 35.6mm x 49mm. DTAO GND GND RSSI VCC A B C FSK/ASK MFO GND SCLK SDTA SDEN ENRX DFO GND MFO GND MODSEL VCC Melexis GND PCB top view EVB722_002 PCB bottom view Page 28 o 32 EVB Description

29 EVB722 7 Package Description The device MLX722 is RoHS compliant. D 24 7 A E 32 9 L 8 A A e b exposed pad D2 The exposed pad is not connected to internal ground, it should not be connected to the PCB. E2 Fig 2: 32L QFN 5x5 Quad all Dimension in mm D E D2 E2 A A A3 L e b min max all Dimension in inch min max Soldering Inormation The device MLX722 is qualiied or MSL3 with soldering peak temperature 260 deg C according to JEDEC J-STD Page 29 o 32 EVB Description

30 EVB722 8 Reliability Inormation This Melexis device is classiied and qualiied regarding soldering technology, solderability and moisture sensitivity level, as deined in this speciication, according to ollowing test methods: Relow Soldering SMD s (Surace Mount Devices) IPC/JEDEC J-STD-020 Moisture/Relow Sensitivity Classiication or Nonhermetic Solid State Surace Mount Devices (classiication relow proiles according to table 5-2) Wave Soldering SMD s (Surace Mount Devices) EN Resistance o plastic- encapsulated SMD s to combined eect o moisture and soldering heat Solderability SMD s (Surace Mount Devices) EIA/JEDEC JESD22-B02 Solderability For all soldering technologies deviating rom above mentioned standard conditions (regarding peak temperature, temperature gradient, temperature proile etc) additional classiication and qualiication tests have to be agreed upon with Melexis. The application o Wave Soldering or SMD s is allowed only ater consulting Melexis regarding assurance o adhesive strength between device and board. 9 ESD Precautions Electronic semiconductor products are sensitive to Electro Static Discharge (ESD). Always observe Electro Static Discharge control procedures whenever handling semiconductor products Page 30 o 32 EVB Description

31 EVB722 Your Notes Page 3 o 32 EVB Description

32 EVB722 0 Disclaimer ) The inormation included in this documentation is subject to Melexis intellectual and other property rights. Reproduction o inormation is permissible only i the inormation will not be altered and is accompanied by all associated conditions, limitations and notices. 2) Any use o the documentation without the prior written consent o Melexis other than the one set orth in clause is an unair and deceptive business practice. Melexis is not responsible or liable or such altered documentation. 3) The inormation urnished by Melexis in this documentation is provided as is. Except as expressly warranted in any other applicable license agreement, Melexis disclaims all warranties either express, implied, statutory or otherwise including but not limited to the merchantability, itness or a particular purpose, title and non-inringement with regard to the content o this documentation. 4) Notwithstanding the act that Melexis endeavors to take care o the concept and content o this documentation, it may include technical or actual inaccuracies or typographical errors. Melexis disclaims any responsibility in connection herewith. 5) Melexis reserves the right to change the documentation, the speciications and prices at any time and without notice. Thereore, prior to designing this product into a system, it is necessary to check with Melexis or current inormation. 6) Melexis shall not be liable to recipient or any third party or any damages, including but not limited to personal injury, property damage, loss o proits, loss o use, interrupt o business or indirect, special incidental or consequential damages, o any kind, in connection with or arising out o the urnishing, perormance or use o the inormation in this documentation. 7) The product described in this documentation is intended or use in normal commercial applications. Applications requiring operation beyond ranges speciied in this documentation, unusual environmental requirements, or high reliability applications, such as military, medical lie-support or lie-sustaining equipment are speciically not recommended without additional processing by Melexis or each application. 8) Any supply o products by Melexis will be governed by the Melexis Terms o Sale, published on Melexis NV. All rights reserved. For the latest version o this document, go to our website at: Or or additional inormation contact Melexis Direct: Europe, Arica: Americas: Asia: Phone: Phone: Phone: sales_europe@melexis.com sales_usa@melexis.com sales_asia@melexis.com ISO/TS 6949 and ISO400 Certiied Page 32 o 32 EVB Description