MLX to 930MHz FSK/OOK Receiver

Transcription

1 Features Two RF s for antenna diversity, LNA cascading or differential feeding Integrated IF filter Integrated FSK and OOK demodulator Fully integrated PLL-based synthesizer Wide operating voltage Very low standby current consumption Low operating current consumption Average and peak detection data slicer mode Analog RSSI output with high dynamic range Noise cancellation filter MCU clock output High frequency accuracy 32-pin QFN package Ordering Code Product Code Temperature Code Package Code Option Code Packing Form Code MLX72 K LQ AAA-000 RE Legend: Temperature Code: K for Temperature Range -40 C to 25 C Package Code: LQ for QFN Packing Form: RE for Reel Ordering example: MLX72KLQ-AAA-000-RE Application Examples Pin Description Automotive RKE TPMS Smart metering (AMR) Home and building automation Consumer remote controls Alarm and security systems Low power telemetry systems Garage and door openers LNAI LNAO MIXP MIXN LNAO2 LNAI2 LNASEL RFSEL top DTAO CLKO IFSEL MLX72 RSSI CINT PDN PDP SLC DFO DF bottom MIXO IFAP IFAN MODSEL SLCSEL DF2 ROI General Description The MLX72 is a highly-integrated single-channel/dual-band RF receiver based on a double-conversion super-heterodyne architecture. It can receive FSK and OOK modulated signals. The IC is designed for general purpose applications for example in the European bands at 433MHz and 868MHz or for similar applications in North America or Asia, for example at 35MHz or 95MHz Page of 29 Data Sheet

2 Table of Contents Theory of Operation General Technical Data Overview Block Diagram Operating Modes LNA Selection Mixer Section IF Filter IF Amplifier PLL Synthesizer Reference Oscillator Clock Output FSK Demodulator Baseband Data Path Data Filter Data Slicer Averaging Detection Mode Peak Detection Mode....6 Data Output and Noise Cancellation Filter Functional Description Frequency Planning Calculation of Frequency Settings Standard Frequency Plans /868MHz Frequency Diversity Pin Definitions and Descriptions Technical Data Absolute Maximum Ratings Normal Operating Conditions DC Characteristics AC System Characteristics External Components Test Circuit Page 2 of 29 Data Sheet

3 5. Antenna Diversity Application Circuit Component List for Fig Package Description Standard Information Regarding Manufacturability of Melexis Products with Different Soldering Processes ESD Precautions Disclaimer Contact Information Page 3 of 29 Data Sheet

4 Theory of Operation. General The MLX72 receiver architecture is based on a double-conversion super-heterodyne approach. The two LO signals are derived from an on-chip integer-n PLL frequency synthesizer. The PLL reference frequency is derived from a crystal (XTAL). As the first intermediate frequency (IF) is very high, a reasonably high degree of image rejection is provided even without using an RF front-end filter. At applications OOKing for very high image rejections, cost-efficient RF front-end filtering can be realized by using a SAW filter in front of the LNA. The second mixer MIX2 is an image-reject mixer. The receiver signal chain can be setup by one or two low noise amplifiers (LNA, LNA2), two downconversion mixers (MIX, MIX2), an on-chip IF filter (IFF) as well as an IF amplifier (IFA). By choosing the required modulation via an FSK/OOK switch (at pin MODSEL), either the on-chip FSK demodulator (FSK DEMOD) or the RSSI-based OOK detector is selected. A second order data filter (OA) and a data slicer (OA2) follow the demodulator. The data slicer threshold can be generated from the mean-value of the data stream or by means of the positive and negative peak detectors (PKDET+/-). Some post-processing of the data output signal can be performed by means a noise cancellation filter (NCF). The dual LNA configuration can be used for antenna space diversity or antenna frequency diversity or to setup an LNA cascade (to further improve the sensitivity). Another option is to set up the two LNAs for feeding the RF signal differentially. A sequencer circuit (SEQ) controls the timing during start-up. This is to reduce start-up time and to minimize power dissipation. A clock output, which is a divide-by-8 version of the crystal oscillator signal, can be used to drive a microcontroller. The clock output is an open drain and gets activated only if a loading resistor is connected to positive supply..2 Technical Data Overview Input frequency ranges: 300 to 470MHz 60 to 930MHz Power supply range: 2. to 5.5V Temperature range: -40 to +25 C Shutdown current: 50 na Operating current: 0.0 to.ma FSK sensitivity: -07dBm* (433MHz) OOK sensitivity: -2dBm* (433MHz) Internal IF:.8MHz with 300kHz 3dB bandwidth FSK deviation range: ±0kHz to ±Hz Image rejection: 65dB st IF (with external RF front-end filter) 25dB 2 nd IF (internal image rejection) Maximum data rate: 50kps RZ (bi-phase) code, ps NRZ Spurious emission: < -54dBm Usable RSSI range: 45 to 55dB Crystal frequency: 6 to 27MHz MCU clock frequency: 2.0 to 3.4MHz * at 4kbps NRZ, BER = 30-3, at LNA pins Page 4 of 29 Data Sheet

5 .3 Block Diagram 2 LNAI LNA LNASEL 32 LNAI2 LNA2 8 7 RFSEL 3 TEST 26 3 LNAO 6 MIXP MIXN MIX LO SEQ BIAS 30 LNAO2 ENRX N counter VCO 0 MIXO MIX2 LO2 IFF N2 counter 2 3 PFD RO IFA LF CP DIV IFSEL ROI 24 RSSI 28 ASK FSK FSK DEMOD CLKO 4 5 MODSEL SW SLCSEL SW DF 9 SLC 6 DF2 OA PKDET+ PKDET _ OA2 NCF DFO 8 20 PDP PDN 2 DTAO 29 CINT 23 Fig. : MLX72 block diagram The MLX72 receiver IC consists of the following building blocks: PLL synthesizer (PLL SYNTH) to generate the first and second local oscillator signals LO and LO2. The PLL SYNTH consists of a fully integrated voltage-controlled oscillator (VCO), a distributed feedback divider chain (N,N2), a phase-frequency detector (PFD) a charge pump (CP), a loop filter (LF) and a crystal-based reference oscillator (RO). Two low-noise amplifiers (LNA, LNA2) for high-sensitivity RF signal reception First mixer (MIX) for down-conversion of the RF signal to the first IF (intermediate frequency) Second mixer (MIX2) with image rejection for down-conversion from the first to the second IF IF Filter (IFF) with a.8mhz center frequency and a 300kHz 3dB bandwidth IF amplifier (IFA) to provide a high voltage gain and an RSSI signal output FSK demodulator (FSK DEMOD) Operational amplifiers OA and OA2 for low-pass filtering and data slicing, respectively Positive (PKDET+) and negative (PKDET-) peak detectors Switches SW to select between FSK and OOK as well as SW2 to chose between averaging or peak detection mode. Noise cancellation filter (NCF) Sequencer circuit (SEQ) and biasing (BIAS) circuit Clock output (DIV8) Page 5 of 29 Data Sheet

6 .4 Operating Modes The receiver offers two operating modes selectable by setting the corresponding logic level at pin ENRX. ENRX Description 0 Shutdown mode Receive mode Note: ENRX is pulled down internally. The receiver s start-up procedure is controlled by a sequencer circuit. It performs the sequential activation of the different building blocks. It also initiates the pre-charging of the data filter and data slicer capacitors in order to reduce the overall start-up time and current consumption during the start-up phase. At ENRX = 0, the receiver is in shutdown mode and draws only a few na. The bias system and the reference oscillator are activated after enabling the receiver by a positive edge at pin ENRX. The crystal oscillator (RO) is turned on first. Then the crystal oscillation amplitude builds up from noise. After reaching a certain amplitude level at pin ROI, the whole IC is activated and draws the full receive mode current consumption I CC. This event is used to start the pre-charging of the external data path capacitors. Pre-charging is finished after 5504 clock cycles. After that time the data output pin DTAO output is activated. ENRX I CC I RO I SDN DTAO Hi-Z valid data Hi-Z t onro t SEQ t on RX Fig. 2: Timing diagram of start-up and shutdown behavior.5 LNA Selection The receiver features two identical LNAs. Each LNA is a cascode amplifier with a voltage gain of approximately 8dB. The actual gain depends on the antenna matching network at the s and the LC tank network between the LNA outputs and mixer. LNA operation can be controlled by the LNASEL pin. LNASEL Description 0 LNA active, LNA2 shutdown Hi-Z LNA and LNA2 active LNA shutdown, LNA2 active Pin LNASEL is internally pulled to /2 during receive mode. Therefore both LNAs are active if LNASEL is left floating (Hi-Z state) Page 6 of 29 Data Sheet

7 .6 Mixer Section The mixer section consists of two mixers. Both are double-balanced mixers. The second mixer is built as an image rejection mixer. The first mixer s s (MIXP and MIXN) are functionally the same. For single-ended drive, the unused has to be tied to ground via a capacitor. A soft band-pass filter is placed between the mixers. RFSEL Description 0 Input frequency range 300 to 470MHz Input frequency range 60 to 930MHz Pin RFSEL is used to select the required RF band. The LO frequencies and the proper sidebands for image suppression will be set accordingly..7 IF Filter The MLX72 comprises an internal IF filter with a -3dB bandwidth (B3dB) of 300kHz and a -40dB attenuation bandwidth (B40dB) of.4mhz. This filter contains three capacitively coupled biquad stages that represent resonant tanks at a filter center frequency (f cent ) of.8mhz 0-20 gain/db B 3dB B 40dB Fig. 3: IF filter tolerance scheme IF Amplifier After having passed the IF filter, the signal is amplified by a high-gain limiting amplifier. It consists of several AC-coupled gain stages with a bandwidth of 400kHz to MHz. The overall small-signal pass-band gain is about 80dB. A received-signal-strength indicator (RSSI) signal is generated within the IF amplifier and is available at pin RSSI. f cent f IF2.9 PLL Synthesizer The PLL synthesizer consists of a fully integrated voltage-controlled oscillator that runs at 400MHz to 640MHz, a distributed feedback divider chain, an edge-triggered phase-frequency detector, a charge pump, a loop filter and a crystal-based reference oscillator. The PLL is used for generating the LO signals. The LO is directly taken from the VCO output, and the LO2 is derived from the LO signal passing the N counter. Another counter N2 follows N to provide the comparison frequency to the PFD. The overall feedback divider ratio N tot is 24. The values of N and N2 can be changed via pin RFSEL for selecting the LO and LO2 frequencies. The table below shows the range of the LO frequencies. RFSEL f LOmin [MHz] f LOmax [MHz] f LO2min [MHz] f LO2max [MHz] N N 2 N tot Page 7 of 29 Data Sheet

8 .0 Reference Oscillator A Colpitts crystal oscillator with integrated functional capacitors is used as the reference oscillator (RO) of the PLL synthesizer. The equivalent capacitance CRO offered to the crystal at pin ROI is about 8pF. The crystal oscillator features an amplitude control loop. This is to assure a very stable frequency over the specified supply voltage and temperature range together with a short start-up time. A buffer amplifier with hysteresis is between RO and PFD. Also a clock divider follows the buffer.. Clock Output The clock output pin CKOUT is an open-drain output. For power saving reasons, the circuit is only active if an external pull-up resistor RCL is applied to the pin. Furthermore, RCL can be used to adjust the clock waveform. It forms an RC low-pass together with the capacitive load at the pin, the parasitics of the PCB and the capacitance of the external circuitry (e.g. a microcontroller). The clock output feature is disabled if pin CKOUT is connected to ground or left open. CLKO RCL RO output DIV8 Control logic C L Fig. 4: Clock output implementation.2 FSK Demodulator The integrated FSK demodulator is based on a phase-coincidence demodulator principle. An injection-locked oscillator (ILO) is used as a frequency-dependent phase shifter. This topology features a good linearity of the frequency-phase relationship over the entire locking range. The type of demodulator has no built-in constraints regarding the modulation index. It also offers a wide carrier acceptance range. In addition, the demodulator provides an AFC loop for correcting the remaining free-running frequency error and drift effects, and also to remove possible frequency offsets between transmitter and receiver frequencies. The AFC loop features a dead band which means that the AFC loop is only closed if the demodulator output voltage leaves the linear region of the demodulator. Most of the time, the control loop is open. This leads to several advantages. The AFC loop bandwidth can be high and therefore the reaction time is short. Furthermore the demodulator itself has no low-end cut-off frequency. The FSK demodulator has a negative control slope, this means the output voltage decreases by increasing the IF2 frequency. This guarantees an overall positive slope because the mixer section converts the receive frequency to IF2 either with high-low or low-high side injection. The FSK demodulator is turned off during OOK demodulation Page 8 of 29 Data Sheet

9 .3 Baseband Data Path The baseband data path can be divided into a data filter section and a data slicer section. MLX72 MODSEL DF DF2 ASK data filter FSK SW OA DF0 PKDET+ data slicer PDP S4 S S2 SLC SLCSEL switches S3 PKDET _ S5 PDN S6 OA2 Control logic DTAO Fig. 5: Block diagram of the data path CINT The data filter is either connected to the OOK or to the FSK demodulation output. Pin MODSEL can be used to set the internal switch SW accordingly. MODSEL Description 0 OOK demodulation FSK demodulation For OOK demodulation, the RSSI signal of the IFA is used. During FSK demodulation, SW is connected to the FSK demodulator output. The SLCSEL pin is used to control the internal switches depending on operating and slicer mode. Pins DF, DF2, DFO, SLC and DTAO are left floating during shutdown mode. So they are in a high-z state Page 9 of 29 Data Sheet

10 .4 Data Filter MLX72 The data filter is formed by the operational amplifier OA, two internal resistors and two external capacitors. It is implemented as a 2 nd order Sallen-Key filter. The low pass filter characteristic rejects noise at higher frequencies and therefore leads to an increased sensitivity. CF DF CF2 DF2 data filter OA DF0 Fig. 6: Data filter The filter s pole locations can be set by the external capacitors CF and CF2. The cut-off frequency f c has to be adjusted according to the transmission data rate R. It should be set to approximately.5 times the fastest expected data rate. For a Butterworth filter characteristic, the data filter capacitors can be calculated as follows. CF 2 π f c CF CF2 2 R RZ [kbit/s] R NRZ [kbit/s] fc [khz] CF [pf] CF2 [pf] Data Slicer The purpose of the data slicer is to convert the filtered data signal into a digital output. It can therefore be considered as an analog-to-digital converter. This is done by using the operational amplifier OA2 as a comparator that compares the data filter output with a threshold voltage. The threshold voltage can be derived in two different ways from the data signal. SLCSEL Description 0 Averaging detection mode Peak detection mode Page 0 of 29 Data Sheet

11 .5. Averaging Detection Mode The simplest configuration is the averaging or RC integration method. Here an on-chip resistor together with an external slicer capacitor (CSL) are forming an RC low-pass filter. This way the threshold voltage automatically adjusts to the mean or average value of the analog voltage. To create a stable threshold voltage, the cut-off frequency of the low pass has to be lower than the lowest signal frequency. τ AVG CSL τ AVG.5 R RZ data filter SLCSEL data slicer PKDET+ S2 switches PKDET _ S4 S S3 S5 S6 PDP SLC CSL PDN A long string of zeros or ones, like in NRZ codes, can Control cause a drift of the threshold. That s why a Manchester OA2 DTAO logic or other DC-free coding scheme works best. CINT The peak detectors are disabled during averaging detection mode, and the output pins PDP and PDN are pulled to ground (S4, S6 are closed). Fig. 7: Data path in averaging detection mode.5.2 Peak Detection Mode Peak detection mode has a general advantage over averaging detection mode because of the part attack and slow release times. Peak detection should be used for all non-dc-free codes like NRZ. In this configuration the threshold is generated by using the positive and negative peak detectors. The slicer comparator threshold is set to the midpoint between the high output and the low output of the data filter by an on-chip resistance divider. Two external capacitors (CP, CP2) determine the release times for the positive and negative envelope. The two on-chip resistors provide a path for the capacitors to discharge. This allows the peak detectors to dynamically follow peak changes of the data filter output voltage. The attack times are very short due to the high peak detector load currents of about 500uA. The decay time constant mainly depends on the longest time period without bit polarity change. This corresponds to the maximum number of consecutive bits with the same polarity (N MAX ). CP/2 τ DECAY N τ DECAY R MAX NRZ Fig. 8: data filter SLCSEL PKDET+ S2 switches PKDET _ OA2 data slicer Data path in peak detection mode S S3 Control logic S4 S5 S6 PDP SLC PDN DTAO CINT CP CP2 If the receiver is in shutdown mode and peak detection mode is selected then the peak detectors are disabled and the output of the positive peak detector (PDP) is connected to (S4 is closed) and the output of the negative peak detector (PDN) is connected to (S5 is closed). This guarantees the correct biasing of CP and CP2 during start-up Page of 29 Data Sheet

12 .6 Data Output and Noise Cancellation Filter The data output pin DTAO delivers the demodulated data signal which can be further processed by a noise cancellation filter (NCF). The NCF can be disabled if pin CINT is connected to ground. In this case the multiplexer (MUX) connects the receiver output DTAO directly to the data slicer output. data slicer output MUX DTAO Fig. 9: Data output and noise filter NCF CINT noise cancellation filter CF3 The noise cancellation filter can suppress random pulses in the data output which are shorter than t min CF3 50 tmin R NRZ R RZ 6 The NCF can also operate as a muting circuit. So if the RF signal is below sensitivity level (or if no RF signal is applied) then the data output will go to a constant DC level (either HIGH or LOW). This can be achieved by setting the bandwidth of the preceding data filter (sec.3) about 0 times higher than the bandwidth of the NCF. Further the data filter cutoff frequency must be higher than the data rate, so the noise pulses are shorter than the shortest data pulse. Otherwise, the NCF will not be able to distinguish between noise and data pulses. Having the NCF activated is a good means for reducing the computing power of the microcontroller that follows the receiver IC for further data processing. In contrast to a conventional muting (or squelch) circuit, this topology does not need the RSSI signal for level indication. The filtering process is done by means of an analogue integrator. The cut-off frequency of the NCF is set by the external capacitor connected to pin CINT. This capacitor C F3 should be set according to the maximum data rate. Below table provides some recommendations.. During receiver start-up a sequencer checks if pin CINT is connected to a capacitor or to ground. The maximum value of C F3 should not exceed 2nF. This defines the lowest data rate that can be processed if the noise cancellation filter is activated. R RZ [kbit/s] R NRZ [kbit/s] C F3 [nf] Page 2 of 29 Data Sheet

13 In shutdown mode pin DTAO is set to Hi-Z state Page 3 of 29 Data Sheet

14 2 Functional Description 2. Frequency Planning Because of the double conversion architecture that employs two mixers and two IF signals, there are four different combinations for injecting the LO and LO2 signals: LO high side and LO2 high side: receiving at f RF (high-high) LO high side and LO2 low side: receiving at f RF (high-low) LO low side and LO2 high side: receiving at f RF (low-high) LO low side and LO2 low side: receiving at f RF (low-low) As a result, four different radio frequencies (RFs) could yield one and the same second IF (IF2). Fig. 0 shows this for the case of receiving at f RF (high-high). In the example of Fig. 0, the image signals at f RF (lowhigh) and f RF (low-low) are suppressed by the bandpass characteristic provided by the RF front-end. The bandpass shape can be achieved either with a SAW filter (featuring just a couple of MHz bandwidth), or by the tank circuits at the LNA and output (this typically yields 30 to 60MHz bandwidth). In any case, the high value of the first IF (IF) helps to suppress the image signals at f RF (low-high) and f RF (low-low). The two remaining signals at IF resulting from f RF (high-high) and f RF (high-low) are entering the second mixer MIX2. This mixer features image rejection with so-called single-sideband (SSB) selection. This means either the upper or lower sideband of IF can be selected. In the example of Fig. 0, LO2 high-side injection has been chosen to select the IF2 signal resulting from f RF (high-high). f LO2 f LO2 f RF f RF f LO f RF f RF Fig. 0: The four receiving frequencies in a double conversion superhet receiver It can be seen from the block diagram of Fig. that there is a fixed relationship between the LO signal frequencies (f LO, f LO2 ) and the reference oscillator frequency f RO. f LO N f LO2 f LO2 N 2 f RO The operating frequency of the internal IF filter (IFF) and FSK demodulator (FSK DEMOD) are.8mhz. Therefore the second IF (IF2) is set to.8mhz as well Page 4 of 29 Data Sheet

15 2.2 Calculation of Frequency Settings The receiver has two predefined receive frequency plans which can be selected by the RFSEL control pin. Depending on the logic level of RFSEL pin the sideband selection of the second mixer and the counter settings for N and N 2 are changed accordingly. RFSEL Injection f RFmin [MHz] f RFmax [MHz] N N 2 0 high-low low-high The following table shows the relationships of several internal receiver frequencies for the two frequency ranges. f RF [MHz] f IF f LO f LO2 f RO 300 to to 930 f f RF RF Nf N Nf N IF2 IF2 N(f N RF N(f N RF f f IF2 IF2 ) ) f RF f N IF2 f RF f N IF2 f RF f IF2 N (N ) 2 f RF f IF2 N (N ) 2 Given IF2 =.8MHz and the corresponding N, N 2 counter settings, above equations can be transferred into the following table. f RF [MHz] f IF f LO f LO2 f RO 300 to 470 f RF 7.2MHz 4(f RF.8MHz ) f RF.8MHz 3 3 f RF.8MHz 8 60 to 930 f RF 3.6MHz 2(f RF.8MHz ) 3 f RF.8MHz Page 5 of 29 Data Sheet

16 2.3 Standard Frequency Plans IF2 =.8MHz RFSEL f RF [MHz] f IF [MHz] f LO [MHz] f LO2 [MHz] f RO [MHz] /868MHz Frequency Diversity The receiver s multi-band functionality can be used to operate at two different frequency bands just by changing the logic level at pin RFSEL and without changing the crystal. This feature is applicable for common use of the 433 and 868MHz bands. Below table shows the corresponding frequency plans. IF2 =.8MHz RFSEL f RF [MHz] f IF [MHz] f LO [MHz] f LO2 [MHz] f RO [MHz] Page 6 of 29 Data Sheet

17 3 Pin Definitions and Descriptions Pin No. Name I/O Type Functional Schematic Description 3 LNAO analog output Vbias Vbias LNAO 3 LNA output LNAI analog LNAI k LNA 2 ground negative supply voltage 4 MIXP analog Vbias MIX positive 5 MIXN analog MIXP 4 2k 2k MIXN 5 MIX negative 6 LNAO2 analog output Vbias Vbias LNAO2 6 LNA output 2 8 LNAI2 analog LNAI2 8 k LNA 2 7 ground negative supply voltage 9 supply positive supply voltage 0 MIXO analog output not used pin left open mixer 2 output ground negative supply voltage 2 IFAP analog 3 IFAN analog 4 MODSEL CMOS not used pins left open IF amplifier positive IF amplifier negative modulation select MODSEL Page 7 of 29 Data Sheet

18 Pin No. Name I/O Type Functional Schematic Description 5 SLCSEL CMOS slicer mode select SLCSEL DF2 analog I/O data filter connection 2 DF DF analog I/O DF data filter connection 8 DFO analog output data filter output DFO SLC analog SLC slicer reference 20 PDP analog output peak detector positive output PDP PDN analog output peak detector negative output PDN Page 8 of 29 Data Sheet

19 Pin No. Name I/O Type Functional Schematic Description 22 supply positive supply voltage 23 CINT analog CINT 23 capacitor for noise cancellation filter pin must be connected to ground if noise cancellation filter is not used 24 RSSI analog output receive signal strength indication RSSI k 25 ROI analog ROI 6k reference oscillator TEST CMOS 27 IFSEL CMOS 28 CLKO CMOS output not used connect to ground not used connect pin to ground CLKO 28 test pin IF select clock output connect pull-up resistor to activate clock 29 DTAO CMOS output data output DTAO ENRX CMOS enable RX mode control ENRX k Page 9 of 29 Data Sheet

20 Pin No. Name I/O Type Functional Schematic Description 3 RFSEL CMOS receive frequency select RFSEL LNASEL CMOS LNASEL k 500k LNA select Page 20 of 29 Data Sheet

21 4 Technical Data 4. Absolute Maximum Ratings Operation beyond absolute maximum ratings may cause permanent damage of the device. Parameter Symbol Condition Min Max Unit Supply voltage V CC 0 7 V Input voltage V IN -0.3 V CC +0.3 V Storage temperature T STG C Junction temperature T J 50 C Thermal Resistance R thja 22 K/W Power dissipation P diss 0.2 W Electrostatic discharge V ESD HBM according to MIL STD 833D, method ± kv 4.2 Normal Operating Conditions Parameter Symbol Condition Min Max Unit Supply voltage V CC V Operating temperature T A C version C Operating temperature T A K version C Input low voltage (CMOS) V IL ENRX, SEL pins 0.3*V CC V Input high voltage (CMOS) V IH ENRX, SEL pins 0.7*V CC V Input frequency range f RF RFSEL= RFSEL= MHz First IF range f IF RFSEL= RFSEL= MHz LO range (VCO frequency) f LO f LO = 24*f REF MHz LO2 range f LO2 RFSEL=0, f LO2 = f LO / RFSEL=, f LO2 = f LO / MHz XOSC frequency f REF set by the crystal 6 27 MHz CLKO frequency f CLK f CLK = f REF / MHz FSK deviation f ±0 ±00 khz Data rate OOK Data rate FSK R OOK R FSK bi-phase code 50 NRZ 00 bi-phase code 50 NRZ 00 kbps Page 2 of 29 Data Sheet

22 4.3 DC Characteristics all parameters under normal operating conditions, unless otherwise stated; typical values at T A = 23 C and V CC = 3 V, all parameters based on test circuits as shown Fig. Parameter Symbol Condition Min Typ Max Unit Operating Currents Shutdown current Supply current reference oscillator Supply current, FSK Supply current, OOK I SDN ENRX=0, T A = 85 C na ENRX=0, T A = 25 C 4 µa I RO ENRX=, t < t onro.5 ma I FSK I OOK Digital Pin Characteristics (except of LNASEL) ENRX=, MODSEL= SLCSEL=0 LNASEL=0 or ENRX=, MODSEL= 0 SLCSEL=0 LNASEL=0 or 0.2 ma 9.8 ma Input low voltage (CMOS) V IL ENRX, SEL pins 0.3*V CC V Input high voltage (CMOS) V IH ENRX, SEL pins 0.7*V CC V Pull down current ENRX pin I PDEN ENRX= µa Low level current ENRX pin I INLEN ENRX=0 µa High level current I INHSEL SEL pins µa Low level current I INLSEL SEL pins µa LNASEL Pin Characteristics Input voltage LNA active V LNASEL ENRX= 0.*V CC V Input voltage LNA2 active V LNASEL2 ENRX= 0.9*V CC V DTAO Pin Characteristics Output low voltage Output high voltage V OL V OH DTAO pin, I SINK = 600µA DTAO pin, I SOURCE = 600µA 0.3*V CC V 0.7*V CC V Page 22 of 29 Data Sheet

23 4.4 AC System Characteristics all parameters under normal operating conditions, unless otherwise stated; typical values at T A = 23 C and V CC = 3 V, all parameters based on test circuits as shown Fig. Parameter Symbol Condition Min Typ Max Unit Receive Characteristics Input Sensitivity ) MODSEL RFSEL FSK 35MHz P min MHz P min MHz P min MHz P min4-02 dbm OOK 35MHz P min MHz P min MHz P min MHz P min8-05 dbm Maximum signal FSK P max, FSK MODSEL= -0 dbm Maximum signal OOK P max, OOK MODSEL=0, M>70dB -0 dbm Spurious emission P spur -54 dbm Image rejection st IF IR w/o SAW filter 20 db Image rejection 2 nd IF IR 2 25 db LNA Parameters Voltage gain G LNA depends on external LC tank IF Filter Parameters 8 db Center frequency f cent.8 MHz 3dB bandwidth B 3dB 300 khz 40dB bandwidth B 40dB.4 MHz IF Amplifier / RSSI Operating frequency f IFA 0.4 MHz RSSI usable range DR RSSI continuous range db RSSI slope S RSSI 20 mv/db FSK Demodulator Input frequency range f DEM.8 MHz Carrier acceptance range f DEM ±80 khz Demodulator sensitivity S DEM 5 mv/ khz ) at 4kbps NRZ, BER 30-3, peak detector data slicer, LNASEL = 0 or Page 23 of 29 Data Sheet

24 Baseband Data Path Parameter Symbol Condition Min Typ Max Unit Data filter bandwidth B DF depending on CF, 00 khz CF2 Peak detector load current I PKD 500 µa Start-up Parameters Reference start-up time oscillator t onro depending on crystal parameters µs Sequencer time t SEQ 5504 / f REF µs Receiver start-up time t onrx t onro + t SEQ 0.6 ms Frequency Stability Frequency pulling by supply voltage df ±3 ppm/v 4.5 External Components Parameter Symbol Condition Min Max Unit Crystal Parameters Crystal frequency f 0 fundamental mode, AT 6 27 MHz Load capacitance C L 0 5 pf Static capacitance C 0 5 pf Series resistance R 60 Noise Cancellation Filter Integrator capacitor CF3 depends on data rate 2 nf Clock Output Pull-up resistor RCL 600 Load capacitance C L 50 pf Page 24 of 29 Data Sheet

25 5 Test Circuit 5. Antenna Diversity Application Circuit FSK ASK output LNASEL RFSEL ENRX CLKO RCL XTAL CX RSSI 50 L C3 LNAI RFSEL ENRX DTAO CLKO IFSEL TEST ROI RSSI 24 CRS CB3 L2 C4 C5 C LNAO MIXP MIXN LNAO2 MLX72 32L QFN 5x5 CINT PDN 2 PDP 20 SLC 9 CP CF3 CP2 CB2 50 L3 C9 7 8 LNAI2 MIXO IFAP IFAN MODSEL SLCSEL DF DFO 8 DF 7 CF CB FSK ASK CF2 CB0 Fig. : Antenna diversity circuit schematic, peak detectors activated Page 25 of 29 Data Sheet

26 5.. Component List for Fig. Part Size 35 MHz MHz MHz 95 MHz Tol. Description C pf 00 pf 00 pf 00 pf 5% LNA filtering capacitor C pf 3.9 pf 2.2 pf.5 pf 5% LNA output tank capacitor C pf 00 pf 00 pf 00 pf 5% MIX positive matching capacitor C pf 00 pf 00 pf 00 pf 5% MIX negative matching capacitor C pf 00 pf 00 pf 00 pf 5% LNA filtering capacitor CB nf 33 nf 33 nf 33 nf 0% decoupling capacitor CB pf 330 pf 330 pf 330 pf 0% decoupling capacitor CB pf 330 pf 330 pf 330 pf 0% decoupling capacitor CB pf 330 pf 330 pf 330 pf 0% decoupling capacitor CF pf 680 pf 680 pf 680 pf 0% CF pf 330 pf 330 pf 330 pf 0% CF value according to the data rate connected to ground if noise filter not used 0% CP nf 33 nf 33 nf 33 nf 0% data low-pass filter capacitor, for data rate of 4 kbps NRZ data low-pass filter capacitor, for data rate of 4 kbps NRZ optional capacitor for noise cancellation filter positive PKDET capacitor, for data rate of 4 kbps NRZ CP nf 33 nf 33 nf 33 nf 0% negative PKDET capacitor, for data rate of 4 kbps NRZ CRS 0603 nf nf nf nf 0% RSSI output low pass capacitor CSL nf 00 nf 00 nf 00 nf for averaging detection mode only 0% data slicer capacitor, for data rate of 4 kbps NRZ CX pf 27 pf 27 pf 27 pf 5% crystal series capacitor L nh 27 nh 0 0 5% matching inductor L nh 5 nh 3.9 nh 3.9 nh 5% LNA output tank inductor L nh 27 nh 0 0 5% matching inductor RCL k 3.3 k 3.3 k 3.3 k 5% XTAL Note: SMD 5x MHz MHz MHz 20ppm cal., 30ppm temp. NIP not in place, may be used optionally MHz optional CLK output resistor, to clock output signal generated fundamental-mode crystal from Telcona, or equivalent part Page 26 of 29 Data Sheet

27 6 Package Description The device MLX72 is RoHS compliant. D 24 7 A E e b A A exposed pad E2 L D2 The exposed pad is not connected to internal ground, it should not be connected to the PCB. Fig. 2: 32L QFN 5x5 Quad all Dimension in mm D E D2 E2 A A A3 L e b min max all Dimension in inch min max Page 27 of 29 Data Sheet

28 7 Standard Information Regarding Manufacturability of Melexis Products with Different Soldering Processes Our products are classified and qualified regarding soldering technology, solderability and moisture sensitivity level according to following test methods: Reflow Soldering SMD s (Surface Mount Devices) IPC/JEDEC J-STD-020 Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices (classification reflow profiles according to table 5-2) EIA/JEDEC JESD22-A3 Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing (reflow profiles according to table 2) Wave Soldering SMD s (Surface Mount Devices) and THD s (Through Hole Devices) EN Resistance of plastic- encapsulated SMD s to combined effect of moisture and soldering heat EIA/JEDEC JESD22-B06 and EN Resistance to soldering temperature for through-hole mounted devices Iron Soldering THD s (Through Hole Devices) EN Resistance to soldering temperature for through-hole mounted devices Solderability SMD s (Surface Mount Devices) and THD s (Through Hole Devices) EIA/JEDEC JESD22-B02 and EN Solderability For all soldering technologies deviating from above mentioned standard conditions (regarding peak temperature, temperature gradient, temperature profile etc) additional classification and qualification tests have to be agreed upon with Melexis. The application of Wave Soldering for SMD s is allowed only after consulting Melexis regarding assurance of adhesive strength between device and board. Melexis recommends reviewing on our web site the General Guidelines soldering recommendation ( as well as trim&form recommendations ( Melexis is contributing to global environmental conservation by promoting lead free solutions. For more information on qualifications of RoHS compliant products (RoHS = European directive on the Restriction Of the use of certain Hazardous Substances) please visit the quality page on our website: 8 ESD Precautions Electronic semiconductor products are sensitive to Electro Static Discharge (ESD). Always observe Electro Static Discharge control procedures whenever handling semiconductor products Page 28 of 29 Data Sheet

29 9 Disclaimer Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Melexis reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with Melexis for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by Melexis for each application. The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of Melexis rendering of technical or other services. 205 Melexis NV. All rights reserved. 0 Contact Information For the latest version of this document, go to our website at Or for additional information contact Melexis Direct: Europe, Africa, Asia: America: Phone: Phone: sales_europe@melexis.com sales_usa@melexis.com ISO/TS 6949 and ISO400 Certified Page 29 of 29 Data Sheet