4 Stereo Inputs, 2W BTL Stereo Output 16-bit Stereo DAC and Volume Control

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1 4 Stereo Inputs, W BTL Stereo Output 6-bit Stereo DAC and Volume Control FEATURES Operation range:.4v ~ 6.5V Volume control range Gain: 0 to db, 3dB/step Attenuation: 0 to 77.5dB,.5dB/step 4 stereo inputs (mixed with an audio DAC) Output mode : Speaker( BTL)/Headphone(SE) BTL Output power, THDN=%, Stereo Input R L =4Ω, W at 5V, 0.8W at 3.3V, 360mW at.4v R L =8Ω,.3W at 5V, 0.53W at 3.3V, 50mW at.4v BTL Output power, DAC Input R L =4Ω,.6W at 5V, 0.70W at 3.3V, 340mW at.4v R L =8Ω, 0.83W at 5V, 0.35W at 3.3V, 70mW at.4v Built-in 6-bit Audio DAC Audio format : I S, Right justified, Left justified Control interface : I C Excellent Power Supply Rejection Ratio(PSRR) Flexibility power management Component less Reduce pop noise circuit Housed in TSSOP8 package, enhanced thermal PAD APPLICATIONS Multimedia system, Portable Digital Audio. DESCRIPTION The is a 6-bits voltage-output Digital-to-Analog Converter (DAC) integrated class AB stereo headphone driver and stereo speaker power amplifier. It can drive W of continuous average power into a dual 4Ω bridged-tied (BTL) speaker or * 90mW into stereo 3Ω single ended (SE) headphone. The 6-bit DAC supports general and popular formats as IS, Right justified. The volume control offers wide range of gain and attenuation for 4-set stereo input. All of the functions are set by IC interface. The has good feature for portable equipment, including wide voltage operation.4v ~ 6.5V, low power consumption, flexible power management, component less and small package TSSOP8, make the ideally suitable for use in the portable digital audio equipments. BLOCK DIAGRAM REV 4 /8

2 PIN CONFIGURATION Symbol Pin Description WS Audio word select input BCK Audio bit clock input CAP 3 Capacitor connected RIN 4 Right channel input RIN 5 Right channel input RIN3 6 Right channel input 3 RIN4 7 Right channel input 4 V SS 8 Negative supply voltage PV DDR 9 Positive supply voltage for right channel of power amplifier OUTR- SE right channel output or negative 0 output of BTL right channel OUTR Positive output of BTL right channel GND Connected to ground PV SSR Negative supply voltage for right 3 channel of power amplifier DACR 4 DAC right channel output DACL 5 DAC Left channel output PV SSL Negative supply voltage for left channel 6 of power amplifier GND 7 Connected to ground OUTL 8 Positive output of BTL left channel OUTL- SE left channel output or negative 9 output of BTL left channel PV DDL Positive supply voltage for left channel 0 of power amplifier Positive supply voltage V DD LIN4 Left channel input 4 LIN3 3 Left channel input 3 LIN 4 Left channel input LIN 5 Left channel input SDA 6 I C data input SCL 7 I C clock input DATA 8 Audio data input WS 8 DATA BCK 7 SCL CAP 3 6 SDA RIN 4 5 LIN RIN 5 4 LIN RIN3 6 3 LIN3 RIN4 7 LIN4 VSS 8 VDD PVDDR 9 0 PVDDL OUTR- 0 9 OUTL- OUTR 8 OUTL GND 7 GND PVSSR 3 DACR 4 5 DACL 6 PVSSL Note:. SE: Single Ended. BTL: Bridged-Tied Load REV 4 /8

3 ORDERING INFORMATION Package Part number Packaging Marking Transport Media 8Pin TSSOP (lead free) TGTR G.5k Units Tape and Reel 8Pin TSSOP (lead free) TGU G 50 Units Tube RoHS Compliance ABSOLUTE MAXIMUM RATINGS Symbol Parameter Rating Unit VDD Supply voltage 6.5 V V ESD Electrostatic handling 000 V T STG Storage temperature range -65 to 50 T A Operating ambient temperature range -40 to 85 T J Maximum junction temperature 50 T S Soldering temperature, 0 seconds 60 R THJA Thermal resistance from junction to ambient in free air TSSOP8 (enhance thermal pad) 5 /W OPERATING RATINGS Symbol Parameter Min Typ Max Unit V DD Supply voltage V REV 4 3/8

4 5V ELECTRICAL CHARACTERISTICS (Ta=5, V DD =5V, V SS =0V, f=khz; unless otherwise specified) Symbol Parameter Conditions Min Typ Max Unit DC Characteristics V CAP Voltage at CAP V DC I Q Output DC level Quiescent current 0.5V DD 0.5V 0.5V DD DD V DD 0.5V 0.5V DD DD 0.05 All devices are active, BTL All devices are active, SE DAC PD, BTL DAC PD, SE L-ch (R-ch) PD, BTL DAC active L-ch (R-ch) PD, SE DAC active Only DAC is active All devices power down I PD Power down current All devices power down, ua except CAP=/ VDD ATT Mute attenuation -90 db GA RAN Gain/Attenuation range Gain 0 - db Attenuation db G STEP Gain step db A STEP Attenuation step db E GA Gain/Attenuation step error db V ICH Serial interface high input level V V ICL Serial interface low input level 0.8 V AC Characteristics (Stereo input) PSRR Power supply rejection ratio CS THDN S/N Po PD: Power Down Channel separation Total harmonic distortion plus Noise Signal-to-noise ratio Maximum output power BTL Mode, R L =8Ω CAP=uF, f=00hz SE Mode, R L =3Ω CAP=uF, f=00hz BTL Mode, R L =8Ω Po=W SE Mode, R L =3Ω Po=60mW SE mode, R L =3Ω, 60mW SE mode, A-weighting, 75mW BTL Mode, R L = 4Ω THDN = % BTL Mode, R L = 8Ω THDN = % SE Mode, R L = 3Ω THDN = 0.% V V ma db db db db db % db - - W W - 93m - W REV 4 4/8

5 Symbol Parameter Conditions Min Typ Max Unit Audio DAC Characteristics (sampling rate=4fs, fs= 44.kHz, f=khz) Res Resolution bits V FSDAC Full scale output voltage of DAC V FS =0.7 * V DD V FS -.5% V FS V FS.5% V CAP=uF (00Hz) 66 - PSRR Power supply rejection ratio db CAP=0uF (00Hz) 67 - CS Channel separation 88 db THDN Total harmonic distortion plus noise DAC output, R L =kω, V FS db % S/N DACPo Signal-to-noise ratio Maximum output power using DAC DAC output, R L =kω, V FS A-weighting BTL Mode, R L = 4Ω THDN = 0.33% BTL Mode, R L = 8Ω THDN = 0.5 % SE Mode, R L = 3Ω THDN = 0.04% db W W 4.4m 46m - W 3.3V ELECTRICAL CHARACTERISTICS (Ta=5, V DD =3.3V, V SS =0V, f=khz; unless otherwise specified) Symbol Parameter Conditions Min Typ Max Unit DC Characteristics I Q Quiescent current AC Characteristics (Stereo input) THDN Total harmonic distortion plus Noise All devices are active, BTL All devices are active, SE DAC PD, BTL DAC PD, SE L-ch (R-ch) PD, BTL DAC active L-ch (R-ch) PD, SE DAC active Only DAC is active SE mode, R L =3Ω, 35mW BTL Mode, R L = 4Ω THDN = % Po Maximum output power BTL Mode, R L = 8Ω THDN = % SE Mode, R L = 3Ω THDN = 0.% Audio DAC Characteristics (sampling rate=4fs, fs= 44.kHz, f=khz) THDN DACPo Total harmonic distortion plus noise Maximum output power using DAC DAC output, R L =kω, V FS BTL Mode, R L = 4Ω THDN = 0.5% BTL Mode, R L = 8Ω THDN = 0.4 % SE Mode, R L = 3Ω THDN = 0.05% REV 4 5/8 ma db % W W - 35m - W db % W W 8m 0m - W

6 .4V ELECTRICAL CHARACTERISTICS (Ta=5, V DD =.4V, V SS =0V, f=khz; unless otherwise specified) Symbol Parameter Conditions Min Typ Max Unit DC Characteristics I Q Quiescent current AC Characteristics (Stereo input) THDN Total harmonic distortion plus Noise All devices are active, BTL All devices are active, SE DAC PD, BTL DAC PD, SE L-ch (R-ch) PD, BTL DAC active L-ch (R-ch) PD, SE DAC active Only DAC is active -. - SE mode, R L =3Ω, 5mW BTL Mode, R L = 4Ω THDN = % Po Maximum output power BTL Mode, R L = 8Ω THDN = % SE Mode, R L = 3Ω THDN = 0.% Audio DAC Characteristics (sampling rate=4fs, fs= 44.kHz, f=khz) THDN DACPo Total harmonic distortion plus noise Maximum output power using DAC DAC output, R L =kω, V FS BTL Mode, R L = 4Ω THDN = 0.85% BTL Mode, R L = 8Ω THDN = 0.7 % SE Mode, R L = 3Ω THDN = 0.07% ma db % W W - 5m - W db % W W 9m 0m - W REV 4 6/8

7 TYPICAL PERFORMANCE CHARACTERISTICS (Ta=5 ; unless otherwise specified) BTL QUIESCENT CURRENT (ma) SE All Devices activate. QUIESCENT CURRENT (ma) BTL SE All Devices activate except DAC QUIESCENT CURRENT (ma) LPD or RPD DAC activates. BTL SE SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Quiescent current vs. supply voltage Quiescent current vs. supply voltage Quiescent current vs. supply voltage QUIESCENT CURRENT (ma) DAC activates only SUPPLY VOLTAGE (V) Quiescent current vs. supply voltage REV 4 7/8

8 MOSA VDD=5V, Po=W BTL mode, RL=4Ω VDD=3.3V, Po=0.8W BTL mode, RL=4Ω VDD=.4V, Po=330mW BTL mode, RL=4Ω THDN (%) THDN vs. frequency THDN (%) THDN vs. frequency THDN (%) THDN vs. frequency VDD=5V, Po=.W BTL mode, RL=8Ω VDD=3.3V, Po=0.53W BTL mode, RL=8Ω VDD=.4V, Po=50mW BTL mode, RL=8Ω THDN (%) THDN vs. frequency THDN (%) THDN vs. frequency THDN (%) THDN vs. frequency VDD=5V, Po=90mW SE mode, RL=3Ω REV 4 THDN (%) THDN (%) THDN (%) Stereo inputs signal (Ta=5, stereo inputs signal, f=khz, DAC is Power Down mode; unless otherwise specified) VDD=3.3V, Po=35mW SE mode, RL=3Ω VDD=.4, Po=5mW SE mode, RL=3Ω THDN vs. frequency THDN vs. frequency THDN vs. frequency 8/8

9 f=0khz f=0khz f=0khz THDN (%) f=khz THDN (%) f=khz THDN (%) f=khz VDD=5V BTL mode RL=4Ω f=0hz VDD=3.3V BTL mode RL=4Ω f=0hz VDD=.4V BTL mode RL=4Ω f=0hz OUTPUT POWER (W) OUTPUT POWER (W) OUTPUT POWER (W) THDN vs. output power THDN vs. output power THDN vs. output power f=0khz f=0khz f=0khz THDN (%) f=khz THDN (%) f=khz f=0hz THDN (%) f=khz f=0hz f=0hz VDD=5V BTL mode RL=8Ω VDD=3.3V BTL mode RL=8Ω VDD=.4V BTL mode RL=8Ω OUTPUT POWER (W) OUTPUT POWER (W) OUTPUT POWER (W) THDN vs. output power THDN vs. output power THDN vs. output power f=0khz f=0khz f=0khz THDN (%) f=0hz f=khz THDN (%) f=0hz f=khz THDN (%) f=khz f=0hz VDD=5V SE mode RL=3Ω VDD=3.3V SE mode RL=3Ω VDD=.4V SE mode RL=3Ω OUTPUT POWER (W) OUTPUT POWER (W) OUTPUT POWER (W) THDN vs. output power THDN vs. output power THDN vs. output power REV 4 9/8

10 CHANNEL SEPARATION (db) VDD=5V, Po=W BTL, RL=8Ω CHANNEL SEPARATION (db) VDD=5V, Po=60mW SE, RL=3Ω Channel separation vs. frequency Channel separation vs. frequency CAP=0uF CAP=0uF CAP=uF CAP=uF PSRR (db) PSRR (db) VDD=5V, VRR=00mVrms, BTL RL=8Ω VDD=5V, VRR=00mVrms, SE RL=3Ω PSRR vs. frequency PSRR vs. frequency REV 4 0/8

11 DAC inputs signal (Ta=5, sampling rate=4fs, fs= 44.kHz, f=khz, PA is Power Down mode; unless otherwise specified) THDN (%) THDN (%) THDN (%) VDD=5V DAC VFS VDD=3.3V, VFS DAC VFS VDD=.4V, VFS DAC VFS THDN vs. frequency THDN vs. frequency THDN vs. frequency CAP=0uF CHANNEL SEPARATION (db) VDD=5V DAC VFS PSRR (db) CAP=uF VDD=5V VRR=0.Vrms SUPPLY VOLTAGE (V) Channel separation vs. supply voltage PSRR vs. frequency REV 4 /8

12 AUDIO TIMING AND FORMAT The accepts input serial data formats of 6-bit word length. Left and right data words are time multiplexed. The MSB must always be first. WS RIGHT LEFT t r t HB t f t LB t HW t SW BCK t cr t SD t HD DATA LSB MSB Audio data format (BCK, WS, DATA) Symbol Parameter Conditions Min Typ Max Unit VIL Input LOW level - - V VIH Input HIGH level V f BCK Input Clock Frequency MHz BR Bit Rate Data Input Mbits/s f WS Word Select Input khz t r Rise Time - - ns t f Fall Time - - ns t Cr Bit Clock Cycle Time ns t HB Bit Clock High Time ns t LB Bit Clock Low Time ns t SD Data Set-up Time - - ns t HD Data Hold Time to Bit Clock - - ns t HW Word Select Hold Time - - ns t SW Word Select Set-up Time - - ns REV 4 /8

13 Right justified format WS LEFT RIGHT BCK DATA MSB LSB MSB LSB Left justified format WS LEFT RIGHT BCK DATA MSB LSB MSB LSB MSB IS format WS LEFT RIGHT BCK BCK BCK DATA MSB LSB MSB LSB REV 4 3/8

14 I C BUS DESCRIPTION Start and Stop Conditions A start condition is activated when the SCL is set to HIGH and SDA shifts from HIGH to LOW state. The stop condition is activated when SCL is set to HIGH and SDA shifts from LOW to HIGH state. Please refer to the timing diagram below. SCL SDA Start Stop SCL : Serial Clock Line, SDA : Serial Data Line Data Validity A data on the SDA line is considered valid and stable only when the SCL signal is in HIGH state. The HIGH and LOW states of the SDA line can only change when the SCL signal is LOW. Please refer to the figure below. SDA SCL Data line stable, Data valid Data change allowed Byte Format Every byte transmitted to the SDA line consists of 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transmitted first. Acknowledge During the Acknowledge clock pulse, the master (up) put a resistive HIGH level on the SDA line. The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during the Acknowledge clock pulse so that the SDA line is in a stable LOW state during this clock pulse. Please refer to the diagram below. SCL SDA Start MSB Acknowledge The audio processor that has been addressed has to generate an Acknowledge after receiving each byte, otherwise, the SDA line will remain at the HIGH level during the ninth (9 th ) clock pulse. In this case, the master transmitter can generate the STOP information in order to abort the transfer. REV 4 4/8

15 Timing of SDA and SCL Bus Lines SDA SCL tf tlow tr tsu;dat tf thd;sta tsp tr tbuf S thd;sta thd;dat thigh tsu;sta Sr tsu;sto P S Standard Mode Symbol Parameter Min Max Unit f SCL SCL clock frequency 0 00 khz Hold time (repeated) START condition. t HD:STA us After this period, the first clock pulse is generated t LOW LOW period of the SCL clock us t HIGH HIGH period of the SCL clock us t SU:STA Set-up time for a repeated START condition us Data hold time: t HD:DAT For I C-bus devices us t SU:DAT Data-set-up time 50 - ns t r Rise time of both SDA and SCL signals ns t f Fall time of both SDA and SCL signals ns t SU:STO Set-up time for STOP condition us t BUF Bus free time between a STOP and START condition us C b Capacitive load for each bus line pf V nl V nh Noise margin at the LOW level for each connected device (including hysteresis) Noise margin at the HIGH level for each connected device (including hysteresis) 0.V DD - V 0.V DD - V REV 4 5/8

16 BUS INTERFACE Data are transmitted to and from the MCU to the via the SDA and SCL. The SDA and SCL make up the BUS interface. It should be noted that pull-up resistors must be connected to the positive supply voltage. V DD SDA (Serial Data Line) Rp Rp Pull up resistors SCL (Serial Clock Line) MCU I C interface protocol The format consists of the following: A START condition A chip address byte including the chip address. (7bits) The 8 th bit of the byte must be 0.(write=0, read=) The chip must always acknowledge the end of each transmitted byte. A data sequence (N-bytes Acknowledge) A STOP condition SDA SCL S START CONDITION ADDRESS R/ W ACK DATA ACK DATA ACK P STOP CONDITION I C chip address 88H bits address W REV 4 6/8

17 I C data bytes description MSB LSB Function 0 0 B B B0 A A A0 L-ch, Attenuation and Mute 0 B B B0 A A A0 R-ch, Attenuation and Mute 0 0 G G G0 S S0 L-ch, Input Gain and line Selection 0 G G G0 S S0 R-ch, Input Gain and line Selection DAC CAP 0 RPD LPD PDPR Power Down Mode PD PD Output mode (SE/BTL), Mixer control S/B MixL MixR AF AF0 and Audio format Where Ax =.5dB/step; Bx = 0dB/step; Gx = 3dB/step Attenuation and Mute MSB LSB Function 0 0 L-ch, Attenuation and Mute B B B0 A A A0 0 R-ch, Attenuation and Mute db db db db db db db db db db db 0-30 db db 0-50 db 0-60 db -70 db Mute Initial state: Both L-ch and R-ch are mute-on. REV 4 7/8

18 Input Selector and Input Gain MSB LSB Function 0 0 L-ch, Input Gain and line Selection G G G0 S S0 0 R-ch, Input Gain and line Selection 0 0 Line (L-ch or R-ch) 0 Line (L-ch or R-ch) 0 Line 3 (L-ch or R-ch) Line 4 (L-ch or R-ch) db db db 0 9 db 0 0 db 0 5 db 0 8 db db Initial state: L-ch, R-ch, Input gain is 0dB. Power Down Mode MSB LSB Function DAC CAP 0 RPD LPD PDPR Power mode selection and power management PD PD 0 DAC is active mode DAC is power down mode 0 R-ch PA output is active mode R-ch PA output is power down mode 0 L-ch PA output is active mode Initial state: All are the power down modes. Enable the power down preparation before the chip will be shut down. L-ch PA output is power down mode 0 Disable preparation for power off Enable preparation for power off 0 Set the voltage of CAP to middle of supply voltage Pull down CAP pin to ground REV 4 8/8

19 Output mode (SE/BTL), Mixer control and Audio format MSB LSB Function S/B MixL MixR AF AF0 Output mode, mixer control and audio format 0 Output mode is BTL Output mode is SE 0 L-ch of input selector is the only signal Mix L-ch of input selector and L-ch of DAC 0 R-ch of input selector is the only signal Mix R-ch of input selector and R-ch of DAC 0 0 Right justified format 0 Left justified format 0 I S format Initial state: Output mode is BTL mode, unmixed mode and Right justified format I C Initial code and status MSB LSB Function Initial status 0 0 L-ch, Attenuation and Mute Mute On 0 R-ch, Attenuation and Mute Mute On L-ch, Input Gain and line Selection Line, 0dB R-ch, Input Gain and line Selection Line, 0dB 0 Power Down Mode All devices power down Output mode (SE/BTL), Mixer control BTL, Unmixed, and Audio format Right justified REV 4 9/8

20 I C CODE EXAMPLE Input selector and input gain Set left channel to be line-4 and input gain to be 3dB. Set right channel to be line-4 and input gain to be 3dB. Gain Start Address ACK ACK Line ACK Stop L-ch = Line4, G = 3dB The left and right input channel are independent. R-ch = Line4, G = 3dB Volume control Set left channel to be -5dB and right channel to be 30dB. Gain Start Address ACK ACK Line ACK Stop L-ch = Line4, G = 3dB R-ch = Line4, G = 3dB Power down mode Set built-in DAC to be power down mode. DACPD Start Address ACK ACK Stop DAC power down Output mode, mixer control and audio format Set output mode to be SE mode, audio format is IS, and both input channel to be mixed. Output mode Mixer Audio format Start Address ACK 0 ACK Stop SE mode, All mix, IS REV 4 0/8

21 OPERATION PROCEDURE The sequence of operation: power on activating power down activating power off. The basic flowcharts are as follows: For HP mode and HP/BTL mode Power On Activating Power Down (Shut Down) Power Off All the Digital Interface Signals Pull Low IC pull low Audio inputs pull low (BCK, WS, DATA) V DD= GND Setting Input Gain Is Fixed [ Enable Input & Input Gain ] Code: Lch 00xxx00 Rch 0xxx00 Volume Down To Mute Input Channels Mute On [ Attenuation and Mute ] Code: Lch 00 (3Fh) Rch 0 (7Fh) Volume Down To Mute Input Channels Mute On [ Attenuation and Mute ] Code: Lch 00 (3Fh) Rch 0 (7Fh) Power On V DD= Supply voltage Default Status Disable Power Down [ Power Down Mode ] Code: (Ch) Wait 0.5sec PDPR = 0 Power Down Preparation [ Power Down Mode ] Code: (Ch) [ Input4 & Gain = 0dB] Code: Lch (83h) Rch 0000 (a3h) wait 7sec Power Down Preparation [ Power Down Mode ] Code: (Ch) [ Input4& Gain = 0dB] Code: Lch (83h) Rch 0000 (a3h) wait 7sec [Attenuation & Mute] Mute on (max attenuation) [ Input Selector & Input Gain ] L-ch, R-ch 0dB [ Power Down Mode ] All power down status [ Power Down Mode ] Code: (C0h) Wait 0.5 sec Mute Off And Volume Up/Down Step By Step Power Down All The Devices Only CAPPD Keep Activating [ Power Down Mode ] Code: 00 (DEh) Power Down All The Devices Pull Down CAP Pin To Ground [ Power Down Mode ] Code: 0 (DFh) [ Output Mode & Mixer & Format ] BTL mode Inputs not mixed with DAC signal RJF format [ Attenuation and Mute ] Code: Lch 00xxxxxx Rch 0xxxxxx Keep All The Digital Interface Signals Unchanged All the Digital Interface Signals Pull Low IC pull low Audio inputs pull low (BCK, WS, DATA) Power Off Disconnect V DD V DD will be fell down to 0V REV 4 /8

22 For BTL mode only Power On Activating Power Down (Shut Down) Power Off All the Digital Interface Signals Pull Low IC pull low Audio inputs pull low (BCK, WS, DATA) V DD= GND Setting Input Gain Is Fixed [ Input Gain ] Code: Lch 00xxx00 Rch 0xxx00 Volume Down To Mute Input Channels Mute On [ Attenuation and Mute ] Code: Lch 00 (3Fh) Rch 0 (7Fh) Volume Down To Mute Input Channels Mute On [ Attenuation and Mute ] Code: Lch 00 (3Fh) Rch 0 (7Fh) Power On V DD= Supply voltage Disable Power Down [ Power Down Mode ] Code: (C0h) Wait 0.5sec Pull Down CAP Pin To Ground [ Power Down Mode ] Code: (Ch) Wait 0.sec Pull Down CAP Pin To Ground [ Power Down Mode ] Code: (Ch) Wait 0.sec Default Status [Attenuation & Mute] Mute on (max attenuation) [ Input Selector & Input Gain ] L-ch, R-ch 0dB Mute Off And Volume Up/Down Step By Step [ Attenuation and Mute ] Code: Lch 00xxxxxx Rch 0xxxxxx Power Down All The Devices [ Power Down Mode ] Code: 0 (DFh) Power Down All The Devices [ Power Down Mode ] Code: 0 (DFh) [ Power Down Mode ] All power down status [ Output Mode & Mixer & Format ] BTL mode Inputs not mixed with DAC signal RJF format Keep All The Digital Interface Signals Unchanged All the Digital Interface Signals Pull Low IC pull low Audio inputs pull low (BCK, WS, DATA) Power Off Disconnect V DD V DD will be fell down to 0V REV 4 /8

23 APPLICATION INFORMATION A base application circuit MCU HP_sense VDD 00k 00k 0uF 0uF 0uF 0uF RIN RIN RIN3 RIN4 Attenuation & Mute Mixer off - OUTR- uf 00uF k 0uF 0uF 0uF 0uF LIN LIN LIN3 LIN4 Input selector & Gain control Attenuation & Mute Mixer off - - OUTR OUTL- R L 8Ω 00uF k Headphone Jack Audio Decoder BCK WS DATA 6-bit DAC - OUTL R L 8Ω Supply I C Interface Power Amplifier Supply VDD Vss CAP DACL DACR SCL SDA PV DDL PV SSL PV DDR PV SSR.4 ~ 6.5V Supply uf uf k k MCU uf uf.4 ~ 6.5V Power Amplifier Supply 0.uF 0nF 0nF REV 4 3/8

24 Output mode operation -- SE mode and BTL mode The output mode has two modes, SE mode and BTL mode. The mode is selected by IC code via a MCU. In BTL mode, the outputs of A(B) and A(B) are then used to drive the bridged-tied load - A - A OUTR R L 4Ω / 8Ω - B OUTR- OUTL- - B OUTL R L 4Ω / 8Ω I C Interface SCL SDA In the SE mode, the amplifiers A and B are shutdown, and then the amplifiers will be a high output impedance state. - A A OUTR- 00uF k Headphone Jack R L 6Ω / 3Ω Shutdown - - B OUTL- 00uF B k Shutdown - I C Interface SCL SDA Headphone sense The output mode is SE or BTL that is decided by a headphone. It has to be set SE mode when a headphone is plug-in status. The output mode is selected by IC command code by a MCU. Please note that the don t detect a headphone automatically. Thus a detect function is executed via a MCU. An operation diagram is as follows: The HP_sense pin is high when a headphone is plug-in. The HP_sense pin is low when a headphone is not plug-in. REV 4 4/8

25 EXTERNAL DIMENSIONS TSSOP8 (Thermal Pad) D D Detail A E EE C A A B e y A L L θ Symbol Dimension in mm Dimension in inches Min Nom Max Min Nom Max A A A b C D D E E E e L L θ 0 o - 8 o 0 o - 8 o y REV 4 5/8

26 DEMO BOARD Function description Label : Supply Input Supply voltage range is.4v to 6.5V. Label : Headphone Jack Used 3.5mm diameter of headphone with 3ohm Label 3: DAC output Connected to a post-power-amplifier, as active speaker. In addition, using volume control for DAC, this output can connected to input section (label 6) as feedback. Label 4: Speaker Output Connected to speaker with 8ohm or 4 ohm Label 5: Digital Signal Input Connected to digital audio formats as IS, Right Justified and Left Justified. Label 6: Signal Input There are four stereo inputs in the section. Please input stereo audio signal, as music or sine wave. Label 7: Reset All I/O pins are reset to default values. Label 8: LED Indicator The LEDs indicate the chip status and IR received status. It keeps on a light state when the is active. The other hand, keeps on a dark state when the is power-off. It is red-dark blink once when the MCU has received the function code correctly. REV 4 6/8

27 SE mode and BTL mode operation The headphone controls operational mode. System enters SE mode when headphone jack is empty. When a set of headphone plugged into the jack, the system switched to BTL mode. IR Controller Power ON/OFF : The power key. Press the key once to set power-on or power-off for. IN~IN4 : Analog input channel. Press the key once to select input channel. The default state is IN. VOL, VOL- : The volume control keys. The volume control in.5db/step as the switch is pressed once, the range is 77.5dB to 0dB. The default value is -0dB. Gain, Gain- : The gain control keys. The gain control in 3dB/step as the switch is pressed once, the range is 0dB to db. The initial value is 0dB. Mute : The mute key Press the key once to set mute-on or mute-off. The default state is mute-off. PD/Active : The power down key. Press the key once to set power-down or activation for. Mix_LR ON/OFF : The mixing DAC signal keys. Mix_L ON, mixed the left channel of DAC with the left channel of input signal. Mix_R OFF, unmixed the right channel of DAC with the right channel of input signal. IS, LJF, RJF: The digital input format keys. There are three formats can be selected that is IS, Left justified and Right justified. REV 4 7/8

28 REV 4 8/8 Circuit C3 0.u C3 0u C 0u C0 u C4 0u C4 u J AVCC SP SPK_R SP SPK_L DVDD WS BCK REF 3 R 4 R 5 R3 6 R4 7 Vss 8 PVDDR 9 -OUTR 0 OUTR GND PVSSR 3 DAC_R 4 DAC_L 5 PVSSL 6 GND 7 OUTL 8 -OUTL 9 PVDDL 0 VDD L4 L3 3 L 4 L 5 SDA 6 SCL 7 DATA 8 U C5 0u C4 0u R G 3 L J4 IN R G 3 L J5 IN R G 3 L J6 IN3 R G 3 L J8 IN4 C0 0u C6 0u C3 0u C 0u P3.7 RST P.0 P3.0 P. 3 P3. 3 P. 4 XTAL 4 P.3 5 XTAL 5 P.4 6 P3. 6 P.5 7 P3.3 7 P.6 8 P3.4 8 P.7 9 P3.5 9 Vcc 0 GND 0 U AT89C405 VS IR 3 GND Q IR C 47u C5 470P R 0 R 0K Y 4M C6 0P C7 0P R3 0K C 0u S RST DGND IR_IN DGND 3 4 J3 DAC_IN AGND IR_IN SCL SDA SCL SDA R5 R6 R7 J DVDD 3 J0 DAC_OUT C5 0u C8 0.u C9 u R G 3 L J DAC_OUT HP-IN HP-R R 3 HP-L 4 L 5 G 6 HEADPHONE C8 00u C9 00u R9 R8 3 J9 OUT R4 00K HP_IN C u C7 u C u 3 J3 LCD TX RX RX TX W Jumper DGND AGND R0 R R R3 R4 R5 R6 R7 D IN D3 IN3 D4 IN4 D IN R8 R9 R0 R W JUMP AVCC R 00K 3 Q NMOS AVCC