TDA7313D DIGITAL CONTROLLED STEREO AUDIO PROCESSOR WITH LOUDNESS

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1 TDA733 DIGITAL CONTROLLED STEREO AUDIO PROCESSOR WITH LOUDNESS INPUT MULTIPLEXER: - 3 STEREO INPUTS - SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTION TO DIFFERENT SOURCES INPUT AND OUTPUT FOR EXTERNAL EQUALIZER OR NOISE REDUCTION SYS- TEM LOUDNESS FUNCTION VOLUME CONTROL IN.25dB STEPS TREBLE AND BASS CONTROL FOUR SPEAKER ATTENUATORS: - 4 INDEPENDENT SPEAKERS CONTROL IN.25dB STEPS FOR BALANCE AND FADER FACILITIES - INDEPENDENT MUTE FUNCTION ALL FUNCTIONS PROGRAMMABLE VIA SE- RIAL I 2 C BUS DESCRIPTION The TDA733 is a volume, tone (bass and treble) balance (Left/Right) and fader (front/rear) processor for quality audio applications in car radio and Hi-Fi DIP28 SO28 ORDERING NUMBERS: TDA733 TDA733D systems. Selectable input gain and external loudness function are provided. Control is accomplished by serial I 2 C bus microprocessor interface. The AC signal setting is obtained by resistor networks andswitches combined with operationalamplifiers. Thanks to the used BIPOLAR/CMOS Tecnology, Low Distortion, Low Noise and Low DC stepping are obtained. PIN CONNECTION (Top view) November 999 /4

2 TDA733 TEST CIRCUIT THERMAL DATA Symbol Description SO28 DIP28 Unit R th j-pins Thermal Resistance Junction-pins max C/W ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit V S Operating Supply Voltage.2 V T amb Operating Ambient Temperature -4 to 85 C T stg Storage Temperature Range -55 to +5 C QUICK REFERENCE DATA Symbol Parameter Min. Typ. Max. Unit V S Supply Voltage 6 9 V V CL Max. input signal handling 2 Vrms THD Total Harmonic Distortion V = Vrms f = KHz.. % S/N Signal to Noise Ratio 6 db S C Channel Separation f = KHz 3 db Volume Control.25dB step db Bass and Treble Control 2db step db Fader and Balance Control.25dB step db Input Gain 3.75dB step.25 db Mute Attenuation db 2/4

3 TDA733 BLOCK DIAGRAM LEFT INPUTS RIGHT INPUTS C C2 C3 C4 C5 C6 3x 2.2µF 3x 2.2µF C9 2.2µF OUT(L) IN(L) C nf nf C4 LOUD(L) 5.6K R2 BOUT(L) nf C5 BIN(L) C7 2.7nF TREBLE(L) RB L 5 L L2 4 L2 L3 3 L3 VOL + LOUD BASS TREBLE INPUT SELECTOR + GAIN SERIAL BUS DECODER + LATCHES R3 9 R3 R2 R2 R R VOL + LOUD BASS TREBLE SUPPLY RB VCC AGND CREF OUT(R) IN(R) LOUD(R) BOUT(R) BIN(R) TREBLE(R) C7 22µF C8 2.2µF nf C2 nf C 5.6K R nf C3 2.7nF C6 SPKR ATT MUTE SPKR ATT MUTE SPKR ATT MUTE SPKR ATT MUTE D94AU OUT LEFT FRONT OUT LEFT REAR SCL SDA DIGGND OUT RIGHT FRONT OUT RIGHT REAR BUS 3/4

4 TDA733 ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25 C, VS = 9V, RL = KΩ, RG = 6Ω, all controls flat (G = ), f = KHz unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY V S Supply Voltage 6 9 V IS Supply Current 8 ma SVR Ripple Rejection 6 8 db INPUT SELECTORS R II Input Resistance Input, 2, KΩ V CL Clipping Level Vrms SIN Input Separation (2) 8 db R L Output Load resistance pin 7, 7 2 KΩ G INmin Min. Input Gain - db G INmax Max. Input Gain.25 db G STEP Step Resolution 3.75 db e IN Input Noise G =.25dB 2 µv V DC DC Steps adjacent gain steps 4 2 mv G = 8.75 to Mute 4 mv VOLUME CONTROL R IV Input Resistance kω C RANGE Control Range db A VMIN Min. Attenuation - db AVMAX Max. Attenuation db A STEP Step Resolution db E A Attenuation Set Error Av = to -2dB Av = -2 to -6dB E T Tracking Error 2 db V DC DC Steps adjacent attenuation steps From db to Av max SPEAKER ATTENUATORS C range Control Range db S STEP Step Resolution db E A Attenuation set error.5 db A MUTE Output Mute Attenuation 8 db VDC DC Steps adjacent att. steps from to mute BASS CONTROL () Gb Control Range Max. Boost/cut db B STEP Step Resolution 2 3 db RB Internal Feedback Resistance KΩ TREBLE CONTROL () Gt Control Range Max. Boost/cut db T STEP Step Resolution 2 3 db db db mv mv mv mv 4/4

5 TDA733 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit AUDIO OUTPUTS V OCL Clipping Level d =.3% Vrms R L Output Load Resistance 2 KΩ C L Output Load Capacitance nf R OUT Output resistance Ω V OUT DC Voltage Level V GENERAL e NO Output Noise BW = 2-2KHz, flat output muted all gains = db A curve all gains = db 3 µv S/N Signal to Noise Ratio all gains = db; VO = Vrms 6 db d Distortion A V =,V IN = Vrms A V = -2dB V IN = Vrms V IN =.3Vrms Sc Channel Separation left/right 8 3 db Total Tracking error A V = to -2dB -2 to -6 db 2 db db BUS INPUTS Notes: V IL Input Low Voltage V V IH Input High Voltage 3 V I IN Input Current µa V O Output Voltage SDA Acknowledge I O =.6mA.4 V () Bass and Treble response see attached diagram (fig.6). The center frequency and quality of the resonance behaviour can be choosen by the external circuitry. A standard first order bass response can be realized by a standard feedback network (2) The selected input is grounded thru the 2.2µF capacitor µv µv % % % Figure : Loudness vs. Volume Attenuation Figure 2: Loudnessvs. Frequency (CLOUD = nf) vs. Volume Attenuation 5/4

6 TDA733 Figure 3: Loudness vs. External Capacitors Figure 4: Noise vs. Volume/Gain Settings Figure 5: Signal to Noise Ratio vs. Volume Setting Figure 6: Distortion & Noise vs. Frequency Figure 7: Distortion & Noise vs. Frequency Figure 8: Distortion vs. Load Resistance 6/4

7 TDA733 Figure 9: Channel Separation (L R) vs. Frequency Figure : Input Separation (L L2, L3, L4) vs. Frequency Figure : Supply Voltage Rejection vs. Frequency Figure 2: Output Clipping Level vs. Supply Voltage Figure 3: Quiescent Current vs. Supply Voltage Figure 4: Supply Current vs. Temperature 7/4

8 TDA733 Figure 5: Bass Resistance vs. Temperature Figure 6: Typical Tone Response (with the ext. components indicated in the test circuit) I 2 C BUS INTERFACE Data transmission from microprocessor to the TDA733 and viceversa takes place thru the 2 wires I 2 C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown in fig. 7, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.8 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. Acknowledge The master (µp) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 9). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the µp can use a simplier transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity. Figure 7: Data Validity on the I 2 CBUS 8/4

9 TDA733 Figure 8: Timing Diagram of I 2 CBUS Figure 9: Acknowledge on the I 2 CBUS SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (s) A chip address byte, containing the TDA733 address (the 8th bit of the byte must be ). The TDA733 must always acknowledge at the end of each transmitted byte. A sequence of data (N-bytes + acknowledge) A stop condition (P) TDA733 ADDRESS MSB first byte LSB MSB LSB MSB LSB S ACK DATA ACK DATA ACK P ACK = Acknowledge S = Start P = Stop MAX CLOCK SPEED kbits/s Data Transferred (N-bytes + Acknowledge) SOFTWARE SPECIFICATION Chip address MSB LSB DATA BYTES MSB LSB FUNCTION B2 B B B B B G B B B B B G C3 C3 S2 C2 C2 Ax =.25dB steps; Bx = db steps; Cx = 2dB steps; Gx = 3.75dB steps A A A A A S C C A A A A A S C C Volume control Speaker ATT LR Speaker ATT RR Speaker ATT LF Speaker ATT RF Audio switch Bass control Treble control 9/4

10 TDA733 SOFTWARE SPECIFICATION (continued) DATA BYTES (detailed description) Volume MSB LSB FUNCTION B2 B B A A Volume.25dB steps B2 B B A A Volume db steps For example a volume of -45dB is given by: Speaker Attenuators MSB LSB FUNCTION B B B B B B B B For example attenuation of 25dB on speaker RF is given by: A A A A A A A A Speaker LF Speaker RF Speaker LR Speaker RR Mute /4

11 TDA733 Audio Switch MSB LSB FUNCTION G G S2 S S Audio Switch Stereo Stereo 2 Stereo 3 Stereo 4 (*) LOUDNESS ON LOUDNESS OFF +.25dB +7.5dB +3.75dB db For example to select the stereo 2 input with a gain of +7.5dB LOUDNESS ON the 8bit string is: (*) Stereo 4 is connected internally, but not available on pins. Bass and Treble C3 C3 C2 C2 C C C C Bass Treble C3 = Sign For example Bass at -db is obtained by the following 8 bit string: Purchase of I 2 C Components of STMicroelectronics, conveys a license under the Philips I 2 C Patent Rights to use these components in an I 2 C system, provided that the system conforms to the I 2 C Standard Specifications as defined by Philips. /4

12 TDA733 DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. OUTLINE AND MECHANICAL DATA A a b b C.5.2 c 45 (typ.) D E e.27.5 e F L S 8 (max.) SO28 2/4

13 TDA733 DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. OUTLINE AND MECHANICAL DATA a b.45.8 b b D E e e F I L DIP28 3/4

14 TDA733 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registeredtrademark of STMicroelectronics 999 STMicroelectronics Printed in Italy All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. 4/4

Obsolete Product(s) - Obsolete Product(s)

Obsolete Product(s) - Obsolete Product(s) TDA73 SERIAL BUS CONTROLLED AUDIO PROCESSOR INPUT MULTIPLEXER: - 4 STEREO INPUTS - ONE DIFFERENTIAL STEREO INPUT FOR REMOTE SOURCES SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTION TO DIFFERENT SOURCES INPUT