AP Channel Audio Processor

Transcription

1 \ AP2600 AP2600

2 Table of Contents. OVERVIEW APPLICATIONS ORDERING INFORMATION FEATURES BLOCK DIAGRAM PIN CONFIGURATION DEVICE PIN OUT AND PIN DESCRIPTIONS APPLICATION CIRCUIT ABSOLUTE MAXIMUM RATING (T a = 25 o C) ELECTRICAL CHARACTERISTICS...4. EQUALIZER DESCRIPTION I 2 C-BUS CONCEPTS I 2 C-BUS FORMAT DATA BYTE FUNCTION & POWER ON RESET CONDITION SOFTWARE SPECIFICATION PACKAGE INFORMATION...4

3 . OVERVIEW The AP2600 is a four-channel input audio processor with input multiplexer, input volume attenuator, equalizer and loudness features. It can effectively suppress noise with very few external components. AP2600 s built-in zero-cross function can effectively prevent click noise. This chip is controlled by serial data I 2 C bus which makes the chip user-friendly by simple command. 2. APPLICATIONS Boombox Mini Stereo System MP3 Docking Speaker System Discman Portable Audio System 3. ORDERING INFORMATION PART NUMBER PINS PACKAGE AP2600-CB-L 28 COB AP2600-SO-L 28 SOP 4. FEATURES 4 stereo input selectors Input volume attenuator (64 steps): master control in.25db steps Two output speaker attenuators (32 steps): balance controls in.25db steps Loudness function on/off Treble and Bass control in 2dB step (5 steps) Few external components Built-in zero-cross detector prevents click noise No DC level shift Gain control in 3.75dB step (4 steps) Separate outputs: line out, speaker out Built-in power-up reset Controlled by serial data I 2 C bus Separate ground for analog and digital circuits 2.7V to 5.5V single supply operation 5. BLOCK DIAGRAM LOUDL TREL BOUTL BINL LMAXO LVOLI CHL CH2L CH3L CH4L CHR CH2R CH3R CH4R GAIN L SPR ATT 4 TREBLE BASS 3 LEFT MULTIPLEXER + VOLUME + LOUDNESS SUPPLY R TREBLE I 2 C BUS DECODER + LATCHES BASS GAIN + SPR ATT RIGHT LOUT SCL SDA GND ROUT RVOLI RMAXO BOUTR BINR TRER VREF VSA VDA LOUDR Revision. Page of 6 February 28, 2006

4 6. PIN CONFIGURATION VDA 28 VREF VDA 28 VREF VSA 2 27 SCL VSA 2 27 SCL TREL 3 26 SDA TREL 3 26 SDA TRER 4 25 GND TRER 4 25 GND RVOLI 5 24 LOUT RVOLI 5 24 LOUT RMAXO LOUDR CH4R AP2600 COB ROUT BOUTR BINR RMAXO LOUDR CH4R AP2600 SOP ROUT BOUTR BINR CH3R 9 20 BOUTL CH3R 9 20 BOUTL CH2R 0 9 BINL CH2R 0 9 BINL CHR 8 LMAXO CHR 8 LMAXO LOUDL 2 7 LVOLI LOUDL 2 7 LVOLI CH4L 3 6 CHL CH4L 3 6 CHL CH3L 4 5 CH2L CH3L 4 5 CH2L 7. DEVICE PIN OUT AND PIN DESCRIPTIONS PIN NUMBER PIN NAME DESCRIPTIONS VDA Power Supply Voltage Input 2 VSA Analog Ground 3 TREL Left Channel Treble Band 4 TRER Right Channel Treble Band 5 RVOLI Right Channel Volume Control Input 6 RMAXO Right Channel Maximum Output 7 LOUDR Right Channel Loudness 8 CH4R Right Channel Audio Input for Stereo Input Channel 4 9 CH3R Right Channel Audio Input for Stereo Input Channel 3 0 CH2R Right Channel Audio Input for Stereo Input Channel 2 CHR Right Channel Audio Input for Stereo Input Channel 2 LOUDL Left Channel Loudness 3 CH4L Left Channel Audio Input for Stereo Input Channel 4 4 CH3L Left Channel Audio Input for Stereo Input Channel 3 5 CH2L Left Channel Audio Input for Stereo Input Channel 2 6 CHL Left Channel Audio Input for Stereo Input Channel 7 LVOLI Left Channel Volume Control Input 8 LMAXO Left Channel Maximum Output 9 BINL Bass Band Left Channel Input 20 BOUTL Bass Band Left Channel Output 2 BINR Bass Band Right Channel Input 22 BOUTR Bass Band Right Channel Output 23 ROUT Right Channel Audio Output for Speaker Use 24 LOUT Left Channel Audio Output for Speaker Use 25 GND Digital Ground 26 SDA Serial Data Line 27 SCL Serial Clock Line 28 VREF Reference Voltage Input Revision. Page 2 of 6 February 28, 2006

5 8. APPLICATION CIRCUIT I2C BUS R 5.6K R2 5.6K C26 C23 C C22 C6 C7 0.U C7 0.U C8 0.U 0.U C8 C C C5 C9 C25 0.U C24 2.7N C6 2.7N C20 C5 C4 C3 C2 C4 C3 470K 470K VDA VSA TREL TRER RVOLI RMAXO LOUDR CH4R CH3R CH2R CHR LOUDL CH4L CH3L VREF SCL SDA GND LOUT ROUT BOUTR BINR BOUTL BINL LMAXO LVOLI CHL CH2L ASP AP2600 AP R3 C0 R4 C2 0.U 0.U Application Notes Application circuit above can be applied to both COB and SOP Tolerance of all resistors = % Tolerance of capacitors = 5% Line out signal can be obtained through pin 6, 8 Speaker out signal can be obtained through pin 23, ABSOLUTE MAXIMUM RATING (T a = 25 o C) [Under no circumstances should the absolute maximum ratings given below be violated. Stresses exceeding one or more of the limiting values may cause permanent damage to the device.] PARAMETER SYMBOL VALUE UNIT Supply Voltage V cc 6 V Power Dissipation P d 50 mw Operating Temperature Range T opr -20 to 70 Storage Temperature Range T stg -20 to 00 o C o C Revision. Page 3 of 6 February 28, 2006

6 0. ELECTRICAL CHARACTERISTICS [Refer to the application circuit V CC =3.3V, T a =25 o C, f=khz, all controls flat unless otherwise specified] SUPPLY PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT Supply Voltage V cc V Supply Current I d ma Supply Rejection SVR db GENERAL Output Noise N out All flat, f=20 to 20kHz All max, f=20 to 20kHz Channel Separation S C All flat, f=k db Total Normalized Volume Set Error G a G = 0 through 50dB db Total Tracking Error (ch. L ch. R) G t db Total Harmonic Distortion + Noise Maximum Input Voltage THD+N V IM All flat All max All flat, THD=3% All max, THD=3% Internal Reference Voltage V ref V cc - V INPUT MASTER VOLUME Input Resistance R in At pins 9-, kω Control Range C range db Maximum Attenuation A max db Step Resolution A step.25.5 db Normalized Attenuation Set Error G a G = 0 through 50dB db Tracking Error (ch. L ch. R) G t G = 0 through 78.75dB db OUTPUT BALANCE AND VOLUME CONTROL Control Range C range db Maximum Attenuation A max db Step Resolution A step.25.5 db Normalized Attenuation Set Error G a G = 0 through 37.5dB db Tracking Error (ch. L ch. R) G t G = 0 through 37.5dB db Mute Attenuation A mute f=k db OUTPUT GAIN CONTROL Maximum Output Gain G maxo db Minimum Output Gain G mino db Step Resolution A step db dbv % V rms Revision. Page 4 of 6 February 28, 2006

7 ELECTRICAL CHARACTERISTICS (continued) AP2600 [Refer to the application circuit V CC =3.3V, T a =25 o C, V in = -20dBV (0.V rms ), f=khz unless otherwise specified] BASS PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT Control Range C range f=00hz ±3 ±4 ±5 db Step Resolution A step db Attenuation Set Error G a G = -4 through 4dB - - db Tracking Error (ch. L ch. R) G t G = -4 through 4dB db TREBLE Control Range C range f=20khz ±3 ±4 ±5 db Step Resolution A step db Attenuation Set Error G a G = -4 through 4dB - - db Tracking Error (ch. L ch. R) G t G = -4 through 4dB db AUDIO OUTPUT Maximum Output Voltage V om THD=3% at pin 6,8,23,24 - V cc - V Output DC Voltage Level V dc At pin 6,8,23, V cc - V Output Resistance R out At pin 6,8,23, Ω POWER-ON RESET Start of Reset V rst V cc - V DIGITAL CIRCUIT (I 2 C-BUS) Input High Voltage for Pin 27 V IH 0.7 V cc - - V Input Low Voltage for Pin 27 V IL V cc V Input Threshold Voltage for Pin 26 V TH V cc - V Output-Low Current for Pin 26 I OL ma Revision. Page 5 of 6 February 28, 2006

8 ELECTRICAL CHARACTERISTICS (continued) AP2600 [Refer to the application circuit V CC =3.3V, T a =25 o C, V in = -20dBV (0.V rms ), f=khz unless otherwise specified] MAXIMUM INPUT VOLTAGE (THD=3%) 5 V IM - MAXIMUM INPUT VOLTAGE (V) f = khz 4 3 All flat 2 All maximum V CC - SUPPLY VOLTAGE (V) FREQUENCY RESPONSE (Loudness) Loudness on In vol. 0 to -50dB FREQUENCY RESPONSE (Treble) Vin = -20dBV Lch Vout = Lch FREQUENCY RESPONSE (Bass) Vin = -20dBV Lch Vout = Lch Revision. Page 6 of 6 February 28, 2006

9 . EQUALIZER DESCRIPTION In AP2600, there is a two-band digitally controlled stereo equalizer. The circuit structures of the Bass band and Treble band are similar. They are connected in a serial format. Each band can be considered as a filtering cell which can boost or cut the signal at certain frequency range. Bass Band Control Circuit A. Boost mode IN OUT f O = (Hz) 2 π R(R2 + R3)(C)(C2) R3 R2 Q C+ C2 (C)(C2)(R2) R C R C2 G V R2 + R3 + 2 R = 20log R3 + 2 R (db) B. Cut mode IN OUT f O = (Hz) 2 π R(R2 + R3)(C)(C2) R2 R3 Q C+ C2 (C)(C2)(R2) R C2 R C G V R3 + 2 = 20log R R2 + R3 + 2 R (db) Under both boost and cut mode, their center frequency (f o ), Q-factor (Q) and maximum gain (G v ) can be controlled by the external components (C, C2, R). Corresponding instance names in application circuit are shown below: LEFT CHANNEL RIGHT CHANNEL INSTANCE NAME IN STRUCTURE C C2 R C C2 R INSTANCE NAME IN APPLICATION CIRCUIT C8 C7 R4 C7 C6 R Revision. Page 7 of 6 February 28, 2006

10 Treble Band Control Circuit A. Boost mode IN OUT f O = (Hz) 2π(R)(C) R R2 R+R2 = 20log R G V (db) C B. Cut mode IN R2 OUT f O = (Hz) 2π(R)(C) R C R = 20log R+R2 G V (db) Under both boost and cut mode, their cut-off frequency (f o ) can be controlled by the external component (C). Corresponding instance names in application circuit are shown below: LEFT CHANNEL RIGHT CHANNEL INSTANCE NAME IN STRUCTURE C C INSTANCE NAME IN APPLICATION CIRCUIT C5 C6 Revision. Page 8 of 6 February 28, 2006

11 2. I 2 C-BUS CONCEPTS I 2 C-bus is a simple bi-directional, 2-wire serial data (SDA) and serial clock (SCL) bus for inter-ic control. Both lines must be connected to a positive supply via a pull-up resistor when connected to output of device. Data Validity One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse. Changes in the data line at this time will be interpreted as control signals. SDA SCL SDA stable data valid change of data allowed Data Transfer Start and Stop Conditions Both data and clock remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data, while the clock is HIGH, is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P). Device Address After the Start condition, the address of a Slave device is sent. This address is 7 bits long followed by an 8 th -bit, which is a data direction bit (R/W): 0 indicates a transmission (Write), indicates a request for data (Read). Acknowledge There is no limit to the number of data byte transferred between the start and stop conditions from transmitter to receiver. Each byte of 8 bits is followed by an acknowledge bit (ACK). A slave receiver must generate an ACK after the reception of each byte. Also a master must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. Device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the ACK related clock pulse, set-up and hold times must be taken into consideration. A master receiver must signal an end of data to the transmitter by not generating an ACK on the last byte that has been clocked out of the slave. In this case, the transmitter must release the data line HIGH to allow the master to generate a stop condition. SDA SDA SCL S P SCL START condition STOP condition Definition of START and STOP condition DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER SCL FROM MASTER acknowledge START condition clock pulse for acknowledge Acknowledgement on I 2 C-bus Revision. Page 9 of 6 February 28, 2006

12 *NAK SDA MSB ~ ~ LSB MSB ~ ~ LSB *ACK ~ ~ SCL Start Condition Slave Address R/W ACK DATA ACK Stop Condition * NAK SDA line is HIGH **ACK SDA line is pulled LOW by receiver Overall Diagram 3. I 2 C-BUS FORMAT The interface protocol comprises: A start condition (S) A chip address byte A sequence of data + acknowledge (A) A stop condition (P) CHIP ADDRESS DATA to DATA n MSB LSB MSB LSB S A DATA A P The byte order and the number of bytes sent are arbitrary. The sequence of data is terminated by the stop condition. 4. DATA BYTE FUNCTION & POWER ON RESET CONDITION MSB DATA BYTE LSB D7 D6 D5 D4 D3 D2 D D0 FUNCTION POWER ON RESET CONDITION MODE STATUS BIT STATUS 0 0 X X X X X X Input Volume 0dB D5:D X X X X X Left Output Attenuation 0dB D4:D X X X X X Right Output Attenuation 0dB D4:D X X X X X Output Gain Loudness Input Sources Selection 0dB OFF CH D4:D3 D2 D:D0 0 0 X X X X EQ Bass Level -4dB D3:D X X X X EQ Treble Level -4dB D3:D Revision. Page 0 of 6 February 28, 2006

13 5. SOFTWARE SPECIFICATION INPUT MASTER VOLUME SELECTION D5:D3 input volume 0dB attenuation D2:D0 input volume.25db attenuation MSB LSB INPUT VOLUME D7 D6 D5 D4 D3 D2 D D0.25dB STEPS dB dB dB dB 0 0-5dB dB 0-7.5dB -8.75dB 0dB STEPS dB 0 0-0dB dB 0-30dB dB 0-50dB 0-60dB -70dB LEFT OUTPUT SPEAKER ATTENUATE SELECTION D4:D3 left output speaker 0dB attenuation D2:D0 left output speaker.25db attenuation MSB LSB LEFT OUTPUT SPEAKER ATTENUATION D7 D6 D5 D4 D3 D2 D D0.25dB STEPS dB dB dB dB 0 0-5dB dB 0-7.5dB -8.75dB 0dB STEPS dB 0-0dB 0-20dB -30dB MUTE Revision. Page of 6 February 28, 2006

14 RIGHT OUTPUT SPEAKER ATTENUATE SELECTION D4:D3 right output speaker 0dB attenuation D2:D0 right input speaker.25db attenuation MSB LSB RIGHT OUTPUT SPEAKER ATTENUATION D7 D6 D5 D4 D3 D2 D D0.25dB STEPS dB dB dB dB 0 0-5dB dB 0-7.5dB -8.75dB 0dB STEPS 0 0 0dB 0-0dB 0-20dB -30dB MUTE SOURCES SELECTION / LOUDNESS / OUTPUT GAIN SELECTION D4:D3 output gain selection D2 loudness ON/OFF D:D0 input sources selection MSB LSB D7 D6 D5 D4 D3 D2 D D0 INPUT SOURCES SELECTION LOUDNESS OUTPUT GAIN SELECTION CH 0 CH2 0 CH3 CH4 0 Loudness ON Loudness OFF 0 0 Output Gain +.25dB 0 Output Gain +7.5dB 0 Output Gain +3.75dB No Gain Revision. Page 2 of 6 February 28, 2006

15 BASS LEVEL SELECTION D3:D0 bass level selection MSB LSB D7 D6 D5 D4 D3 D2 D D0 BASS LEVEL dB dB dB 0 0-8dB dB 0 0-4dB 0 0-2dB 0 0dB 0dB 0 2dB 0 4dB 0 0 6dB 0 8dB 0 0 0dB 0 0 2dB dB TREBLE LEVEL SELECTION D3:D0 treble level selection MSB LSB D7 D6 D5 D4 D3 D2 D D0 TREBLE LEVEL dB dB dB 0 0-8dB dB 0 0-4dB 0 0-2dB 0 0dB 0dB 0 2dB 0 4dB 0 0 6dB 0 8dB 0 0 0dB 0 0 2dB dB Revision. Page 3 of 6 February 28, 2006

16 6. PACKAGE INFORMATION PIN LOCATION COB PACKAGE Revision. Page 4 of 6 February 28, 2006

17 PACKAGE INFORMATION SOP28 PACKAGE Revision. Page 5 of 6 February 28, 2006

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