FEATURES DESCRIPTION APPLICATIONS BLOCK DIAGRAM. PT W x 2, Class-D Audio Power Amplifier

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1 PT83 x, Class-D Audio Power Amplifier DESCRIPTION The PT83 is a Class-D power amplifier designs for audio system; the maximum output power could up to x. It is housing in a small, thermal enhanced package, the best benefits of the PT83 are high efficiency and less external components. Fabricated by high voltage BCD process to improve ESD and electro stress handling capabilities. APPLICATIONS Sound Bar Mini Audio System Docking Speaker System Consumer Audio Applications FEATURES Supports Multiple Output Configurations (THD=) --- x into a 8Ω BTL at 9V --- x into a 8Ω BTL at V --- x into a 8Ω BTL at V 4Ω minimum load Single power supply reduces component count (Built-in V regulator) Master/Slave Synchronization 4 voltage gains setting Power ON de-pop enable Integrated Self-Protection Circuits including Under / Over supply voltage, short circuit and over temperature protection Stereo and Mono mode with Single Filter Mono configuration ide Voltage Range: 4.V~6V Small size 8 Pins HT-SSOP package with thermal pad BLOCK DIAGRAM BYPASS VDDP SVCC HVSS Regulator HVSS Regulator SGND SVC C PVCC VCMfb Driver-H CVCM PM Logic Level Shift HVS S VDDP OUTN Driver-L INN PGND INP PVCC GAIN0 GAIN Gain Adj PM Logic Level Shift Driver-H HVS S VDDP OUTP SYNCLK Driver-L ROSC OSC PGND OE Protection & Function *Shows the block diagram of one of the two identical channels STBY MUTE Tel: Fax: F, No. 47, Lane, Sec., Guangfu Rd., Hsinchu City 3007, Taiwan

2 PT83 APPLICATION CIRCUIT DIAGRAM C8 SVCC BYPASS 8 C C HVSS INNB 7 C 3 SUB_GND INPB 6 C L 4 OUTPB GAIN VCC GND C3 C7 C8 C L L3 R3 C3 C PGNDB PVCCB OUTNB OUTNA PT83 GAIN0 CVCM OE SGND 4 3 C7 C4 C C9 C6 R4 C4 C 9 PVCCA PGNDA 0 SYNCLK 9 C0 L4 OUTPA ROSC 8 C PGND INNA 7 R C4 SVCC R R6 C9 C 3 4 VDDP STBY INPA MUTE 6 C6 C3 R SVCC LC Filter components R_load L, L, L3, L4 C, C6 4Ω uh 470nF 6Ω uh 0nF 8Ω 33uH 0nF PARTS RECOMMENDATION Capacitor Resistor C, C, C3, C uF R---39KΩ C, C, C, C, C7~C---0.uF R, R6---33KΩ C6, C8, C ---.uf R3, R4, R---Ω C7, C9,---uF C3, C pF C3---00uF C---0.uF C4 4.7uF For better THD+N performance the X7R material SMD capacitor is recommended. V. August 0

3 PT83 ORDER INFORMATION Part Number Package Type Top Code PT83-HT 8 pins, HTSSOP, 73mil PT83-HT PIN CONFIGURATION SVCC BYPASS 8 HVSS INNB 7 3 SUB_GND INPB 6 4 OUTPB GAIN PGNDB GAIN0 4 6 PVCCB CVCM OUTNB OUTNA PT83 OE SGND 9 PVCCA 0 PGNDA SYNCLK 9 OUTPA ROSC 8 PGND INNA 7 3 VDDP INPA 6 4 STBY MUTE V. 3 August 0

4 PIN DESCRIPTION Pin Name I/O Description Pin No. SVCC Power Signal power supply HVSS O Regulator output referred to power supply SUB_GND Power Connect to the frame 3 OUTPB O Positive PM for right channel 4 PGNDB Power Power stage ground for right channel PVCCB Power Power supply for right channel 6 OUTNB O Negative PM output for right channel 7 OUTNA O Negative PM output for left channel 8 PVCCA Power Power supply for left channel 9 PGNDA Power Power stage ground for left channel OUTPA O Positive PM for left channel PGND Power Power stage ground VDDP O Regulator output referred to ground for power stage 3 STBY I Standby mode control 4 MUTE I Mute mode control INPA I Positive differential input of left channel 6 INNA I Negative differential input of left channel 7 ROSC O Master Oscillator frequency-setting pin 8 SYNCLK I/O Clock in/out for external oscillator 9 O Regulator output referred to ground for power stage 0 SGND Power Signal ground OE O Open-drain diagnostic output CVCM O Supply voltage rejection 3 GAIN0 I Gain setting input 4 GAIN I Gain setting input INPB I Positive differential input of right channel 6 INNB I Negative differential input of right channel 7 BYPASS O Half referred to ground 8 PT83 V. 4 August 0

5 PT83 FUNCTIONAL DESCRIPTION POER REQUIREMENT Operating voltage range of the PT83 is from 4.V to 6V, all of PVDD pins should add bypass cap to absorb ripples and noises, using a 0.μF+μF capacitors for bypassing is recommended. The power supply monitor (UV/OV) block will always monitor the supply voltage. It have window limits; one for the under voltage (UV) and another one for over voltage (OV), refer to electric spec for detail specifications. hen supply voltage variation exceeds the window, the amplifier will be muted to eliminate pop-noise. Built-in V regulator provides a clean, filtered DC power source to the analog and control logic circuitry to improve PSRR. The STBY pin is use to cut-off current consumption of whole chip. Total supply current will drop under 0uA typically when shutdown is active even PVDD is still powered. CLASS-D GAIN SETTING The gain of the PT83 is set by the two inputs, GAIN0 (pin 4) and GAIN (pin ). Internally, the gain is set by changing the feedback resistors of the amplifier. Class-D Amp Gain CLASS-D GAIN GAIN GAIN0 0dB 0 0 6dB 0 30dB 0 3dB V. August 0

6 PT83 INTERNAL AND EXTERNAL CLOCKS The clock of the class-d amplifier can be generated internally or can be driven by an external source. If two or more class-d amplifiers are used in the same system, it is recommended that all devices operate at the same clock frequency. This can be implemented by using one PT83 as master clock, while the other devices are in slave mode (that is, externally clocked). The clock interconnect is via pin SYNCLK of each device. As explained below, SYNCLK is an output in master mode and an input in slave mode. MASTER MODE (INTERNAL CLOCK) Using the internal oscillator, the output switching frequency, fs, is controlled by the resistor, ROSC, connected to pin ROSC. In master mode, pin SYNCLK is used as a clock output pin, whose frequency is: fsynclk = * fs For master mode to operate correctly then resistor ROSC must be less than 60kΩ. SLAVE MODE (EXTERNAL CLOCK) In order to accept an external clock input the pin ROSC must be left open, that is, floating. This force pin SYNCLK to be internally configured. The output switching frequency of the slave devices is: fs = fsynclk / Mode ROSC SYNCLK Master ROSC < 60KΩ Output Slave Floating (no connect) Input Master Slave PT83 PT83 ROSC SYNCLK ROSC SYNCLK Output Input V. 6 August 0

7 PT83 MODE SELECTION STANDBY MODE All of circuits are turned off, very low current consumption. MUTE MODE: Pull Mute pin to GND, the class-d output PM waveform will stay on 0 duty cycle but the output audio signal was muted. NORMAL MODE: The amplifiers are active. The OE has internally pull up resistance to V supply, in general condition connect a cap on OE pin could help delay the turn on time to prevent pop noise. PROTECTION MODE: During power-on period---oe stay Logic Low, OV/UV, OC, & OT, there would be no output. Mode STBY Mute OE Standby L X X Mute H L X Mute X X L Normal H H H* *Drive level defined in Electrical specifications POER-ON SEQUENCE FOR MINIMIZING SPEAKER POP SVCC STBY OE To mute BYPASS OE.V If external mute 0.uF INPUT OUTPUT Hardware mute configuration Power-on & Mute timing V. 7 August 0

8 PT83 MONO MODE (PBTL) The PT83 family can be connected in MONO mode enabling up to 8 output power. This is done by: Connect INPB and INNB directly to Ground (without capacitors) this sets the device in Mono mode during power up. Connect OUTPA and OUTNA together for the positive speaker terminal and OUTNB and OUTPB together for the negative terminal Analog input signal is applied to INPA and INNA CHA PT83 OUTPA OUTNA PSU 4.V~6V LC Filter CHB PBTL Detect OUTPB OUTNB PROTECTION FUNCTION The PT83 is fully protected against over-voltage, under-voltage, over-current and thermal overload. OVER-VOLTAGE PROTECTION (OVP) If the supply voltage exceeds the value for VOVP, the over-voltage protection is activated which forces the outputs to the high-impedance state. hen the supply voltage drops to below the threshold value the device restarts. UNDER-VOLTAGE PROTECTION (UVP) If the supply voltage drops below the value for VUVP, the under-voltage protection is activated which forces the outputs to the high-impedance state. hen the supply voltage recovers the device restarts. OVER-CURRENT PROTECTION (OCP) If the output current exceeds the value for IOCP, the over-current protection is activated which forces the outputs to the high-impedance state. Periodically, the device attempts to restart. If the over-current condition is still present then the OCP remains active. The restart time, TOC, is determined by the Capacitor components connected to pin OE. THERMAL PROTECTION (OTP) If the junction temperature, Tj, reaches 4 C (nominal), the device goes to mute mode and the positive and negative PM outputs are forced to 0 duty cycle. If the junction temperature reaches the value for Tj, the device shuts down and the output is forced to the high impedance state. hen the device cools sufficiently the device restarts. V. 8 August 0

9 PT83 PCB LAYOUT The heat dissipation of the PT83 is summed up by the following factors: supply voltage, load Impedance, and type of input signal. Because of the amplitude and frequency of the audio signals is not a fixed value during general music broadcasts; thus, the accumulated heat will be less than a continuous sine wave power output. In brief, because the amplitude and frequency of audio signals varies, the average power output is lower than that of a fixed continuous sine wave. Thus, the heat caused by a normal sine wave will accumulate faster because of a higher average power output. Sometimes when testing continuously may activate the overheat protection. The activation of the overheat protection depends on the heat dissipation condition. The larger copper foil area on the PCB, the better heat is dissipated. Please refer to the list below when designing the PCB layout.. Large (00μF or greater) bulk power supply decoupling capacitors should be placed near the PT83 on the PVCC supplies. The high-frequency bypass capacitors (0.uF) should be placed as close to the PVCCA/PVCCB pins as possible. These caps can be connected to the IC GND pad directly for an excellent ground connection.. Keep the current loop from each of the outputs through the inductor and the small filter cap and back to GND as small and tight as possible. The size of this current loop determines its effectiveness as an antenna. 3. The copper foil on the PCB must have at least.oz thickness. 4. The PCB should layers board is recommended.. PCB must have enough via holes below the thermal pad; it is recommended to have 8 holes, the holes diameter is 0.mm. 6. The copper foil connected with thermal pad should be connected to ground plate and do not connected to any others Voltage LEVEL. The copper foil must be plated in broad and continuously and do not cut off from the midway as possible. V. 9 August 0

10 ABSOLUTE MAXIMUM RATING PT83 Characteristic MIN MAX Unit Supply voltage, PVCC 0 8 V Operating Temperature, Top C Storage Temperature, Tstg C Junction Temperature, Tj C ESD All Pins HBM - + KV MM V Maximum Input Voltage, Vi max LV group V HV group -0.3 PVCC+0.3 V ELECTRICAL CHARACTERISTIC Unless Stated Otherwise, PVCC(A/B)=V, RL(load) =8Ω, ROSC=39KΩ, COSC=0nF, f=khz, GV=0dB, Tamb= C, TEST BANDIDTH= ~ KHZ Symbol Parameter Test Conditions Min Typ Max Unit General PVCC Supply Voltage V ICC Supply Current No input, exclude filter ma STBY=0.8V µa VOS Output offset voltage Play mode -0-0 mv VOS Output offset voltage Mute mode -0-0 mv IOCP(BTL) Over-current RL = 0 Ω, protection threshold OUTPA, NA, OUTPB, NB A IOCP(PBTL) Over-current RL = 0 Ω, protection threshold OUTPA, NA, OUTPB, NB A OTP Junction Temperature at Over-temperature thermal, Output Off protection threshold Output On OVP Over Voltage Protection V UVP Under Voltage Protection V VIH Digital Input High Gain0, Gain, MUTE, STBY V VIL Digital Input Low Gain0, Gain, MUTE, STBY V Class-D Amplifier Rin Input Resistance IN+ and IN- KΩ Fosc Switch Frequency Range PVDD=V KHz Fsw Switch Frequency Internal oscillator, master mode KHz Rsw Switch Resistance N + PMOS, Tj= mω THD+N Total Harmonic Distortion Po=, RL=8Ω GAIN=0, GAIN0=0 8 0 Gv Closed loop gain GAIN=, GAIN0= GAIN=0, GAIN0= db GAIN=, GAIN0= Gmatch Gain matching OUTA and OUTB - - db CT Cross Talk F=KHz, Po= db V. August 0

11 PT83 Symbol Parameter Test Conditions Min Typ Max Unit VCC=V, THD=, RL=8Ω VCC=V, THD=, RL=8Ω - - VCC=V,THD=, RL=8Ω - - VCC=V,THD=, RL=8Ω Pomax Vno Maximum Output Power Output Noise VCC=V, THD=, RL=4Ω VCC=V, THD=, RL=4Ω VCC=V,THD=, RL=4Ω VCC=V,THD=, RL=4Ω - - A-weighted, Gain=0dB 0~KHz μv dbv μv dbv SNR Signal to noise ratio THD+N<, A-weighted - - db AMUTE Mute Attenuation 0dB@Po= db PD Power Dissipated Po=+, THD=, PVCC=V η Efficiency Po=+, PVCC=V PSRR Power Supply Rejection Ratio Fr=0Hz, Vr=Vpp, Csvr=uF db Tr, Tf Rise and fall times Ns RL(BTL) Minimum load Ω RL(PBTL) Impedance Ω V. August 0

12 Output Power () Efficiency () PT83 Test Condition: PVCC=~V, RL=8Ω, F=KHz, Gain=0dB, T= C Output Power vs PVCC Efficiency THD= THD= PVCC (V) 9V V V Output Power Per Channel () THD vs Output Power - PVCC=V THD vs Output Power - PVCC=9V m 00m 00m 0 40 THD vs Output Power - PVCC=V m 00m 00m 0 40 THD vs Output Power - PVCC=V m 00m 00m m 00m 00m 0 40 V. August 0

13 Output Power () Efficiency () Test Condition: PVCC=~V, RL=6Ω, F=KHz, Gain=0dB, T= C Output Power vs PVCC THD= PVCC (V) THD= Efficiency 9V V V 0 0 Output Power Per Channel () PT83 THD vs Output Power - PVCC=V THD vs Output Power - PVCC=9V m 0m 00m 00m 0 40 THD vs Output Power - PVCC=V m 0m 00m 00m 0 40 THD vs Output Power - PVCC=V m 0m 00m 00m m 0m 00m 00m 0 40 V. 3 August 0

14 Output Power () Efficiency () Test Condition: PVCC=~V, RL=4Ω, F=KHz, Gain=0dB, T= C Output Power vs PVCC THD= PVCC (V) THD= Efficiency 9V V V 0 0 Output Power Per Channel () PT83 THD vs Output Power - PVCC=V THD vs Output Power - PVCC=9V TTTTTTTTTTTTT TTTTTTTTTTTTT m 00m 00m m 00m 00m 0 40 THD vs Output Power - PVCC=V THD vs Output Power - PVCC=V TTTTTTTTTTTTT m 00m 00m m 00m 00m 0 40 V. 4 August 0

15 Output Power () Efficiency () PT83 Test Condition: PBTL, PVCC=~V, RL=4Ω, F=KHz, Gain=0dB, T= C Output Power vs PVCC Efficiency THD= THD= 9V V V PVCC (V) THD vs Output Power - PVCC=V Output Power Per Channel () THD vs Output Power - PVCC=9V m 00m 00m 0 40 THD vs Output Power - PVCC=V m 00m 00m 0 40 THD vs Output Power - PVCC=V m 00m 00m m 00m 00m 0 40 V. August 0

16 PT83 PACKAGE INFORMATION 8-PIN, HTSSOP, 73MIL Symbol Min. Nom. Max. A A b c 0.7 TYP. e 0.6 BSC. D D E 6.4 BSC. E E L.00 REF. 0-8 Notes:. Refer to JEDEC MO-3 AET. Unit: mm V. 6 August 0

17 IMPORTANT NOTICE PT83 Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. F, 33-, Baociao Road, Sindian Dist., New Taipei City 34, Taiwan Tel: Fax: V. 7 August 0