MVSR Engineering College Electronics and Communication Department LIST OF JOURNAL PAPERS PUBLISHED BY FACULTY Acad. Year

Size: px
Start display at page:

Download "MVSR Engineering College Electronics and Communication Department LIST OF JOURNAL PAPERS PUBLISHED BY FACULTY Acad. Year"

Transcription

1 MVSR Engineering College Acad Sudhir Dakey Design of Area and Power Efficient Line Decoders for SRAM Journal of Emerging Technologies in Engineering (IJETER) Volume 5, Issue 11, ISSN : , Pages : vember (2017) 2 E.V.Naga Lakshmi Design and Implementation of Double Gate 8 T SRAM Cell Using MTCMOS Journal of e-issn : P-ISSN : X Volume-4, Issue-10 Sep, E.V.Naga Lakshmi Design and Implementation of Double Gate SRAM Cells Journal of in Electronics & Communication Engineering ISSN : (online) ISSN : X(Print) Volume-5, Issue-5 Sep-Oct, Shilpa B Darvesh 5 DVSR. Sesidhar M.Vijaya Krishna Design and Implementation of Low Power LFSR For Fast ATPG Process Comparative Analysis of SWT Based OFDM and DWT based OFDM using Different Modulation Approaches to Improve BER Performance Journal of Emerging Technologies in Engineering (IJETER) Journal of Technology ISSN : Volume-5, Issue-9 ISSN Vol-06, Issue-25 Sep,2017 July,2017

2 MVSR Engineering College Acad V.SURESHKUMAR 2 V.SURESHKUMAR 3 4 T. Kavitha V.R.Manimala N.Kavitha Sudhir Dakey 5 N. Namassivaya 6 B. Srinivas 7 N. Srinivas 8 Sreehari 9 V.SURESHKUMAR Safe Driving without using mobile phones A High Capacity and Secured color image Stegnographic technique using Discrete Wavelet Transform Design of Fully Scalable Reconfigurable Parallel Architecture for the Computation of Approximate DCT Removal of Artifacts Based on Weighted guided filtering for Digital Video quality Presentation Analysis of Routing Protocols In Ad Hoc Network s And Its Portability Design and Analysis of Gate Diffusion input technology Techniques Based double gate Full Adder Analytical Performance of Soft Data Fusion-Aided Spectrum Sensing in Hybrid Terrestrial-Satellite Networks FPGA Realization of MUX Based FIR Filter Architecture FPGA implementation of Vedic ALU with application specific Reversible Gates Journal for Innovative Engineering and Management Journal for Innovative Engineering and Management Journal of Innovative computer Science and Engineering (IJICSE) Journal of Journal of Science, Technology and Management (IJSTM) Journal of VLSI System Design and Communication Systems (IJVDCS) Journal of Satellite Communications and Networking Journal of (IJESAR) Journal of Reseach Vol-6,Issue 5,Page no Vol-6,Issue 5,Page no Vol-4, Issue-2, p.p no-126 July,2017 July,2017 March- April,2017 Vol-4, Issue-2, Feb,2017 ISSN , Vol-X, p.no-14-21, Vol-4, Issue-12, ( ) ISSN Vol 2, Issue 5, Pg no X Vol-2,Issue 5,Page no Jan,2017 v,2016 Sep,2016 Sepoct,2016 Sep- Oct,2016 international 10 N. Namassivaya Enhanced Low Power CMOS Current comparator using Diode Free Adiabatic (DFAL) Technique Journal of VLSI System Design and Communication Systems ISSN Vol-4, Issue-9 9 th Sep-2016

3 11 G.V.Chalapathi Rao 12 E.V.Naga Lakshmi 13 Shilpa B Darvesh 14 T. Kavitha 15 N.SRINIVAS DEVELOPMENT OF A NEW EFFICIENT MULTIPATH MITTIGATION ALGORITHM FOR PRECISE GPS POSITION APPLICATIONS Design of ALU Using Modified GDI Technology Enhanced Multi-threshold Schmitt Trigger Circuit Design Using FINFET Technology (IJVDCS) A Low Power 32 Bit Mac Unit Design Using Vedic Multiplier and Brent-Kung Adder Analytical performance of soft data fusion- aided spectrum sensing in hybrid terrestrial satellite networks THE IUP JOURNAL OF TELECOMMUNICATIONS Journal of Advance (IJOAR) VOL III NO3 ISSN Vol-4, Issue-8 Journal Vol-4, Issue-8 Journal of (IJESAR) Journal of Satellite Communications and Networking Vol-2, Issue-4, P.no DOI: /sat.1200 Oct, M.Sarath Chandra 17 T. Kavitha 18 KVBL Deepthi 19 E.V.Naga Lakshmi 20 SVR Manimala 21 B. Bhavani Design & Implementation of Thermometer Code TPC for BIST DWT Based Scheme For Video Watermarking An investigation on Substrate Integrated Luneburg Lens Antenna with Gradient Index and Meta Materials Implementation and Comparison of Power Gated CMOS Circuits Designing of Avionics Full Duplex Switch on Netfpga FPGA Based Performance Analysis of Micro programmed FIR filters using multipliers Journal (IJETR) Journal of Engineering and Technology (IRJET) Journal of applied engineering research ( IJAER) Journal of Engineering and Technology (IRJET) IOSR Journal Electronics and Communication Engineering Journal of Engg. Science and Generic (IJESAR ) ISSN: Vol-4, Issue-4, p.no e-issn p-issn Print ISSN Online ISSN e-issn p-issn Vol-3, Issue-7 ISSN , Vol- 11, Issue-4,Version-III P Vol-2, Issue : 4, P.no August, July,2016 July,2016 July- July-

4 22 B. Bhavani 23 N. Namassivaya LINUX Systems Development & Remote Debugging on Embedded Industrial Gate Way, IJIJR Design of 32 Bit High Speed Six Stage Pipeline RISC Processor for Convolution Journal of Innovative Technology & ) Journal of (IJESAR) Vol-4, Issue no-4, p.no: ISSN X, Journal Digital Journal DIDS Impact Factor Vol-2, Issue-4 June- July,2016 July- MVSR Engineering College Acad Vol.& Issue 1 2` Shilpa B Darvesh T. Kavitha E.V.Naga Lakshmi 3 KVBL Deepthi 4 Sudhir Dakey N.Kavitha FPGA Implementation of High Performance Fully Pipelined Aes Algorithm Using Reversible Logic A New Design of Reversible Full Substractor An Investigation of the Substrate- Integrated Luneburg Lens Antenna with Gradient Index and Metamaterial Structures An Over view of Security Issues in Internet of Things Journal of Engineering Science and Generic (IJESAR) Journal of Educational Journal of Applied Engineering Journal of Modern Trends in Engg. & ISSN : X Vol. 2, Issue : 3, P.nos : ISSN: , Impact factor : 3.318: IC, Value: 5.16, ISI: Value: 2.286, Volume : 5, Issue :4, (5) ISSN : , Vol-11, Number-8, p.p ISSN: Vol-2, Issue-11 May-June, 2016 April, 2016 April- May, 2016 v,2015

5 5 Sudhir Dakey 6 Dr. G.Kanaka Durga 7 Sudhir Dakey 8 N. Kavitha Dr. K. Usha 9 Sudhir Dakey 10 B. Sarala Design and analysis of a Full Adder Using Various Reversible Gates Design and implementation of Wallace Tree Multiplier Using Kogge Stone Adder and Brent Efficient Area and High Speed Advanced encryption Standard Algorithm Optimized Evaluation Approach to Show the Timing Hitter and I/Q Imbalance Impact in OFDM Communication System Design and Implementation of Area Delay Efficient Booth Multiplier Based on CBL Secure Data Communication using Cryptography and Steganography Standards Journal of Modern Trends in Engg. & Journal of Engineering Researach & Technology Journal of Emerging Engineering and Technology Global journal of Advanced Engineering Techniques Journal & Magazine of Engineering & Technology, Management and Journal of Emerging Engineering and Technology ISSN: Vol-2, Issue-8 Vol-3, Issue-8, ppno , ISSN (Print) ISSN (online) ISSN: , Vol-3, Issue -7 ISSN- (online) & (Print) ISSN Volume -4,Issue-4 ISSN NO (Print) ISSN NO (Online) Vol.-3, Issue-7, p.p. no , ISSN (Print) & ISSN (online) Aug,2015 Aug, B. Sarala Design and Analysis of Variable Body Bias SRAM Journal of Advanced Technology and Innovative ISSN Vol-07,Issue-06, p.p no B. Sarala 14 E.V. Naga Lakshmi 15 B. Bhavani 14 V.R.Manimala 15 V.SureshKumar 16 N.Srinivas Fault Tolerant Architecture Design for Digital Adder Implementation of Parallel Prefix Adders Using Reversible Logic Gates Design and Implementation of Folded & Un-folded Tree Architectures for Processing Unit in Wireless Sensor des FPGA implementation of short duration Video Encryption & Decryption Convolution using Delay efficient improved hybrid multiplier Cooperative Spectrum Sensing with Double Threshold and Censoring in Rayleigh Faded Cognitive Radio Network Journal of Emerging Engineering and Technology Journal & Magazine of Engineering Technology, Management and Journal of Technology Journal of Technology Wireless Personal Communication Vol-3, Issue-7,p.p no-41-47, ISSN (Print) & ISSN (online) ISSN NO , Vol-2(2015), Issue no-7 (July) p.p. no ISSN: , Vol-04, Issue- 25, Pages IJESC Vol.no.4,issue.26 Vol.82,number.2 May,2015

6 MVSR Engineering College Acad N.Namassivaya 2 N. Kavitha 3 Sudhir Dakey 4 Dr. N. Srinivas 5 Smitashree Mohopatra 6 M. Vijay Krishna 7 K.Usha 8 B. Srinivas 9 E.V.Naga Lakshmi Dynamic Power Reduction in Frequency Divider Using Advanced Adiabatic PARP reduction in OFDM system using non linear companding algorithm Design, implementation and performance analysis of 8-bit vadic multiplier Cooperative spectrum sensing with double threshold and censoring in Rayleigh faded cognitive radio network Implementation of Carry select adder using CMOS full adders Design of ternary sequence using of MATLAB Performance analysis of new binary user codes for DSCDMA communication Design and implementation of sub microns level 10T full adder in ALU using cell based and SOC technology Implementation of Time Efficient Architecture for Compressive Sensing Algorithm Journal of Engineering & Science Journal of Technology Journal of Modern Trends in Engg. & journal of Wireless personal communications, springer publication ISSN : VOL :-5/ Issue : 6/ ISSN : Vol. no:4, p.p no Issue 18 Vol-2,Issue: 6, p.p no Vol-84, issue-1 p.p no IJESR- June,2015 June 2015 June,2015 Sep,2015 IJERT Vol-4, p.p no Journal of Advanced computing communication technology Journal of Institution of Engineers (JIE) series- B journals of Engineering research and applications Journal of Multidisciplinary Education ISSN , Vol. no-3, issue 4, Vol-95, Vol-4, version-5, issue-9, ISSN pp ISSN , Impact factor -2735; IC Value-5-16, Vol-3, Issue 9 (4) Feb,2015 Dec.,2014 Sep.,2014 Sep,2014

7 10 B.Bhavani Embedded Memory Test and Repair Journal of Multi disciplinary Educational Vol-3, ISSN no-10, pp Oct, Aruna 12 B. Sarala 13 B. Sarala 14 Aruna 15 Aruna 16 KVBL Deepthi 17 KVBL Deepthi Implementation of Digital Serial FIR filter using wireless priority service (WPS). Implementation of FIR filter using novel modulo adder for residue 2 n 2 K -1 number system Design and implementation of Symmetric Cryptographic Algorithm using 5x5 square matrix with Single Point Crossover A High resolution Low Offset Voltage Gain Stability Comparator Multiplier less Design of Low Complexity FIR filter : Algorithms, CAD tools A numerically efficient power optimization scheme for coded OFDM systems in achieving minimum frame error rate. A practical frame work for the performance evaluation of classical frequency planning schemes in OFDM based on Markov s model Journal of Advanced in Electronics and Communication Engineering Organization of Scientific Community of er Journal of Advanced in Electronics and Communication Engineering Progress in Science and Engineering Journal Journal of Advanced in Electronics and Communication Engineering ISSN X Vol-3, Issue-8 Pg August, 2014 Vol-9, Issue-4, July-Aug, 2014 ISSN X Vol-3, Issue-7 pp July,2014 Vol-2, ISSN July,2014 ISSN X Vol-3, Issue-3 July,2014 IJSRP Volume-4, Issue-1 January-2014 IJERA Volume-4, Issue-1 PP January-2014

Department of Electronics and Communication LIST OF JOURNAL PAPERS PUBLISHED BY FACULTY Acad. Year

Department of Electronics and Communication LIST OF JOURNAL PAPERS PUBLISHED BY FACULTY Acad. Year S. No Department of Communication LIST OF JOURNAL PAPERS PUBLISHED BY FACULTY Acad. Year 2017-18 Name of the Staff Title of the Paper Name of Journ 1 Sudhir Dakey 2 E.V.Naga Lakshmi 3 E.V.Naga Lakshmi

More information

MVSR ENGINEERING COLLEGE, ECE DEPARTMENT Timetable for B.E. 2/4 ECE (SEC-A) Acad. Year: II Semester. Room No: EC-105 W.E.

MVSR ENGINEERING COLLEGE, ECE DEPARTMENT Timetable for B.E. 2/4 ECE (SEC-A) Acad. Year: II Semester. Room No: EC-105 W.E. MVSR EGIEERIG OEGE, EE DEPARTMET Timetable for B.E. 2/4 EE (SE-A) Acad. Year: 2016-17- II Semester Room o: E-105 W.E.F: 02-01-2017 MO T WED TRS (GP) (GP) AE (SS) T (GVR) (K) AE(SS/SD)/ET AB(GPR) (Batch

More information

Sno Projects List IEEE. High - Throughput Finite Field Multipliers Using Redundant Basis For FPGA And ASIC Implementations

Sno Projects List IEEE. High - Throughput Finite Field Multipliers Using Redundant Basis For FPGA And ASIC Implementations Sno Projects List IEEE 1 High - Throughput Finite Field Multipliers Using Redundant Basis For FPGA And ASIC Implementations 2 A Generalized Algorithm And Reconfigurable Architecture For Efficient And Scalable

More information

Design and Implementation of Wallace Tree Multiplier Using Kogge Stone Adder and Brent Kung Adder

Design and Implementation of Wallace Tree Multiplier Using Kogge Stone Adder and Brent Kung Adder International Journal of Emerging Engineering Research and Technology Volume 3, Issue 8, August 2015, PP 110-116 ISSN 2349-4395 (Print) & ISSN 2349-4409 (Online) Design and Implementation of Wallace Tree

More information

Design and Implementation of Parallel Micro-programmed FIR Filter Using Efficient Multipliers on FPGA

Design and Implementation of Parallel Micro-programmed FIR Filter Using Efficient Multipliers on FPGA 2018 IJSRST Volume 4 Issue 2 Print ISSN: 2395-6011 Online ISSN: 2395-602X Themed Section: Science and Technology Design and Implementation of Parallel Micro-programmed FIR Filter Using Efficient Multipliers

More information

Analysis Parameter of Discrete Hartley Transform using Kogge-stone Adder

Analysis Parameter of Discrete Hartley Transform using Kogge-stone Adder Analysis Parameter of Discrete Hartley Transform using Kogge-stone Adder Nikhil Singh, Anshuj Jain, Ankit Pathak M. Tech Scholar, Department of Electronics and Communication, SCOPE College of Engineering,

More information

SPIRO SOLUTIONS PVT LTD

SPIRO SOLUTIONS PVT LTD VLSI S.NO PROJECT CODE TITLE YEAR ANALOG AMS(TANNER EDA) 01 ITVL01 20-Mb/s GFSK Modulator Based on 3.6-GHz Hybrid PLL With 3-b DCO Nonlinearity Calibration and Independent Delay Mismatch Control 02 ITVL02

More information

ISSN Vol.07,Issue.08, July-2015, Pages:

ISSN Vol.07,Issue.08, July-2015, Pages: ISSN 2348 2370 Vol.07,Issue.08, July-2015, Pages:1397-1402 www.ijatir.org Implementation of 64-Bit Modified Wallace MAC Based On Multi-Operand Adders MIDDE SHEKAR 1, M. SWETHA 2 1 PG Scholar, Siddartha

More information

MVSR ENGINEERING COLLEGE, ECE DEPARTMENT Timetable for B.E. 2/4 ECE (SEC-A) Acad. Year: II Semester EC/ET LAB (DPK, AVD/ GPB) (A/B) NTL (NN)

MVSR ENGINEERING COLLEGE, ECE DEPARTMENT Timetable for B.E. 2/4 ECE (SEC-A) Acad. Year: II Semester EC/ET LAB (DPK, AVD/ GPB) (A/B) NTL (NN) Timetable for B.E. 2/4 EE (SE-A) Acad. Year: 2014-15- II Semester Room o: E-113 MO T (A) (DPK, AVD/ GPB) () (DVSRS) (DPK, AVD/ GPB) WED TRS FRI (DVSRS) (DPK) (VS) (DPK, AVD/ GPB) (A) (DPK) (AVD) RT (A)

More information

A High Speed Wallace Tree Multiplier Using Modified Booth Algorithm for Fast Arithmetic Circuits

A High Speed Wallace Tree Multiplier Using Modified Booth Algorithm for Fast Arithmetic Circuits IOSR Journal of Electronics and Communication Engineering (IOSRJECE) ISSN: 2278-2834, ISBN No: 2278-8735 Volume 3, Issue 1 (Sep-Oct 2012), PP 07-11 A High Speed Wallace Tree Multiplier Using Modified Booth

More information

M.Tech Projects. ECE (Embedded/DSP/DIP/VLSI)

M.Tech Projects. ECE (Embedded/DSP/DIP/VLSI) M.Tech Projects ECE (Embedded/DSP/DIP/VLSI) S.NO TITLE/NAME OF THE PROJECT YEAR DOMAIN IMAGE PROCESSING 1 Quality Assessment Of Deblocked Images 2 Salient Motion Features For Video Quality Assessment 3

More information

PROMINENT SPEED ARITHMETIC UNIT ARCHITECTURE FOR PROFICIENT ALU

PROMINENT SPEED ARITHMETIC UNIT ARCHITECTURE FOR PROFICIENT ALU PROMINENT SPEED ARITHMETIC UNIT ARCHITECTURE FOR PROFICIENT ALU R. Rashvenee, D. Roshini Keerthana, T. Ravi and P. Umarani Department of Electronics and Communication Engineering, Sathyabama University,

More information

Visvesvaraya Technological University, Belagavi

Visvesvaraya Technological University, Belagavi Time Table for M.TECH. Examinations, June / July 2017 M. TECH. 2010 Scheme 2011 Scheme 2012 Scheme 2014 Scheme 2016 Scheme [CBCS] Semester I II III I II III I II III I II IV I II Time Date, Day 14/06/2017,

More information

A Novel Approach For Designing A Low Power Parallel Prefix Adders

A Novel Approach For Designing A Low Power Parallel Prefix Adders A Novel Approach For Designing A Low Power Parallel Prefix Adders R.Chaitanyakumar M Tech student, Pragati Engineering College, Surampalem (A.P, IND). P.Sunitha Assistant Professor, Dept.of ECE Pragati

More information

MATLAB COMMUNICATION TITLES

MATLAB COMMUNICATION TITLES MATLAB COMMUNICATION TITLES -2018 ORTHOGONAL FREQUENCY-DIVISION MULTIPLEXING(OFDM) 1 ITCM01 New PTS Schemes For PAPR Reduction Of OFDM Signals Without Side Information 2 ITCM02 Design Space-Time Trellis

More information

Implementation and Performance Evaluation of Prefix Adders uing FPGAs

Implementation and Performance Evaluation of Prefix Adders uing FPGAs IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) ISSN: 2319 4200, ISBN No. : 2319 4197 Volume 1, Issue 1 (Sep-Oct. 2012), PP 51-57 Implementation and Performance Evaluation of Prefix Adders uing

More information

Design and Characterization of 16 Bit Multiplier Accumulator Based on Radix-2 Modified Booth Algorithm

Design and Characterization of 16 Bit Multiplier Accumulator Based on Radix-2 Modified Booth Algorithm Design and Characterization of 16 Bit Multiplier Accumulator Based on Radix-2 Modified Booth Algorithm Vijay Dhar Maurya 1, Imran Ullah Khan 2 1 M.Tech Scholar, 2 Associate Professor (J), Department of

More information

A BIST Circuit for Fault Detection Using Recursive Pseudo- Exhaustive Two Pattern Generator

A BIST Circuit for Fault Detection Using Recursive Pseudo- Exhaustive Two Pattern Generator Vol.2, Issue.3, May-June 22 pp-676-681 ISSN 2249-6645 A BIST Circuit for Fault Detection Using Recursive Pseudo- Exhaustive Two Pattern Generator K. Nivitha 1, Anita Titus 2 1 ME-VLSI Design 2 Dept of

More information

HIGH PERFORMANCE BAUGH WOOLEY MULTIPLIER USING CARRY SKIP ADDER STRUCTURE

HIGH PERFORMANCE BAUGH WOOLEY MULTIPLIER USING CARRY SKIP ADDER STRUCTURE HIGH PERFORMANCE BAUGH WOOLEY MULTIPLIER USING CARRY SKIP ADDER STRUCTURE R.ARUN SEKAR 1 B.GOPINATH 2 1Department Of Electronics And Communication Engineering, Assistant Professor, SNS College Of Technology,

More information

IJCSIET-- International Journal of Computer Science information and Engg., Technologies ISSN

IJCSIET-- International Journal of Computer Science information and Engg., Technologies ISSN High throughput Modified Wallace MAC based on Multi operand Adders : 1 Menda Jaganmohanarao, 2 Arikathota Udaykumar 1 Student, 2 Assistant Professor 1,2 Sri Vekateswara College of Engineering and Technology,

More information

DESIGN OF CONVOLUTIONAL ENCODER USING 16 BIT REVERSIBLE LOGIC VEDIC MULTIPLIER

DESIGN OF CONVOLUTIONAL ENCODER USING 16 BIT REVERSIBLE LOGIC VEDIC MULTIPLIER DESIGN OF CONVOLUTIONAL ENCODER USING 16 BIT REVERSIBLE LOGIC VEDIC MULTIPLIER *Naveen K B., **Yogananda C D., *** Dr. M B Anandaraju *Assistant Professor, Department of ECE BGS Institute of Technology,

More information

Globally Asynchronous Locally Synchronous (GALS) Microprogrammed Parallel FIR Filter

Globally Asynchronous Locally Synchronous (GALS) Microprogrammed Parallel FIR Filter IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 6, Issue 5, Ver. II (Sep. - Oct. 2016), PP 15-21 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org Globally Asynchronous Locally

More information

An Optimized Wallace Tree Multiplier using Parallel Prefix Han-Carlson Adder for DSP Processors

An Optimized Wallace Tree Multiplier using Parallel Prefix Han-Carlson Adder for DSP Processors An Optimized Wallace Tree Multiplier using Parallel Prefix Han-Carlson Adder for DSP Processors T.N.Priyatharshne Prof. L. Raja, M.E, (Ph.D) A. Vinodhini ME VLSI DESIGN Professor, ECE DEPT ME VLSI DESIGN

More information

DESIGN OF FIR FILTER ARCHITECTURE USING VARIOUS EFFICIENT MULTIPLIERS Indumathi M #1, Vijaya Bala V #2

DESIGN OF FIR FILTER ARCHITECTURE USING VARIOUS EFFICIENT MULTIPLIERS Indumathi M #1, Vijaya Bala V #2 ISSN: 0975-766X CODEN: IJPTFI Available Online through Research Article www.ijptonline.com DESIGN OF FIR FILTER ARCHITECTURE USING VARIOUS EFFICIENT MULTIPLIERS Indumathi M #1, Vijaya Bala V #2 1,2 Electronics

More information

Performance Boosting Components of Vedic DSP Processor

Performance Boosting Components of Vedic DSP Processor Performance Boosting Components of Vedic DSP Processor Anuradha Savadi Electronics and communication engineering PDA college of Engineering Kalaburgi, Karnataka, India Raju Yanamshetti Electronics and

More information

Design of Adjustable Reconfigurable Wireless Single Core

Design of Adjustable Reconfigurable Wireless Single Core IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-issn: 2278-2834,p- ISSN: 2278-8735. Volume 6, Issue 2 (May. - Jun. 2013), PP 51-55 Design of Adjustable Reconfigurable Wireless Single

More information

Modelling Of Adders Using CMOS GDI For Vedic Multipliers

Modelling Of Adders Using CMOS GDI For Vedic Multipliers Modelling Of Adders Using CMOS GDI For Vedic Multipliers 1 C.Anuradha, 2 B.Govardhana, 3 Madanna, 1 PG Scholar, Dept Of VLSI System Design, Geetanjali College Of Engineering And Technology, 2 Assistant

More information

Design and Implementation of a delay and area efficient 32x32bit Vedic Multiplier using Brent Kung Adder

Design and Implementation of a delay and area efficient 32x32bit Vedic Multiplier using Brent Kung Adder Design and Implementation of a delay and area efficient 32x32bit Vedic Multiplier using Brent Kung Adder #1 Ayushi Sharma, #2 Er. Ajit Singh #1 M.Tech. Student, #2 Assistant Professor and Faculty Guide,

More information

Title of the Program/Course. S.No. Training program

Title of the Program/Course. S.No. Training program Name: DR. P. SRI HARI Designation: Professor Department: Electronics and Communication Engg. Mail I d: srihari_p@vnrvjiet.in Experience (in years): 27 Teaching: 27 Research: 04 Others(if any, specify):

More information

ASIC Implementation of High Speed Area Efficient Arithmetic Unit using GDI based Vedic Multiplier

ASIC Implementation of High Speed Area Efficient Arithmetic Unit using GDI based Vedic Multiplier INTERNATIONAL JOURNAL OF APPLIED RESEARCH AND TECHNOLOGY ISSN 2519-5115 RESEARCH ARTICLE ASIC Implementation of High Speed Area Efficient Arithmetic Unit using GDI based Vedic Multiplier 1 M. Sangeetha

More information

By Dayadi Lakshmaiah, Dr. M. V. Subramanyam & Dr. K. Satya Prasad Jawaharlal Nehru Technological University, India

By Dayadi Lakshmaiah, Dr. M. V. Subramanyam & Dr. K. Satya Prasad Jawaharlal Nehru Technological University, India Global Journal of Researches in Engineering: F Electrical and Electronics Engineering Volume 14 Issue 9 Version 1.0 Type: Double Blind Peer Reviewed International Research Journal Publisher: Global Journals

More information

Course Outcome of M.Tech (VLSI Design)

Course Outcome of M.Tech (VLSI Design) Course Outcome of M.Tech (VLSI Design) PVL108: Device Physics and Technology The students are able to: 1. Understand the basic physics of semiconductor devices and the basics theory of PN junction. 2.

More information

FPGA Implementation of Serial and Parallel FIR Filters by using Vedic and Wallace tree Multiplier

FPGA Implementation of Serial and Parallel FIR Filters by using Vedic and Wallace tree Multiplier FPGA Implementation of Serial and Parallel FIR Filters by using Vedic and Wallace tree Multiplier P Kiran Mojesh 1, N Rajesh Babu 2 P. G. Student, Department of Electronics & Communication Engineering,

More information

Comparison of Multiplier Design with Various Full Adders

Comparison of Multiplier Design with Various Full Adders Comparison of Multiplier Design with Various Full s Aruna Devi S 1, Akshaya V 2, Elamathi K 3 1,2,3Assistant Professor, Dept. of Electronics and Communication Engineering, College, Tamil Nadu, India ---------------------------------------------------------------------***----------------------------------------------------------------------

More information

JDT EFFECTIVE METHOD FOR IMPLEMENTATION OF WALLACE TREE MULTIPLIER USING FAST ADDERS

JDT EFFECTIVE METHOD FOR IMPLEMENTATION OF WALLACE TREE MULTIPLIER USING FAST ADDERS JDT-002-2013 EFFECTIVE METHOD FOR IMPLEMENTATION OF WALLACE TREE MULTIPLIER USING FAST ADDERS E. Prakash 1, R. Raju 2, Dr.R. Varatharajan 3 1 PG Student, Department of Electronics and Communication Engineeering

More information

(M.TECH) IEEE VLSI PROJECT TITLES PROJECT NUMBER 1 Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic

(M.TECH) IEEE VLSI PROJECT TITLES PROJECT NUMBER 1 Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic 2015 2016 (M.TECH) IEEE VLSI PROJECT TITLES PROJECT NUMBER TITLE 1 Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic 2 A Modified Partial Product Generator for Redundant Binary Multipliers

More information

JDT LOW POWER FIR FILTER ARCHITECTURE USING ACCUMULATOR BASED RADIX-2 MULTIPLIER

JDT LOW POWER FIR FILTER ARCHITECTURE USING ACCUMULATOR BASED RADIX-2 MULTIPLIER JDT-003-2013 LOW POWER FIR FILTER ARCHITECTURE USING ACCUMULATOR BASED RADIX-2 MULTIPLIER 1 Geetha.R, II M Tech, 2 Mrs.P.Thamarai, 3 Dr.T.V.Kirankumar 1 Dept of ECE, Bharath Institute of Science and Technology

More information

[Krishna, 2(9): September, 2013] ISSN: Impact Factor: INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY

[Krishna, 2(9): September, 2013] ISSN: Impact Factor: INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY Design of Wallace Tree Multiplier using Compressors K.Gopi Krishna *1, B.Santhosh 2, V.Sridhar 3 gopikoleti@gmail.com Abstract

More information

High Speed Binary Counters Based on Wallace Tree Multiplier in VHDL

High Speed Binary Counters Based on Wallace Tree Multiplier in VHDL High Speed Binary Counters Based on Wallace Tree Multiplier in VHDL E.Sangeetha 1 ASP and D.Tharaliga 2 Department of Electronics and Communication Engineering, Tagore College of Engineering and Technology,

More information

MC CDMA PAPR Reduction Using Discrete Logarithmic Method

MC CDMA PAPR Reduction Using Discrete Logarithmic Method International Journal of Engineering Research and Development ISSN: 2278-067X, Volume 1, Issue 4 (June 2012), PP.38-43 www.ijerd.com MC CDMA PAPR Reduction Using Discrete Logarithmic Method B.Sarala 1,

More information

Design and implementation of Parallel Prefix Adders using FPGAs

Design and implementation of Parallel Prefix Adders using FPGAs IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-issn: 2278-2834,p- ISSN: 2278-8735. Volume 6, Issue 5 (Jul. - Aug. 2013), PP 41-48 Design and implementation of Parallel Prefix Adders

More information

Adaptive Modulation with Customised Core Processor

Adaptive Modulation with Customised Core Processor Indian Journal of Science and Technology, Vol 9(35), DOI: 10.17485/ijst/2016/v9i35/101797, September 2016 ISSN (Print) : 0974-6846 ISSN (Online) : 0974-5645 Adaptive Modulation with Customised Core Processor

More information

Fast Fourier Transform utilizing Modified 4:2 & 7:2 Compressor

Fast Fourier Transform utilizing Modified 4:2 & 7:2 Compressor International Journal of Engineering Research and Development e-issn: 2278-067X, p-issn: 2278-800X, www.ijerd.com Volume 11, Issue 05 (May 2015), PP.23-28 Fast Fourier Transform utilizing Modified 4:2

More information

DAV Institute of Engineering & Technology Department of ECE. Course Outcomes

DAV Institute of Engineering & Technology Department of ECE. Course Outcomes DAV Institute of Engineering & Technology Department of ECE Course Outcomes Upon successful completion of this course, the student will intend to apply the various outcome as:: BTEC-301, Analog Devices

More information

Design and Simulation of Convolution Using Booth Encoded Wallace Tree Multiplier

Design and Simulation of Convolution Using Booth Encoded Wallace Tree Multiplier IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-issn: 2278-2834,p- ISSN: 2278-8735. PP 42-46 www.iosrjournals.org Design and Simulation of Convolution Using Booth Encoded Wallace

More information

VLSI DFT(DESIGN FOR TESTABILITY)

VLSI DFT(DESIGN FOR TESTABILITY) S.NO PROJECT CODE 01 ITVL01 02 ITVL02 03 ITVL03 04 ITVL04 06 ITVL06 07 ITVL07 08 ITVL08 09 ITVL09 10 ITVL10 VLSI DFT(DESIGN FOR TESTABILITY) TITLE Test Stimulus Compression Based on Broadcast Scan with

More information

Index terms: Gate Diffusion Input (GDI), Complementary Metal Oxide Semiconductor (CMOS), Digital Signal Processing (DSP).

Index terms: Gate Diffusion Input (GDI), Complementary Metal Oxide Semiconductor (CMOS), Digital Signal Processing (DSP). GDI Based Design of Low Power Adders and Multipliers B.Shanmukhi Abstract: The multiplication and addition are the important operations in RISC Processor and DSP units. Specifically, speed and power efficient

More information

ISSN Vol.03,Issue.02, February-2014, Pages:

ISSN Vol.03,Issue.02, February-2014, Pages: www.semargroup.org, www.ijsetr.com ISSN 2319-8885 Vol.03,Issue.02, February-2014, Pages:0239-0244 Design and Implementation of High Speed Radix 8 Multiplier using 8:2 Compressors A.M.SRINIVASA CHARYULU

More information

Implementation of Parallel Multiplier-Accumulator using Radix- 2 Modified Booth Algorithm and SPST

Implementation of Parallel Multiplier-Accumulator using Radix- 2 Modified Booth Algorithm and SPST ǁ Volume 02 - Issue 01 ǁ January 2017 ǁ PP. 06-14 Implementation of Parallel Multiplier-Accumulator using Radix- 2 Modified Booth Algorithm and SPST Ms. Deepali P. Sukhdeve Assistant Professor Department

More information

A Novel High Performance 64-bit MAC Unit with Modified Wallace Tree Multiplier

A Novel High Performance 64-bit MAC Unit with Modified Wallace Tree Multiplier Proceedings of International Conference on Emerging Trends in Engineering & Technology (ICETET) 29th - 30 th September, 2014 Warangal, Telangana, India (SF0EC024) ISSN (online): 2349-0020 A Novel High

More information

Cmos Full Adder and Multiplexer Based Encoder for Low Resolution Flash Adc

Cmos Full Adder and Multiplexer Based Encoder for Low Resolution Flash Adc IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-issn: 2278-2834,p- ISSN: 2278-8735.Volume 12, Issue 2, Ver. II (Mar.-Apr. 2017), PP 20-27 www.iosrjournals.org Cmos Full Adder and

More information

International Journal of Digital Application & Contemporary research Website: (Volume 1, Issue 7, February 2013)

International Journal of Digital Application & Contemporary research Website:   (Volume 1, Issue 7, February 2013) Performance Analysis of OFDM under DWT, DCT based Image Processing Anshul Soni soni.anshulec14@gmail.com Ashok Chandra Tiwari Abstract In this paper, the performance of conventional discrete cosine transform

More information

Efficient Reversible GVJ Gate as Half Adder & Full Adder and its Testing on Single Precision Floating Point Multiplier

Efficient Reversible GVJ Gate as Half Adder & Full Adder and its Testing on Single Precision Floating Point Multiplier Efficient Reversible GVJ Gate as Half Adder & Full Adder and its Testing on Single Precision Floating Point Multiplier Efficient Reversible GVJ Gate as Half Adder & Full Adder and its Testing on Single

More information

SIGNED PIPELINED MULTIPLIER USING HIGH SPEED COMPRESSORS

SIGNED PIPELINED MULTIPLIER USING HIGH SPEED COMPRESSORS INTERNATIONAL JOURNAL OF RESEARCH IN COMPUTER APPLICATIONS AND ROBOTICS ISSN 2320-7345 SIGNED PIPELINED MULTIPLIER USING HIGH SPEED COMPRESSORS 1 T.Thomas Leonid, 2 M.Mary Grace Neela, and 3 Jose Anand

More information

A New High Speed Low Power Performance of 8- Bit Parallel Multiplier-Accumulator Using Modified Radix-2 Booth Encoded Algorithm

A New High Speed Low Power Performance of 8- Bit Parallel Multiplier-Accumulator Using Modified Radix-2 Booth Encoded Algorithm A New High Speed Low Power Performance of 8- Bit Parallel Multiplier-Accumulator Using Modified Radix-2 Booth Encoded Algorithm V.Sandeep Kumar Assistant Professor, Indur Institute Of Engineering & Technology,Siddipet

More information

A design of 16-bit adiabatic Microprocessor core

A design of 16-bit adiabatic Microprocessor core 194 A design of 16-bit adiabatic Microprocessor core Youngjoon Shin, Hanseung Lee, Yong Moon, and Chanho Lee Abstract A 16-bit adiabatic low-power Microprocessor core is designed. The processor consists

More information

Modified Booth Encoding Multiplier for both Signed and Unsigned Radix Based Multi-Modulus Multiplier

Modified Booth Encoding Multiplier for both Signed and Unsigned Radix Based Multi-Modulus Multiplier Modified Booth Encoding Multiplier for both Signed and Unsigned Radix Based Multi-Modulus Multiplier M.Shiva Krushna M.Tech, VLSI Design, Holy Mary Institute of Technology And Science, Hyderabad, T.S,

More information

Review Paper on an Efficient Processing by Linear Convolution using Vedic Mathematics

Review Paper on an Efficient Processing by Linear Convolution using Vedic Mathematics Review Paper on an Efficient Processing by Linear Convolution using Vedic Mathematics Taruna Patil, Dr. Vineeta Saxena Nigam Electronics & Communication Dept. UIT, RGPV, Bhopal Abstract In this Technical

More information

MACGDI: Low Power MAC Based Filter Bank Using GDI Logic for Hearing Aid Applications

MACGDI: Low Power MAC Based Filter Bank Using GDI Logic for Hearing Aid Applications International Journal of Electronics and Electrical Engineering Vol. 5, No. 3, June 2017 MACGDI: Low MAC Based Filter Bank Using GDI Logic for Hearing Aid Applications N. Subbulakshmi Sri Ramakrishna Engineering

More information

FPGA implementation of DWT for Audio Watermarking Application

FPGA implementation of DWT for Audio Watermarking Application FPGA implementation of DWT for Audio Watermarking Application Naveen.S.Hampannavar 1, Sajeevan Joseph 2, C.B.Bidhul 3, Arunachalam V 4 1, 2, 3 M.Tech VLSI Students, 4 Assistant Professor Selection Grade

More information

Design of Low power and Area Efficient 8-bit ALU using GDI Full Adder and Multiplexer

Design of Low power and Area Efficient 8-bit ALU using GDI Full Adder and Multiplexer Design of Low power and Area Efficient 8-bit ALU using GDI Full Adder and Multiplexer Mr. Y.Satish Kumar M.tech Student, Siddhartha Institute of Technology & Sciences. Mr. G.Srinivas, M.Tech Associate

More information

INTERNATIONAL JOURNAL OF PURE AND APPLIED RESEARCH IN ENGINEERING AND TECHNOLOGY

INTERNATIONAL JOURNAL OF PURE AND APPLIED RESEARCH IN ENGINEERING AND TECHNOLOGY INTERNATIONAL JOURNAL OF PURE AND APPLIED RESEARCH IN ENGINEERING AND TECHNOLOGY A PATH FOR HORIZING YOUR INNOVATIVE WORK DESIGN AND IMPLEMENTATION OF TRUNCATED MULTIPLIER FOR DSP APPLICATIONS AKASH D.

More information

Implementation of FPGA based Design for Digital Signal Processing

Implementation of FPGA based Design for Digital Signal Processing e-issn 2455 1392 Volume 2 Issue 8, August 2016 pp. 150 156 Scientific Journal Impact Factor : 3.468 http://www.ijcter.com Implementation of FPGA based Design for Digital Signal Processing Neeraj Soni 1,

More information

Mahendra Engineering College, Namakkal, Tamilnadu, India.

Mahendra Engineering College, Namakkal, Tamilnadu, India. Implementation of Modified Booth Algorithm for Parallel MAC Stephen 1, Ravikumar. M 2 1 PG Scholar, ME (VLSI DESIGN), 2 Assistant Professor, Department ECE Mahendra Engineering College, Namakkal, Tamilnadu,

More information

Nutaq OFDM Reference

Nutaq OFDM Reference Nutaq OFDM Reference Design FPGA-based, SISO/MIMO OFDM PHY Transceiver PRODUCT SHEET QUEBEC I MONTREAL I NEW YORK I nutaq.com Nutaq OFDM Reference Design SISO/2x2 MIMO Implementation Simulation/Implementation

More information

Review On Design Of Low Power Multiply And Accumulate Unit Using Baugh-Wooley Based Multiplier

Review On Design Of Low Power Multiply And Accumulate Unit Using Baugh-Wooley Based Multiplier Review On Design Of Low Power Multiply And Accumulate Unit Using Baugh-Wooley Based Multiplier Ku. Shweta N. Yengade 1, Associate Prof. P. R. Indurkar 2 1 M. Tech Student, Department of Electronics and

More information

VLSI Implementation of Auto-Correlation Architecture for Synchronization of MIMO-OFDM WLAN Systems

VLSI Implementation of Auto-Correlation Architecture for Synchronization of MIMO-OFDM WLAN Systems JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.10, NO.3, SEPTEMBER, 2010 185 VLSI Implementation of Auto-Correlation Architecture for Synchronization of MIMO-OFDM WLAN Systems Jongmin Cho*, Jinsang

More information

IJCSIET--International Journal of Computer Science information and Engg., Technologies ISSN

IJCSIET--International Journal of Computer Science information and Engg., Technologies ISSN An efficient add multiplier operator design using modified Booth recoder 1 I.K.RAMANI, 2 V L N PHANI PONNAPALLI 2 Assistant Professor 1,2 PYDAH COLLEGE OF ENGINEERING & TECHNOLOGY, Visakhapatnam,AP, India.

More information

Design Of Arthematic Logic Unit using GDI adder and multiplexer 1

Design Of Arthematic Logic Unit using GDI adder and multiplexer 1 Design Of Arthematic Logic Unit using GDI adder and multiplexer 1 M.Vishala, 2 Maddana, 1 PG Scholar, Dept of VLSI System Design, Geetanjali college of engineering & technology, 2 HOD Dept of ECE, Geetanjali

More information

Multiplier Design and Performance Estimation with Distributed Arithmetic Algorithm

Multiplier Design and Performance Estimation with Distributed Arithmetic Algorithm Multiplier Design and Performance Estimation with Distributed Arithmetic Algorithm M. Suhasini, K. Prabhu Kumar & P. Srinivas Department of Electronics & Comm. Engineering, Nimra College of Engineering

More information

International Journal of Advance Research in Computer Science and Management Studies

International Journal of Advance Research in Computer Science and Management Studies Volume 3, Issue 2, February 2015 ISSN: 2321 7782 (Online) International Journal of Advance Research in Computer Science and Management Studies Research Article / Survey Paper / Case Study Available online

More information

DESIGN, IMPLEMENTATION AND OPTIMISATION OF 4X4 MIMO-OFDM TRANSMITTER FOR

DESIGN, IMPLEMENTATION AND OPTIMISATION OF 4X4 MIMO-OFDM TRANSMITTER FOR DESIGN, IMPLEMENTATION AND OPTIMISATION OF 4X4 MIMO-OFDM TRANSMITTER FOR COMMUNICATION SYSTEMS Abstract M. Chethan Kumar, *Sanket Dessai Department of Computer Engineering, M.S. Ramaiah School of Advanced

More information

Optimized BPSK and QAM Techniques for OFDM Systems

Optimized BPSK and QAM Techniques for OFDM Systems I J C T A, 9(6), 2016, pp. 2759-2766 International Science Press ISSN: 0974-5572 Optimized BPSK and QAM Techniques for OFDM Systems Manikandan J.* and M. Manikandan** ABSTRACT A modulation is a process

More information

Analysis of Interference & BER with Simulation Concept for MC-CDMA

Analysis of Interference & BER with Simulation Concept for MC-CDMA IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-issn: 2278-2834,p- ISSN: 2278-8735.Volume 9, Issue 4, Ver. IV (Jul - Aug. 2014), PP 46-51 Analysis of Interference & BER with Simulation

More information

A Fixed-Width Modified Baugh-Wooley Multiplier Using Verilog

A Fixed-Width Modified Baugh-Wooley Multiplier Using Verilog A Fixed-Width Modified Baugh-Wooley Multiplier Using Verilog K.Durgarao, B.suresh, G.Sivakumar, M.Divaya manasa Abstract Digital technology has advanced such that there is an increased need for power efficient

More information

Design and Implementation Radix-8 High Performance Multiplier Using High Speed Compressors

Design and Implementation Radix-8 High Performance Multiplier Using High Speed Compressors Design and Implementation Radix-8 High Performance Multiplier Using High Speed Compressors M.Satheesh, D.Sri Hari Student, Dept of Electronics and Communication Engineering, Siddartha Educational Academy

More information

Design and Implementation of Pipelined 4-Bit Binary Multiplier Using M.G.D.I. Technique

Design and Implementation of Pipelined 4-Bit Binary Multiplier Using M.G.D.I. Technique Volume 2 Issue 3 September 2014 ISSN: 2320-9984 (Online) International Journal of Modern Engineering & Management Research Website: www.ijmemr.org Design and Implementation of Pipelined 4-Bit Binary Multiplier

More information

Design of Roba Mutiplier Using Booth Signed Multiplier and Brent Kung Adder

Design of Roba Mutiplier Using Booth Signed Multiplier and Brent Kung Adder International Journal of Engineering Science Invention (IJESI) ISSN (Online): 2319 6734, ISSN (Print): 2319 6726 Volume 7 Issue 4 Ver. II April 2018 PP 08-14 Design of Roba Mutiplier Using Booth Signed

More information

An Implementation of LSB Steganography Using DWT Technique

An Implementation of LSB Steganography Using DWT Technique An Implementation of LSB Steganography Using DWT Technique G. Raj Kumar, M. Maruthi Prasada Reddy, T. Lalith Kumar Electronics & Communication Engineering #,JNTU A University Electronics & Communication

More information

Realization of 8x8 MIMO-OFDM design system using FPGA veritex 5

Realization of 8x8 MIMO-OFDM design system using FPGA veritex 5 Realization of 8x8 MIMO-OFDM design system using FPGA veritex 5 Bharti Gondhalekar, Rajesh Bansode, Geeta Karande, Devashree Patil Abstract OFDM offers high spectral efficiency and resilience to multipath

More information

A Survey on Power Reduction Techniques in FIR Filter

A Survey on Power Reduction Techniques in FIR Filter A Survey on Power Reduction Techniques in FIR Filter 1 Pooja Madhumatke, 2 Shubhangi Borkar, 3 Dinesh Katole 1, 2 Department of Computer Science & Engineering, RTMNU, Nagpur Institute of Technology Nagpur,

More information

Comparative Analysis of Multiplier in Quaternary logic

Comparative Analysis of Multiplier in Quaternary logic IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 3, Ver. I (May - Jun. 2015), PP 06-11 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org Comparative Analysis of Multiplier

More information

An Design of Radix-4 Modified Booth Encoded Multiplier and Optimised Carry Select Adder Design for Efficient Area and Delay

An Design of Radix-4 Modified Booth Encoded Multiplier and Optimised Carry Select Adder Design for Efficient Area and Delay An Design of Radix-4 Modified Booth Encoded Multiplier and Optimised Carry Select Adder Design for Efficient Area and Delay 1. K. Nivetha, PG Scholar, Dept of ECE, Nandha Engineering College, Erode. 2.

More information

A GENERAL SYSTEM DESIGN & IMPLEMENTATION OF SOFTWARE DEFINED RADIO SYSTEM

A GENERAL SYSTEM DESIGN & IMPLEMENTATION OF SOFTWARE DEFINED RADIO SYSTEM A GENERAL SYSTEM DESIGN & IMPLEMENTATION OF SOFTWARE DEFINED RADIO SYSTEM 1 J. H.VARDE, 2 N.B.GOHIL, 3 J.H.SHAH 1 Electronics & Communication Department, Gujarat Technological University, Ahmadabad, India

More information

INTERNATIONAL JOURNAL OF PURE AND APPLIED RESEARCH IN ENGINEERING AND TECHNOLOGY

INTERNATIONAL JOURNAL OF PURE AND APPLIED RESEARCH IN ENGINEERING AND TECHNOLOGY INTERNATIONAL JOURNAL OF PURE AND APPLIED RESEARCH IN ENGINEERING AND TECHNOLOGY A PATH FOR HORIZING YOUR INNOVATIVE WORK DESIGN OF A CARRY TREE ADDER VISHAL R. NAIK 1, SONIA KUWELKAR 2 1. Microelectronics

More information

Recursive Pseudo-Exhaustive Two-Pattern Generator PRIYANSHU PANDEY 1, VINOD KAPSE 2 1 M.TECH IV SEM, HOD 2

Recursive Pseudo-Exhaustive Two-Pattern Generator PRIYANSHU PANDEY 1, VINOD KAPSE 2 1 M.TECH IV SEM, HOD 2 Recursive Pseudo-Exhaustive Two-Pattern Generator PRIYANSHU PANDEY 1, VINOD KAPSE 2 1 M.TECH IV SEM, HOD 2 Abstract Pseudo-exhaustive pattern generators for built-in self-test (BIST) provide high fault

More information

International Journal Of Scientific Research And Education Volume 3 Issue 6 Pages June-2015 ISSN (e): Website:

International Journal Of Scientific Research And Education Volume 3 Issue 6 Pages June-2015 ISSN (e): Website: International Journal Of Scientific Research And Education Volume 3 Issue 6 Pages-3529-3538 June-2015 ISSN (e): 2321-7545 Website: http://ijsae.in Efficient Architecture for Radix-2 Booth Multiplication

More information

OFDM Based Low Power Secured Communication using AES with Vedic Mathematics Technique for Military Applications

OFDM Based Low Power Secured Communication using AES with Vedic Mathematics Technique for Military Applications OFDM Based Low Power Secured Communication using AES with Vedic Mathematics Technique for Military Applications Elakkiya.V 1, Sharmila.S 2, Swathi Priya A.S 3, Vinodha.K 4 1,2,3,4 Department of Electronics

More information

EC 1354-Principles of VLSI Design

EC 1354-Principles of VLSI Design EC 1354-Principles of VLSI Design UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY PART-A 1. What are the four generations of integrated circuits? 2. Give the advantages of IC. 3. Give the variety of

More information

The Parametric Analysis of Gaussian Pulse Shaping Filter in WCDMA Network

The Parametric Analysis of Gaussian Pulse Shaping Filter in WCDMA Network Abstract The Parametric Analysis of Gaussian Pulse Shaping Filter in WCDMA Network Shilpa Shukla*, Mr. Puran Gour,*Student, H.O.D, Department of Electronics & Comm., NIIST, Bhopal (M.P.) Digital Signal

More information

nmos, pmos - Enhancement and depletion MOSFET, threshold voltage, body effect

nmos, pmos - Enhancement and depletion MOSFET, threshold voltage, body effect COURSE DELIVERY PLAN - THEORY Page! 1 of! 7 Department of Electronics and Communication Engineering B.E/B.Tech/M.E/M.Tech : EC Regulation: 2016(Autonomous) PG Specialization : Not Applicable Sub. Code

More information

A CASE STUDY OF CARRY SKIP ADDER AND DESIGN OF FEED-FORWARD MECHANISM TO IMPROVE THE SPEED OF CARRY CHAIN

A CASE STUDY OF CARRY SKIP ADDER AND DESIGN OF FEED-FORWARD MECHANISM TO IMPROVE THE SPEED OF CARRY CHAIN Volume 117 No. 17 2017, 91-99 ISSN: 1311-8080 (printed version); ISSN: 1314-3395 (on-line version) url: http://www.ijpam.eu ijpam.eu A CASE STUDY OF CARRY SKIP ADDER AND DESIGN OF FEED-FORWARD MECHANISM

More information

FPGA Implementation of MAC Unit Design by Using Vedic Multiplier

FPGA Implementation of MAC Unit Design by Using Vedic Multiplier FPGA Implementation of MAC Unit Design by Using Vedic Multiplier Syed Nighat Deptt of Electronics & Communication Engg. Anjuman College Of Engg &Tech., Nagpur, India nighatsyed786@gmail.com Prof. M. Nasiruddin

More information

CONTENTS. low power vlsi design (COMMON TO VLSI/VLSI DESIGN/VLSI SYSTEM DESIGN) OW-POWER CIRCUIT DESIGN SOURCES OF POWER DISSIPATION

CONTENTS. low power vlsi design (COMMON TO VLSI/VLSI DESIGN/VLSI SYSTEM DESIGN) OW-POWER CIRCUIT DESIGN SOURCES OF POWER DISSIPATION i low power vlsi design FOR m.tech (jntu - h&k) i year Ii semester (COMMON TO VLSI/VLSI DESIGN/VLSI SYSTEM DESIGN) CONTENTS UNIT - I [FUND FUNDAMENT AMENTALS ALS OF LOW OW-POWER CMOS VLSI DESIGN]... 1.1-1.12

More information

International Journal of Advance Research in Engineering, Science & Technology

International Journal of Advance Research in Engineering, Science & Technology Impact Factor (SJIF): 5.301 International Journal of Advance Research in Engineering, Science & Technology e-issn: 2393-9877, p-issn: 2394-2444 Volume 5, Issue 3, March-2018 DESIGN AND ANALYSIS OF VEDIC

More information

ISSN:

ISSN: 308 Vol 04, Issue 03; May - June 013 http://ijves.com ISSN: 49 6556 VLSI Implementation of low Cost and high Speed convolution Based 1D Discrete Wavelet Transform POOJA GUPTA 1, SAROJ KUMAR LENKA 1 Department

More information

AN EFFICIENT MAC DESIGN IN DIGITAL FILTERS

AN EFFICIENT MAC DESIGN IN DIGITAL FILTERS AN EFFICIENT MAC DESIGN IN DIGITAL FILTERS THIRUMALASETTY SRIKANTH 1*, GUNGI MANGARAO 2* 1. Dept of ECE, Malineni Lakshmaiah Engineering College, Andhra Pradesh, India. Email Id : srikanthmailid07@gmail.com

More information

COMPARISION OF LOW POWER AND DELAY USING BAUGH WOOLEY AND WALLACE TREE MULTIPLIERS

COMPARISION OF LOW POWER AND DELAY USING BAUGH WOOLEY AND WALLACE TREE MULTIPLIERS COMPARISION OF LOW POWER AND DELAY USING BAUGH WOOLEY AND WALLACE TREE MULTIPLIERS ( 1 Dr.V.Malleswara rao, 2 K.V.Ganesh, 3 P.Pavan Kumar) 1 Professor &HOD of ECE,GITAM University,Visakhapatnam. 2 Ph.D

More information

Performance Evaluation of Wireless Communication System Employing DWT-OFDM using Simulink Model

Performance Evaluation of Wireless Communication System Employing DWT-OFDM using Simulink Model Performance Evaluation of Wireless Communication System Employing DWT-OFDM using Simulink Model M. Prem Anand 1 Rudrashish Roy 2 1 Assistant Professor 2 M.E Student 1,2 Department of Electronics & Communication

More information

International Journal for Research in Applied Science & Engineering Technology (IJRASET) Design A Power Efficient Compressor Using Adders Abstract

International Journal for Research in Applied Science & Engineering Technology (IJRASET) Design A Power Efficient Compressor Using Adders Abstract Design A Power Efficient Compressor Using Adders Vibha Mahilang 1, Ravi Tiwari 2 1 PG Student [VLSI Design], Dept. of ECE, SSTC, Shri Shankracharya Group of Institutions, Bhilai, CG, India 2 Assistant

More information