UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD. BROADCOM CORPORATION Petitioner v. TESSERA, INC. Patent Owner.

Transcription

1 UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD BROADCOM CORPORATION Petitioner v. TESSERA, INC. Patent Owner. Patent No. 6,856,007 Issue Date: February 15, 2005 Title: HIGH-FREQUENCY CHIP PACKAGES Inter Partes Review No. Unassigned DECLARATION OF DR. JEFFREY C. SUHLING

2 CONTENTS CONTENTS... 2 I. Introduction And Qualifications... 4 II. Understanding of the Governing Law and Perspectives Applied... 8 A. Types Of Claims Independent And Dependent... 8 B. Unpatentability By Anticipation Or Obviousness... 8 C. Secondary Or Objective Evidence Of Non-Obviousness... 9 D. Interpreting Patents Claims Before The Patent Office... 9 E. Relevant Time Period For Analysis F. Level Of Ordinary Skill In The Art In The Relevant Timeframe III. 007 Information Considered and Bases For My Opinion IV. Overview Of The 007 patent A. Specification B. Challenged Claims and Applicable Construction C. Prosecution History V. Detailed Analysis of the Applicable Level of Skill and Prior Art A. General Techinical Background Interconnections and Package Types Known Soldering Techniques Understanding Within The Art Of Effect of Solder Thickness Desirability of Uniform Solder Joint B. Amkor MLF The MLF Application Notes Describe All Features of Independent Claim The MLF Application Notes Describe All Features of Dependent Claim The MLF Application Notes Describe All Features of Dependent Claim The MLF Application Notes Describe All Features of Dependent Claim The MLF Application Notes Describe All Features of Dependent Claim The MLF Application Notes Describe All Features of Independent Claim C. Sharma Sharma Describe All Features of Independent Claim It Would Have Been Obvious to Apply a Unitary Solder Layer to Sharma s QFN Package As Recited In Dependent Claim

3 3. It Would Have Been Obvious to Apply a Unitary Solder Layer Having the Thickness Recited In Dependent Claim 13 To Sharma s QFN Package It Would Have Been Obvious To Mount Shama s QFN Package to A Circuit Panel As Recited In Dependent Claim It Would Have Been Obvious to Apply a Unitary Solder Layer Having the Thickness Recited In Dependent Claim 13 To Sharma s QFN Package It Would Have Been Obvious to Bond Sharma s QFN Package To A Circuit Panel To Form An Assembly As Recited in Independent Claim Summary of Conclusions As To Sharma D. Secondary or Objective Evidence of Non-obviousness VI. Overall Conclusion

4 I, Jeffrey C. Suhling, a resident of Opelika, Alabama, hereby declare as follows: 1. I have been retained by Foley & Lardner LLP to provide certain opinions concerning the validity of claims 1, 11, 12, 13, 16 and 18 of U.S. Pat. No. 6,856,007 ( the 007 patent ) (Ex. 1001), which I refer to in this declaration collectively as the challenged claims or claims at issue. I am being compensated for my time at a rate of $300 per hour. I am not receiving any other form of compensation. I have no interest in the outcome of this proceeding, and my compensation is not dependent on the content of my opinions or the outcome of this proceeding. I. Introduction And Qualifications 2. My technical background and experience are summarized in my resume (Exhibit A to this declaration). In summary, I earned a Bachelor of Science in Applied Mathematics, Engineering, and Physics (AMEP) from the University of Wisconsin in I earned a Master of Science in Engineering Mechanics from the University of Wisconsin in 1981, and a Doctorate in Engineering Mechanics from the University of Wisconsin in I am currently employed as a Quina Distinguished Professor and Department Chair at the Department of Mechanical Engineering at Auburn University in Auburn, Alabama. I have been a Professor at Auburn University

5 since I am a member of the American Society for Mechanical Engineers (ASME) and the Institute of Electrical and Electronics Engineers (IEEE), and currently serve on several boards. 4. My primary areas of expertise and research are semiconductor packaging and solid mechanics. I have over 30 years of experience in each of these fields. In the area of semiconductor packaging, I have extensive experience in electronics assembly and packaging technologies and processes, stress and strain analysis of electronic products, on-chip silicon sensors, solder joint reliability, material testing and mechanical behavior of solders and microelectronic encapsulants, and finite element modeling (FEA) and reliability modeling of electronic products. I have regularly taught undergraduate-level and graduate-level courses on electronics packaging technology for the past 25 years. I have published and presented over 425 technical papers in various international journals and conferences. 5. I co-founded the Center for Advanced Vehicle Electronics or CAVE in This organization is a research center for semiconductor packaging that has been continuously funded for the past 18 years by the National Science Foundation and over 50 member companies. The CAVE Center specializes in the assembly, packaging, mechanics, thermal, and reliability aspects of semiconductor packaging in harsh environments such as automotive and

6 aerospace electronics, computer servers, cellular phones and portable electronics, among other devices. I served as Center Director of CAVE from , and Center Associate Director from I have continued to direct two CAVE research areas (Lead Free Soldering, and Flip Chip and Underfills) since being promoted in 2008 to Department Chair of the Department of Mechanical Engineering 6. I have received over 100 contracts and grants to support my research, the bulk of which is focused on various aspects of semiconductor packaging. In particular, I have obtained research support from the National Science Foundation, Semiconductor Research Corporation, NASA, Department of Defense - Army, Air Force, Navy, and over 50 companies including Texas Instruments, ST Microelectronics, Freescale Semiconductor, NXP, Cookson Electronics, Henkel Corporation, Schlumberger, John Deere Electronics, Chrysler Corporation, Continental Automotive, Siemens, LG, General Dynamics Corporation, and others. I have received several awards including being elected a Fellow of the American Society of Mechanical Engineers, as well as receiving the Electronic Packaging Division Mechanics Research Award from the same society. 7. As evidenced by my resume attached to this declaration, I am well versed in semiconductor packaging technology and I have been working in that

7 field for nearly 30 years from 1988-present. I have published and presented over 350 technical papers in the electronic packaging technical area, as well as attending over 50 technical conferences in the field. I have served as the Conference General Chair of the 2009 International Conference on Packaging and Integration of Electronic and Photonic Microsystems (InterPACK), and am currently serving as the Vice Program Chair for the 2017 Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm). I have also served in other leadership roles in the semiconductor packaging area, including my current appointment as Associate Editor for the ASME Journal of Electronic Packaging, a leading technical journal in the field. 8. I am very familiar with the technology of semiconductor packaging, and my work in this area for the past three decades has included a wide range of packaging technologies including through-hole components, leaded surface mount plastic packages, leadless ceramic and plastic packages, ceramic and plastic ball grid array technologies, chip scale packages, flip chip on laminate and flip chip in package, and stacked die and 3D packaging technologies. My prior experiences includes the semiconductor packaging technologies and microelectronics soldering techniques described in the 007 patent, as they existed around the August, 2001 time frame of the alleged invention of the 007 patent

8 II. Understanding of the Governing Law and Perspectives Applied A. Types Of Claims Independent And Dependent 9. I understand that there are two types of U.S. patent claims: 1) independent claims and 2) dependent claims. I understand that independent claims only include the aspects stated in the independent claim. I further understand that dependent claims include the aspects stated in that dependent claim, and any other aspects stated in any claim from which that dependent claim depends. B. Unpatentability By Anticipation Or Obviousness 10. I understand that a claim is not patentable if it is anticipated or obvious. I understand that anticipation of a claim requires that every element of a claim is disclosed expressly or inherently in a single prior art reference, arranged as in the claim, when considered from the perspective of a person of ordinary skill in the relevant art. I understand that when the structure recited in a reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. 11. I further understand that obviousness of a claim requires that the claim be obvious from the perspective of a person of ordinary skill in the relevant art, at the time the invention was made. In analyzing obviousness, I understand that it is important to understand the scope of the claims, the level of skill in the relevant art, the scope and content of the prior art, the differences between the prior art and the claims, and any secondary considerations (described below). I also

9 understand that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill. There may also be a specific teaching, suggestion or motivation to combine any first prior art reference with a second prior art reference. Such a teaching, suggestion, or motivation to combine the first prior art reference with the second prior art reference can be explicit or implicit. C. Secondary Or Objective Evidence Of Non-Obviousness 12. I understand that secondary (or objective) considerations are relevant to the determination of whether a claim is obvious. Such secondary (or objective), considerations can include evidence of commercial success caused by an invention evidence of a long-felt need that was solved by an invention, evidence that others copied an invention, or evidence that an invention achieved a surprising or unexpected result. I understand that such evidence must have a nexus, or causal relationship to the elements of a claim, in order to be relevant to the obviousness or non-obviousness of the claim. D. Interpreting Patents Claims Before The Patent Office 13. I understand that inter partes review is a proceeding before the United States Patent & Trademark Office ( Patent Office ) for evaluating the unpatentability of an issued patent claim. Counsel has informed me that claims in

10 an inter partes review are given their broadest reasonable interpretation that is consistent with the patent specification. I understand that a patent s specification includes all the figures, discussion, and claims within the patent document. I understand that the Patent Office will look to the specification to see if there is a definition for a claim term, and if not, will apply the broadest reasonable ordinary meaning from the perspective of a person of ordinary skill in the art. However, I also understand that if a term has no accepted meaning to those of ordinary skill in the prior art, its meaning, then, must be found in the patent. I present a more detailed explanation of certain of the terms in the 007 patent in the section entitled Detailed Explanation of Claim Terms below. E. Relevant Time Period For Analysis 14. I understand that the earliest patent application filing leading to U.S. Pat. No. 6,856,007 ( the 007 patent") (Ex. 1001) was a provisional application filed on August 28, 2001, and I have assumed this is the 007 patent s alleged invention date. I have therefore analyzed the unpatentability of the claims as of that day or somewhat before (approximately 2000 August 28, 2001), understanding that as time passes the knowledge of a person of ordinary skill in the art will increase. I may refer to the relevant time period as in this declaration, with the understanding that this does not include the time period on or after the filing date of the first application (August 28, 2001)

11 F. Level Of Ordinary Skill In The Art In The Relevant Timeframe 15. To assess the level of ordinary skill in the art at that time, I understand that one should consider factors such as: (a) the educational background of those actively working in the field at the time the invention was made; (b) the type of problems encountered in the art; (c) the various ways that others sought to solve the existing problems; (d) the rapidity with which innovations were being made in the art at the time of the invention was made; (e) the level of technological sophistication at the time the invention was made; (f) the educational level of the inventor; and (g) the teachings and disclosures of any references that indicate what the level of ordinary skill in the field may have been at the time the invention was made. 16. Considering all of these factors, it is my opinion that one of ordinary skill in the art of the 007 patent would have been a person having a Bachelor s degree in physics or engineering and about four years of experience in semiconductor packaging. I believe that the person of ordinary skill would have an understanding of techniques utilized for soldering a packaged chip to a circuit board as known and used conventionally by , as well as the general thermal, reliability, and economic design considerations used for soldering packaged chips to a circuit board at that time as discussed further below

12 17. I base the foregoing on my own experience as an educator at Auburn University, where certain of my former students in the relevant timeframe were involved in the design and development of semiconductor packages and associated technology. Further, I have been a frequent attendee at conferences and conventions, including several within or immediately before the relevant time-frame, at which I interacted with engineers working in the industry. Some examples include the 1999, 2000, and 2001 IEEE Electronic Components and Technology Conferences, the 1999 and 2001 ASME InterPACK Conferences, the 1999 IMAPS annual conference, the 2000 NEPCON West Conference and Exhibition, and the 2001 SMTA Surface Mount International Conference. 18. I note that my understanding of the applicable level of skill is the same as the assessment of other experts in the 1010 Investigation discussed below, including Patent Owner s expert, Dr. Paul Kohl. 19. My statements in this declaration are given from the perspective of a person of ordinary skill in the art at the time of the August 2001 filing date of the 007 patent, and for some time before then, unless otherwise specifically indicated. This is true even if my statements are given in the present tense. III. 007 Information Considered and Bases For My Opinion 20. In forming my opinion, I have relied on the 007 patent claims, the 007 patent specification, the exhibits to the Petition for inter partes review of the

13 007 patent, and my own experience and expertise of the knowledge of the person of ordinary skill in the relevant art in the timeframe, as discussed in more detail above. 21. I note that I previously was retained by Petitioner and certain other respondents as a technical expert in an investigation pending before the International Trade Commission, In the Matter of Certain Semiconductor Devices, Semiconductor Device Packages, and Products Containing Same, No. 337-TA ( ITC Investigation or 1010 Investigation ). In connection with the ITC Investigation, I testified as an expert witness regarding certain technical issues relating to the 007 patent. While my testimony and opinions in the Investigation were primarily directed to infringement issues, I also considered information and testimony offered by experts for both parties relating to the validity of claims 13, 16 and 18 of the 007 patent, including the testimony offered by Patent Owner s expert, Dr. Paul Kohl and Respondents expert, Dr. Pradeep Lall, as discussed below. IV. Overview Of The 007 patent A. Specification 22. The 007 patent relates to a semiconductor package and printed circuit board or PCB design to improve heat dissipation from the chip in the package

14 The patent describes how radio frequency or RF semiconductor chips generate extraordinary amounts of heat that need to be drawn away from the chip. 23. As discussed further below, the challenged claims, in whole or in part, are directed to a packaged semiconductor chip that includes a thermal conductor on a surface of the packaged that has a unitary, solder-wettable surface that is designed to facilitate heat transfer from the semiconductor chip to a thermal conductor mounting on a circuit board. Certain of the challenged claims, specifically, claims 13, 16 and 18 (which were at issue in the ITC Investigation) are limited to the use of a specific solder thickness or bonding spacing for attaching the package to a PCB. 24. The Background section of the 007 patent, at column 1, lines 15-20, indicates that Semiconductor chips or dies are provided in packages which facilitate handling of the chip during manufacture and mounting of the chip on an external substrate such as a circuit board or other circuit panel. At column 1, lines 31-33, the 007 patent acknowledges that it was known to mount a package chip by soldering and to bond the terminals of the chip (die) to the substrate. 25. The Background section refers to a particular type of packaging technology sold under the trademark μbga, which is registered to Tessera. As discussed in the Background, one aspect of Tessera s μbga technology involves the use of a dielectric element having terminals connected to the die. The

15 connection between the terminals and the die are formed by what Tessera characterizes as flexible leads, such that the terminals remain movable with respect to the chip. This technology may utilize a layer of compliant material provided between the dielectric and the chip. According to Tessera, because the terminals on the dielectric can move relative to the chip, the assembly can compensate for differential thermal expansion and contraction of the chip and the circuit board, which is discussed at column 1, lines These types of assemblies were previously described in prior art Tessera patents, referenced in the Background of the 007 at column 1, lines As discussed below, however, the ALJ in the 1010 Investigation declined to construe the claims in a manner that would limit them to requiring flexible leads or a layer of compliant material between the dielectric and the chip. As a result, the elements pertaining to the packaged chip recited in the claims challenged in this IPR and the ITC Investigation of the 007 patent cover package designs using a thermal conductor, which were well known in the industry well before August, The Background section of the 007 patent, at column 2, lines 4-20, further references chips used for generating radio frequency (RF) signals, which were known to generate a substantial amount of heat. The patent indicates that it was desired to provide packages that are suitable for use with RF chips using the same production and techniques used with other package designs, such as, for

16 example, the μbga chips, at column 2, lines Thus, the 007 patent purports to improve thermal dissipation by including as part of the chip carrier a large metallic thermal conductor which can be solder-bonded to a circuit board so as to provide enhanced thermal conductivity, as explained in the Abstract and also at column 2, lines When the packaged chip is installed on a circuit panel, the thermal conductor of the chip carrier is soldered to a thermal conductor mounting on the surface of the circuit panel, as explained at column 2, lines This is intended to provide a direct low thermal resistance path for heat flow away from the chip, according to the 007 patent at column 2, lines The patent, however, does not purport to teach a novel thermal conductor nor does it claim a new method for surface mounting semiconductor devices, i.e., connecting the semiconductor chip package to the surface of a circuit panel, as I discuss further below. 28. The 007 patent goes on to describe several different packaged semiconductor chips in reference to Figs Several of these drawings illustrate the packaged chip attached to a circuit board, forming what the patent refers to as an assembly. Thus the 007 patent draws a distinction between an assembly and a packaged chip. The packaged chip or packaged semiconductor chip is the die attached to a chip carrier substrate (and then typically encapsulated). The

17 assembly is the combination of the packaged chip mounted to a circuit panel, as explained, for example, at column 7, lines Fig. 1 is illustrative of the claimed subject matter. According to the 007 patent, Fig. 1 shows a diagrammatic sectional view of a chip assembly, and that the assembly includes a packaged chip 10 mounted to a circuit board 12, as explained at column 7, lines According to the 007 patent at column 7, lines 16-17, the packaged chip 10 includes a chip or die 14 and a chip carrier 16. The chip carrier 16 includes a dielectric layer 18 which desirably is a thin, flexible layer of a polymeric dielectric as, for example, polyimide or BT resin, as explained at column 7, lines The chip carrier has a large metallic thermal conductor 20 in a central region and a plurality of terminals 22 in a peripheral region surrounding the central region, as explained at column 7, lines The 007 patent states, at column 9, lines 48-50, that the packaged semiconductor chip is provided with thin layers of solder 50 on the terminals 22, and with a thin layer of solder 52 on thermal conductor 20. The 007 patent purports to rely on known, conventional soldering techniques, such as the use of solder paste or wave-soldering or dip-soldering techniques to apply the layer of solder 52, and does not teach any new soldering method, as explained at column 9, lines and

18 31. The 007 Patent states that in a surface mount assembly technique, the packaged semiconductor chip is assembled to a circuit board or other circuit panel 12 as shown in FIG. 1. The 007 Patent further states that the terminals are soldered to the contact pads 54 of the circuit board, whereas the thermal conductor 20 is soldered to the thermal conductor mounting 56 of the circuit board. An annotated version of FIG. 1 highlighting some of those elements is as follows: Ex. 1001, Fig. 1 (annotated). 32. As discussed further in the following section, claim 13 is drawn to a packaged chip, and depends from claims 1 and 12. Claim 13 recites the additional limitation of the unitary layer of solder having a substantially uniform thickness of between about 25 µm and 50 µm. Claim 16 recites the same limitation, but as a result of its dependency from claim 11, requires an assembly that includes not only the packaged chip, but also a circuit panel, such that the layer of solder bonds the thermal conductor of the chip package to the thermal

19 conductor mounting of the circuit panel. Independent claim 18 recites a packaged semiconductor chip having features similar to those of claim 1, but also recites a circuit panel having a thermal conductor mounting as in claim 11. Claim 18 does not explicitly require a layer of solder, but instead states that said thermal conductor of said chip carrier being bonded to said thermal conductor mounting of said circuit panel at a spacing of between about 25 µm and 50 µm. 33. The only relevant description of the ranges recited in claims 13, 16 and 18 are in the summary of the invention at column 5, line 64 through column 6, line 7 and in the Detailed Description section at column 9, lines and column 10, lines Column 9, lines states as follows: The packaged semiconductor chip is provided with thin layers of solder 50 on the terminals 22, 22a, and with a thin layer of solder 52 on thermal conductor 20. Such thin layers can be applied by application of a solder paste and subsequent volatilization of the organic carrier from the paste or by wave-soldering or dip-soldering techniques. Desirably, the solder lands are less than about 75 microns thick, most preferably between 25 and 50 microns thick. The solder layers can be applied before severing the tape to form individual packaged chips. 34. Column 10, lines 20-21, simply states that the solder lands used to connect the structure to the circuit board are about µm thick. 35. The summary of the invention citation states that the solder connections can be relatively thin layers of solder, for example, microns thick. Ex. 1001, 6:3-5. The 007 patent states that the connection between the

20 packaged chip and the circuit panel may be a land grid array rather than a ball grid array. As explained below, however, it was known in the art to use thin layers of solder with a land grid array well prior to August, Further, as I explain in greater detail below, the thermal characteristics and mechanical reliability associated with use of a thin solder layer used to mount a packaged chip to a circuit board had been studied extensively, and were well understood in the field significantly prior to August, The 007 patent does not provide any discussion or description suggesting that there was anything unexpected resulting from use of a thin solder layer or a thin spacing between the thermal conductor of the packaged chip and the thermal conductor mounting of the circuit board as claimed in claims 13, 16 and 18. B. Challenged Claims and Applicable Construction 37. Challenged claim 13 depends from challenged claims 1 and 12. These claims recite as follows: 1. A packaged semiconductor chip comprising: (a) a first semiconductor chip having a front face, a rear face, edges bounding said faces and contacts exposed at said front face; and (b) a chip carrier having inner and outer surfaces, the inner surface of said chip carrier facing in an upward direction toward said chip, said chip carrier having a plurality of terminals and a metallic thermal conductor having a unitary solder-wettable area exposed at said outer surface, said unitary solder-wettable area having an area larger than the area of each of said terminals, said thermal conductor being at least partially aligned with said chip, at least some of said terminals being electrically connected to at least some of said contacts of said chip

21 12. A packaged chip as claimed in claim 1, further comprising a unitary layer of solder covering substantially all of said unitary solder wettable area. 13. A packaged chip as claimed in claim 12, wherein said unitary layer of solder has a substantially uniform thickness of between about 25 µm and 50 µm. 38. Challenged claim 16 depends from challenged claims 1 and 11. Claims 11 and 16 recite as follows: 11. An assembly comprising a packaged chip as claimed in claim 1, a circuit panel having contact pads and a thermal conductor mounting, and a unitary layer of solder bonded to said thermal conductor mounting, said chip carrier being disposed on said circuit panel with said outer face of said chip carrier facing downwardly toward said circuit panel, said terminals of said chip carrier being connected to said contact pads o said circuit panel, wherein substantially all of said unitary solder-wettable area of said thermal conductor of said chip carrier is bonded by said unitary layer of solder to said thermal conductor mounting of said circuit panel. 16. An assembly as claimed in claim 11, wherein said unitary layer of solder has a substantially uniform thickness of between about 25 µm and 50 µm. 39. Challenged claim 18 recites as follows: 18. A packaged semiconductor chip comprising: (a) a first semiconductor chip having a front face, a rear face, edges bounding said faces and contacts exposed at said front face; (b) a chip carrier having inner and outer surfaces, the inner surface of said chip carrier facing in an upward direction toward said chip, said chip carrier having a plurality of terminals and a metallic thermal conductor exposed at said outer surface, said thermal conductor having area larger than the area of each of said terminals, said thermal conductor being at least partially aligned with said chip,

22 at least some of said terminals being electrically connected to at least some of said contacts of said chip; and (c) a circuit panel having contact pads and a thermal conductor mounting, said chip carrier being disposed on said circuit panel with said outer face of said chip carrier facing downwardly toward said circuit panel, said terminals of said chip carrier being connected to said contact pads of said circuit panel, said thermal conductor of said chip carrier being bonded to said thermal conductor mounting of said circuit panel at a spacing of between about 25 µm and 50 µm. 40. As reflected above, elements (a) and (b) of claims 1 and 18 are drawn to features of a packaged chip. The elements of claims 11, 12, 13 and 16, are drawn to features of a circuit panel and a layer of solder that bonds the thermal conductor of the packaged chip to the thermal conductor mounting of the circuit panel. The remaining elements (c) of claim 18 are drawn to features of a circuit panel and recite the range of spacing between the thermal conductor of the packaged chip and the thermal conductor mounting of the circuit panel without specifying that there is a layer of solder between the thermal conductors of the package and the circuit panel. 41. Tessera asserted claims 13, 16, and 18 in the ITC Investigation. Certain terms of these claims and the base claims upon which they depend were construed by the ALJ in the ITC Investigation. I applied these constructions in connection with my analysis here. To the extent the Board may adopt a broader construction utilizing the broadest reasonable interpretation standard, the features

23 of the claims would still be found in the prior art discussed below. The claim constructions I applied in my analysis as adopted by the ALJ are as follows: Claim Term chip carrier (claims 1, 11, and 18) unitary solder wettable area (claims 1, 11, and 12) unitary layer of solder (claims 11, 12, 13, and 16) substantially all of said unitary solder-wettable area of said thermal conductor (claims 11, and 12) said unitary layer of solder has a thickness of between about 25 µm and 50 µm (claims 13 and 16) / bonded to said thermal conductor mounting of said circuit panel at a spacing of between about 25 µm and 50 µm (claim 18) at least partially aligned (claims 1 and 18) Construction a connection component that facilitates handling of the chip during manufacture of and mounting of the chip on an external substrate such as a circuit board or other circuit panel a single, continuous solder-wettable area a single continuous layer of solder largely, but not wholly, all of said unitary solder-wettable area of said thermal conductor plain and ordinary meaning aligned to a degree, not completely 42. In the ITC Investigation, I testified that the term about should add no more than 10% of the range of thickness values to each boundary. In my opinion, the difference in the claimed range is (50 25) = 25 µm, so that 10% of the range is 2.5 µm. Thus, 10% of the range translates to a lower limit of 22.5 µm

24 and an upper limit of 52.5 µm. In my opinion, 10% of the total range (added to both limits) is an appropriate meaning of about. This interpretation increases the overall claimed range by 20% percent (10% at each of the lower and upper extremes). Patent Owner and its expert, Dr. Kohl, disagreed with my understanding of the term about, and maintained that there was no hard upper limit for the about 25 µm and 50 µm limitation. 43. In the ITC Investigation, I also testified that the term of in the phrase of between about means that variations in the thickness within the about 25 µm and 50 µm limitation cannot exceed 5 μm. Again, Tessera and its expert, Dr. Kohl, disagreed with my opinion. 44. I maintain that my opinions as to the proper understanding of the terms about and of in the 007 patent claims are correct. However, I do not believe that any differences in my understanding of the claim terms and the broader constructions advocated by Tessera affect my analysis of the prior art as set forth below. Specifically, I believe that a person of ordinary skill would have found it obvious to apply a thin solder layer falling within the claimed range, and would also have found it obvious to apply a more uniform thickness of solder as I believe is required by the claims

25 C. Prosecution History 45. I understand that the prosecution history of a patent is the written record of the examination of the application that leads to a patent. My understanding of the prosecution of the application leading to the 007 patent is as follows. 46. The application leading to the 007 patent was initially filed with 75 claims, but the Patent Owner elected to only have application claims 1-10 and 19 examined. I understand that the patent examiner rejected application claims 1-3, 6, 7, 9, 10 and 19 as being anticipated by U.S. Patent No. 5,869,887 to Urushima, and rejected claims 4, 5, and 8 as being obvious over Urushima in view of U.S. Patent No. 5,285,352 to Pastore, et al., Ex In response to the examiner s rejection, the Patent Owner amended application claim 1 to recite that the metallic thermal conductor has a unitarysolder wettable area, amended application claim 19 (which issued as claim 11), and added new claims (which issued as claims 12-18). See Ex (Response dated 8/12/2004). Claims 77, 80, and 82 added the solder thickness and spacing limitations found in patent claims 13, 16 and Patent Owner argued that Urushima and Pastore merely show packages in which the thermally conductive element can only be mounted to a circuit board by way of solder balls. Id., 19. Patent Owner argued that Solder

26 ball mounting results in limited cross-sectional area of thermal communication between the thermal conductor and the circuit board. Id. 49. The patent examiner allowed application claims 1-10, 19, 76-80, stating as his reason for allowance that none of the reference of record teaches or suggests the claimed HIGH-FREQUENCY CHIP PACKAGES having the limitations: [ ] A unitary solder-wettable area exposed at said outer surface, said unitary solder-wettable area having an area larger than the said terminals, [ ] and all other limitations as recited in claim 1. Ex. 1005, p. 2. As to claim 82 (which issued as claim 18), the examiner referred to the spacing limitation in his reason for allowance. Id., p After the patent examiner s initial rejection, Patent Owner submitted an Information Disclosure Statement on July 26, 2004, which listed 7 references. Ex One of the listed references was U.S. Patent No. 6,521,987 to Glenn et al. Ex The Glenn patent was assigned to Amkor, and it is my understanding that Tessera has contended that it is cumulative of references describing the Amkor MLF product, which is described in the Amkor Application Notes I rely on below. While I understand that the patent examiner indicated he considered this reference by including an initialed copy of the form listing the Glenn patent along with the Notice of Allowance, there is no indication that the patent examiner specifically reviewed the Glenn reference or appreciated its

27 relevance as to the features of the packaged chip recited in claims 1 and 18. Further, there is no indication that the examiner considered any evidence showing that the solder dimensions and spacing recited in the challenged claims reflected well-known design parameters, as I discuss further below. V. Detailed Analysis of the Applicable Level of Skill and Prior Art 51. Below, I provide my analysis of the prior art relative to the challenged claims of the 007 patent. A. General Technical Background 1. Interconnections and Package Types 52. The 007 patent relates to packaging microelectronic elements such as semiconductor chips. Ex. 1001, 1: A semiconductor chip commonly is an integrated circuit (IC) that performs logic (i.e. calculations), memory and other functions. Most ICs are fabricated on large silicon wafers in batch form. A silicon wafer can contain hundreds or even thousands of individual ICs or dies. The silicon wafer is singulated into individual silicon ICs after the fabrication process is complete. Each IC or unpackaged die has many electrical contacts on the front surface. The electrical contacts on the die are metal pads used to provide (i) direct current (DC) for powering the IC and (ii) input and output (I/O) signals. 53. After the individual IC or die is fabricated, it is packaged so that it can be assembled together with other ICs to form an electrical system. This is often

28 accomplished by mounting the packaged chips onto a circuit board, which is part of a product, such as a phone or a computer. 54. The bare IC is too fragile and the metal contacts are too small to directly mount on the circuit panel. The role of the electronic package is to (i) provide electrical pathways between the IC and circuit panel (DC power and high frequency signal), (ii) mechanically protect the delicate silicon IC, (iii) chemically protect the IC for external threats, and (iv) provide an efficient thermal pathway for cooling the IC. The electronic package generally contains a physical structure which carries the IC (i.e. chip carrier). The chip carrier also provides the supporting structure for electrical wires within the package. As recognized in the Area Array Packaging Handbook, The ideal electronic package is an economical and manufacturable electromechanical platform for one or more electronic devices that affords protection, facilitates handling, and provides the geometric translations and compatible interface required for connection to the next system level by practical assembly processes. Ex. 1008, The connection within a packaged chip between the contact pads of the bare die and terminals on a chip carrier is often referred to as the first-level connection. By August, 2001, there were two fundamental methods of connection to chip pads. Id., 1.5. The pads of the chip were either connected directly by a miniature solder bump or by a fine wire, known as wire bonding. Id

29 The disclosed embodiments of the 007 patent generally utilize wire bonds for the first-level connection. 56. The connection between the packaged chip and a circuit board is commonly referred to as the second-level connection. An early type of second level connection was a pin grid array, in which pins on the package were inserted into plated through holes in a circuit board. However, with increases in density number of connections, other second level connections were developed by August, 2001 to permit connection of leadless chip scale packages by soldering the package to the board. Ball grid array (BGA) packages utilize solder balls as contacts between the packaged chip and the circuit board. Land grid arrays or LGA packages (referenced as prior art in the 007 patent) use flat contacts which are soldered directly to the circuit board. 57. The 007 patent is particularly concerned with packaging for RF chips, which typically generate substantial amounts of heat. Ex. 1001, 2:9-10. As set forth below, by August 2001, the industry had developed various LGA package designs that were particularly suited for transferring heat from such chips to the underlying circuit board by way of a larger metal pad designed to be soldered to a corresponding thermal conductor pad or land on the circuit board. Examples of such packages include quad flat no-lead or QFN packages

30 58. QFNs were developed several years prior to the 007 patent. A QFN is a chip scale package (CSP) that has surface dimensions close to the dimensions of the chip contained in the package. A QFN has terminals formed along the perimeter of the package and an exposed solder-wettable thermal pad formed in the center. The terminals and pad are coplanar and formed from a leadframe. The terminals and thermal pad are configured to be soldered to a printed circuit board. The solder connections (solder joints) form electrical and mechanical connections between the package and the board, as well as thermal paths to facilitate heat transfer from the chip to the board. 59. As I discuss further below, the terminals of QFN packages located on the periphery of the package included solder-wettable metal surfaces on the bottom surface facing the circuit board, as well as metal surfaces running up the sides of the package. Such side portions of the perimeter terminals on leadless packages have historically been known as castellations. When solder was applied to the terminals, the solder would adhere not only to the bottom surface of the terminals (heel of solder joint), but also would run up the side, forming a toe solder fillet. This configuration is shown and described in the literature, for example, in Jean- Paul Clech, Solder Reliability Solutions: A PC-Based Design-for-Reliability, ESPI (Sept. 1996) (Ex. 1009) ( Clech ). The figure below is taken from Ex at p

31 60. As Clech indicates, the castellated packages shown above have low stand-off height (h 1 ) and toe solder fillets that run up the castellations. The inclusion of the toe portion of the solder fillet reduces strain in the solder joint and permits a thinner solder thickness in the heel region between the bottom of the package and the circuit board (h 1 ). Clech explains in the table on page 7 that the thickness (h 1 ) of the parts he considered was 1.4 mil or 1.6 mil, which is around 35 µm 41 µm, and within the claimed range of the 007 patent. 61. Similarly, the 1998 paper Solder Joint Reliability of a Lead-Less RFtransistor authored by Gunnar Gustafsson, (Ex. 1010) shows in column 1 of page 88 and in Figure 2 a solder layer of thickness 40 µm in the heel region underneath the component, and a significant toe solder fillet on the side of the leadless RFtransistor:

32 Gustafsson further shows that it was known to use thin solder layers, with thickness values within the claimed range of the 007 patent, particularly for packages having a heel and toe solder fillet. 62. Yet another publication indicates that the use of a thin solder layer with a land grid array as disclosed in the 007 patent was known in the prior art. Specifically, LGA vs. BGA: What is more reliable? A 2nd Level Reliability Comparison, authored by Ahmer Syed and Robert Darveaux ( Syed ) (Ex. 1019), was published on September 24, Syed discusses reliability as to Land Grid Array (LGA) packages that employed solder joints in the 2 to 3 mils or 50.8 to 76.2 µm range (Ex. 1019, p. 1), which is near the about 25 µm to 50 µm range claimed in the 007 patent. 63. I note that each of the Clech, Gustafsson, and Syed papers was published well prior to the filing date of the 007 patent, and were accessible to those of ordinary skill in the art. I confirmed that Clech (Ex. 1009) was published

33 on September 10, 1996 at the Surface Mount International Conference, and made available through the SMTA Knowledgebase website. I have also confirmed that Gustafsson (Ex. 1010) was published in 1998 in the Proceedings of the 48th Electronic Components and Technology Conference (Cat. No.98 CH 36206), available through the IEEE-EXPLORE website. I also have confirmed that Syed (Ex. 1019) was published in September, 2000 in the Proceedings of the Surface Mount Technology Association (SMTA) International Conference, available through the SMTA website. 2. Known Soldering Techniques 64. As of August 2001, solder was widely used to form an electrical and mechanical connection between a packaged chip and a circuit board, and to facilitate heat transfer. Solder is generally understood to be a fusible alloy with a liquidus temperature below 400ºC. Ex. 1008, As of August 2001, solder was made in various physical forms, including bars, ingots, wire, powder, preform, balls, and paste. Id. Generally, solder is applied to a solder-wettable surface that contains material to which the solder material will adhere to and form chemical bonds in the form of intermetallic compounds. 65. As of August 2001, the industry commonly used tin-lead solder. Solder-wettable terminals and lands to which solder was applied were generally made of copper, which forms intermetallic compounds with the tin-lead material

34 during the soldering process. The material properties of various types of tin-lead solder were well known and understood as of that time. 66. As acknowledged in the 007 patent, there were various known techniques for applying solder to a component. As set forth above, the 007 patent refers to three known techniques: (1) wave-soldering; (2) dip-soldering; and (3) application of a solder paste. 67. Wave soldering is a bulk soldering process, primarily used for mounting through-hole components to a circuit board. The components are attached to the board, and then the board is passed over a container of molten solder that is agitated to produce an upswell that looks like a wave. As the board makes contact with the wave, the solder adheres to solder-wettable surfaces and solders the components to the board. 68. Dip soldering is a small scale process in which a circuit board with mounted components is dipped into a tank of molten solder. The molten solder adheres to the solder-wettable surfaces on the assembly. 69. Solder paste reflow processes were commonly used for surface mount devices, such as QFNs and other land grid array packages. Solder paste includes metallic material (e.g., tin and lead) in powder form (spherical particles) that is suspended in a viscous medium referred to as flux. Flux acts as a temporary adhesive that holds the components until the soldering process melts the metal

35 particles, and forms solder joints that include intermetallic compounds. The flux may also remove oxidation from the surfaces of the components being soldered. 70. One technique well known prior to 2001 was to screen print solder paste onto a circuit board using a stencil containing apertures corresponding to the solder-wettable lands and terminals on the circuit board. After application of the solder paste, components are placed onto the circuit board. The assembly is then heated in a reflow process, in which the flux volatizes and the remaining metal particles react and bind with the solder-wettable surfaces on the components and circuit board, thereby forming solder joints. 3. Understanding Within The Art Of The Effect of Solder Thickness 71. As discussed above, claims 13 and 16 require what the 007 patent characterizes as a thin layer of solder between the thermal conductors of the packaged chip and the circuit board of between about 25 µm and 50 µm. While claim 18 does not require a solder layer, it states that the spacing between the thermal conductors is between about 25 µm and 50 µm. Accordingly, this element of claim 18 would read on assemblies where the thermal conductors of the package and the board are separated by a layer of solder falling within the claimed range. 72. Well prior to 2001, the effect of solder thickness on heat transfer within an electronics assembly was well known and understood. Specifically, it

36 was recognized that a thinner layer of solder reduced thermal resistance between the chip and the circuit board, and was desirable for at least that reason. 73. For example, Luo and Chung, Effect of the Thickness of a Thermal Interface Material (Solder) on Heat Transfer Between Copper Surfaces, Vol. 24(2), International Journal of Microcircuits and Electronic Packaging, pp , (2 nd Q 2001) ( Luo ) (Ex. 1011) notes that Heat dissipation, is a critical problem that limits the reliability, performance and further miniaturization of microelectronics. Ex. 1011, 1. This publication studies and reports the effects of solder thickness from 10 to 30 µm on heat transfer between two copper surfaces. Id., 2. Luo concluded that Increasing the solder thickness from 10 to 30 µm caused a 25% increase in the thermal rise time (t 0.5 ), although the thermal contact conductance of each copper-solder interface was not affected. 74. I note that in the ITC Investigation, Tessera has disputed that Luo is prior art, even though it was published by the International Microelectronics and Packaging Society (IMAPS), and was publicly accessible to those of ordinary skill by the second quarter of 2001 (i.e., by June 2001). I have confirmed that Luo was published at this time as a printed journal distributed to subscribers and libraries, as well as at the IMAPS website at with the name q2 (quarter 2)

37 75. While denying that Luo is prior art, Patent Owner s expert in the ITC Investigation, Dr. Kohl, admitted that increasing the solder thickness results in slower heat transfer, and that this would already have been known by a person of ordinary skill in the art because the person of ordinary skill would know that the shorter the distance, the lower the resistance, keeping all other factors the same. 76. This understanding, that decreasing solder thickness decreases thermal resistance, can be understood mathematically by the following equation: R th l A In this relation, the thermal resistance R th is directly proportional to the length l of the thermal path (and inversely proportional to the contact area A of the connection and the thermal conductivity λ of the solder material). Thus, the thermal resistance can be minimized by reducing the length of the thermal path or by increasing the area of the contact pad. This fundamental relationship would have been well known and understood by a person of ordinary skill in the art in In addition to reducing thermal resistance and thereby improving heat dissipation, another reason that a thinner solder layer was known to be desirable relates to the economics of mass production of microelectronic packages. At a large scale, conservation of materials provides an economic benefit. In choosing a

38 solder thickness for mounting a packaged chip to a board, a person of ordinary skill would be highly motivated to use the least amount of solder necessary. 78. In the ITC Investigation, Tessera has asserted that it would not have been obvious to use a thinner solder thickness as claimed, because it was understood by a person of ordinary skill in the art that, as a general matter, decreasing solder thickness can reduce mechanical reliability. In this regard, I testified as follows: In well-made electronic assemblies, thicker layers of solder are generally more reliable than thinner layers, particularly for larger packages, as they reduce and better distribute solder joint shear strains caused by mismatches in the thermal expansions of the electronic component and the printed circuit board. Based on this testimony, I understand that Patent Owner has argued that there would not be a motivation to use a thin solder layer as claimed. In my view, Patent Owner has misunderstood the relevance of my testimony and overlooked other design factors known to a person of ordinary skill in the art (e.g. heat transfer enhancement and economic savings, as discussed above). 79. First, I am not aware of any evidence that prior to August, 2001, there was a general understanding that a solder thickness of less than about 50 µm would be unreliable such that a particular assembly would be unfit for use. It should be understood that mechanical reliability was (and is) generally assessed based on cycles to failure, measured by repeatedly heating and cooling an assembly until a

39 failure in the assembly occurs. While as a general matter a thicker solder joint might increase number of cycles to failure, a thinner solder joint would still function. Depending on the application, other design considerations, such as thermal dissipation and material costs (as I discussed above), would have led a designer to choosing a thinner solder thickness. 80. Second, concerns over strain resulting from a thinner solder thickness were addressed by other design considerations, such as the shape of the solder joint. As I have discussed above, Clech (Ex. 1009) and Gustafsson (Ex. 1010) provided prior art examples of assemblies using a heel and toe solder fillet, which permitted a reliable thinner solder layer between the bottom surface of the package and the circuit board that fell within the claimed range of the 007 patent. Syed (Ex. 1019) provided another prior art example of a thin solder layer in an LGA package that was within the claimed range of the 007 patent. 81. Third, it was understood that reliability concerns resulting from thinner solder joint thicknesses were not significant with smaller sized packages. In particular, well prior to 2001, it was generally understood that mechanical reliability issues typically resulted from differences between the coefficients of thermal expansion (CTE) of the package and the board, which caused those components to expand at different rates when heated. This so-called CTE mismatch can lead to solder fatigue. See, e.g., Ex. 1009, p. 1 ( Cycle thermal

40 stress conditions in surface mount assemblies leads to solder fatigue. ). This understanding resulted from various studies that analyzed the factors affecting solder joint reliability in different packages. 82. It was well understood that the shear strain at a particular point within the solder joint was typically proportional to the distance from the neutral point (DNP) (i.e, the distance from the center of the package). It was also understood that shear strain was inversely proportional to the height of the solder joint. This understanding is reflected in the following mathematical expression (DNP formula), which shows the shear strain Δε shear in the solder joint as follows: shear ( )(a / C H) T S where a = DNP is the in-plane distance from the solder joint to the center of the package, α c is the coefficient of thermal expansion of the chip carrier, α s is the coefficient of thermal expansion of the circuit board, H is the height of the solder joint or layer, and ΔT is the change in temperature. See Hall et al., Thermal Deformations Observed in Leadless Ceramic Chip Carriers Surface Mounted to Printed Wiring Boards, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol. CHMT-6, No. 4 (Dec. 1983) ( Hall ) (Ex. 1012). Thus, strain increases in the solder joints as they become more distant from the center of the assembly (the DNP increases)

41 83. Because it was well known that strain increases with the distance from the neutral point, it was also understood that smaller packages with a smaller footprint (i.e., less distance from the neutral point to the sides of the package) would undergo smaller solder joint shear strains, thereby permitting use of thinner solder joints with sufficient reliability. 84. In other words, it was understood that for solder joints further from center of an electronic package, the CTE mismatch between the board and package would lead to greater strains. Conversely, it was understood that if the package was smaller, there would be correspondingly lower strains resulting from the same CTE mismatch. 85. I note that the 007 patent does not provide any analysis or discussion as to how any degradation in mechanical reliability associated with use of a thinner solder joint can be avoided. I understand that the named inventor of the 007 patent, Mr. Michael Warner, suggested a reliable assembly using a thinner solder layer could be achieved by using a compliant layer as disclosed in the 007 patent or a smaller package. However, nothing in the challenged claims limits the package in this way. 86. In summary, the impact of solder joint thickness was a well-known and understood parameter in mounting packaged chips to a circuit board. Use of a thinner solder layer or spacing as reflected in claims 13, 16 and 18 is found in the

42 prior art and would have been obvious to a person of ordinary skill, taking into account design objectives such as thermal heat transfer, cost, and mechanical reliability. Nothing in the 007 patent or elsewhere suggests that that the claimed solder thickness and spacing provides any unexpected results. 4. Desirability of a Uniform Solder Joint 87. Claims 11 and 12 recite a unitary layer of solder. As set forth above, this term has been construed as a single, continuous layer of solder. 88. As I have discussed above, it was well recognized in the art that the contact area of the solder layer is inversely proportional to thermal resistance. Accordingly, a person of ordinary skill in the art understood that for packages designed to promote thermal transfer from the chip to the circuit board, it would have been obvious to increase the effective area of the solder layer by making it a single continuous layer so as to decrease its thermal resistance. 89. As reflected in the Amkor MLF Application Notes (Ex. 1015), which I discuss in detail in the following section, it was understood in the art that in assemblies in which the packaged chip had a relatively large thermal mounting or pad, it was found that a large, single layer of solder was susceptible to voids being formed in the solder layer as a result of out-gassing when the volatile components of the solder paste underwent heating during reflow. Thus, in certain applications, it was known to use apertures and/or masks to effectively divide the solder layer

43 into separate sections to permit outgassing. However, such apertures and masks were understood to be unnecessary for smaller sized packages. Thus, use of a unitary layer of solder was understood to be desirable, but was not employed in certain applications where the large area of the solder layer may result in undesirable out-gassing during reflow. In other words, use of a unitary layer of solder was a recognized design choice. B. Amkor MLF 90. The MLF Application Notes bear a date of March, Ex. 1015, p. 1. As reflected in Exhibit 1016, a printout from the Internet Archive s Wayback Machine indicates that the MLF Application Notes were publicly accessible to persons of ordinary skill through Amkor s website at least as early as April, The MLF Application Notes provide guidelines for soldering Amkor s MLF products to a PCB. I note that those products were described in several publications prior to the August 2001 filing date of the 007 patent. For example, Exhibit 1013 is a product announcement dated February, 1999 describing relevant features of the product. Exhibit 1014 is a data sheet dated June, Further, features of the Amkor MLF are described in the Glenn patent, which was October 31, 2000, and claims priority to a prior application filed October 21, Ex

44 92. Based on my experience and knowledge of the industry, it was commonplace for chip manufacturer s to make soldering guidelines publicly available to its customers without restrictions on use. Consistent with this understanding, the Amkor MLF Application Notes were cited by a third party, Micron, to the U.S. Patent & Trademark Office in an Information Disclosure Statement submitted in June 2000, prior to the August 2001 filing date of the 007 patent. Ex In the ITC Investigation, Patent Owner did not contest that the Amkor MLF included all features of the packaged chip as recited in claims 1, 11, 12 and 18 of the 007 patent. Patent Owner, however, disputed that the features relating to the circuit board, the solder thickness and spacing of the dependent claims were taught by the MLF Application Notes. I address Patent Owner s contentions as to the teachings of the MLF Application Notes below. 1. The MLF Application Notes Describe All Features of Independent Claim 1 (1) Claim 1 preamble: A packaged semiconductor chip comprising. 94. The MLF Application Notes describe the Amkor MLF package, which is a packaged semiconductor chip, as shown in Figure 1 (Ex. 1015, p. 3), annotated as follows:

45 (2) Claim 1, element (a): a first semiconductor chip having a front face, a rear face, edges bounding said faces and contacts exposed at said front face 95. The MLF Application Notes indicate that the MLF package includes a first semiconductor chip having a front face, a rear face, edges bounding those faces and contacts exposed at the front face as annotated below. The first semiconductor chip is the die. The die has a front face, a rear face, edges bounding those faces, and contacts exposed at the front face as shown below: (3) Claim 1, element (b): a chip carrier having inner and outer surfaces, the inner surface of said chip carrier facing in an upward direction toward said chip, said chip carrier having a plurality of terminals and a metallic thermal conductor having a unitary solder-wettable area exposed at said outer surface, said unitary solder

46 wettable area having an area larger than the area of each of said terminals, said thermal conductor being at least partially aligned with said chip, at least some of said terminals being electrically connected to at least some of said contacts of said chip. 96. The MLF Application Notes show that all elements of feature (b) are found in the MLF package. These include a chip carrier having inner and outer surfaces, the inner surface of the chip carrier facing in an upward direction toward the chip, the chip carrier having a plurality of terminals and a metallic thermal conductor having a unitary solder-wettable area exposed at the outer surface, the unitary solder-wettable area having an area larger than the area of each of the terminals, the thermal conductor being at least partially aligned with the chip, at least some of the terminals being electrically connected to at least some of the contacts of the chip. The annotations of Figure 1 shown these elements of the claim as follows:

47 97. As previously noted, chip carrier was construed to mean a connection component that facilitates handling of the chip during manufacture of and mounting of the chip on an external substrate such as a circuit board or other circuit panel. The copper leadframe substrate with the central exposed die paddle (thermal conductor) and perimeter terminals satisfies the construction. The copper leadframe substrate is a connection component that facilitates handling of the semiconductor die during manufacture of and mounting of the semiconductor die on the printed circuit board. 98. The plurality of terminals is the group of lands (also called bond pads or terminals) on the bottom surface of the package shown in Figures 1 and 2. The metallic thermal conductor is the central exposed die paddle shown in Figures 1 and 2. As shown in Figure 1, the copper leadframe substrate with the exposed die paddle has inner and outer surfaces, and the inner surface faces in an upward direction toward the semiconductor die. As shown in Figures 1 and 2, the lands are on the leadframe substrate and the carrier includes the die attach paddle. 99. Unitary solder wettable area was construed to mean a single, continuous solder-wettable area. The central copper die paddle (thermal conductor) of the MLF package has a bottom exposed surface that is single and continuous. Because it is made of copper with a solder plating finish on its exposed surface, it is solder wettable. The solder plating on the thermal conductor

48 is clearly labeled on Figure 1 as a blue layer on the bottom of the central die paddle. As also shown in Figure 1, the unitary solder-wettable area of the die attach paddle has an area that is clearly larger than the area of each of the perimeter lands (terminals) The central die paddle (thermal conductor) is fully aligned with the semiconductor die, and therefore meets the limitation that the thermal conductor be at least partially aligned with the semiconductor chip The MLF Application Notes state on page 3 that the exposed die attach paddle on the bottom efficiently conducts heat to the PCB and provides a stable ground through down bonds or electrical connections through conductive die attach material. The die paddle is therefore a thermal conductor As shown in the cross-sectional view in Figure 1, gold wires electrically connect at least some of the terminals formed on the leadframe with the contacts of the chip. 2. The MLF Application Notes Describe All Features of Dependent Claim Claim 12 depends from claim 1, which I have addressed in the preceding section. It additionally recites a unitary layer of solder covering substantially all of said unitary solder wettable area

49 104. The MLF Application Notes makes clear that layer of solder is applied to the larger rectangular PCB land pattern shown in Figure 3 (Ex. 1015, p. 4) as shown below: 105. The MLF Application Notes state that the thermal pad provides a solderable surface on the top surface of the PCB (to solder the package die paddle on the board). Ex. 1015, p. 8. It further teaches that Normally, the size of the thermal pad should at least match the exposed die paddle size. Id. Both the thermal pad on the PCB and the exposed surface of the die paddle are solder wettable. Therefore, solder applied to the thermal pad would adhere to the entire surface of both the thermal pad and exposed surface of the die paddle during reflow In the ITC Investigation, Patent Owner has disputed that the MLF Application Notes teach an embodiment in which there would be a unitary layer of solder, noting that Section 3.3 and Fig. 11 of the document refers to a solder stencil

50 design for the thermal pad that utilize smaller multiple openings rather than one big opening. Ex. 1015, p. 12. However, other teachings of the MLF Application Notes show that one single opening in the stencil is used to apply solder paste to the thermal land of the PCB, which would result in a single, unitary layer of solder covering substantially all of the die attach paddle. Specifically, the MLF Application Notes disclose the following: 3.2 Stencil Design for Thermal Pad In order to effectively remove the heat from the package and to enhance electrical performance the die paddle needs to be soldered to the PCB thermal pad, preferably with minimum voids. However, eliminating voids may not be possible because of presence of thermal vias and the large size of the thermal pad for larger size packages. Also, out gassing occurs during reflow process which may cause defects (splatter, solder balling) if the solder paste coverage is too big. It is, therefore, recommended that smaller multiple openings in stencil should be used instead of one big opening for printing solder paste on the thermal pad region. This will typically result in 50 to 80% solder paste coverage. As has been discussed before, the thermal performance is not affected significantly even with 50% coverage. Shown in Fig. 11 are some of the ways to achieve these levels of coverage. Ex. 1015, p. 12 ( 3.2 and Fig. 11) (emphasis added)

51 107. Thus, the MLF Application Notes indicate that because of the presence of thermal vias and the large size of the thermal pad for larger size packages, out gassing during reflow may result if the solder paste coverage is too big. Id. The Notes, however, makes clear that there were also smaller MLF packages that did not require this alternative stencil design and instead utilize one big opening. Id In particular, Table 1 of the publication lists the dimensions of various MLF packages and the printed circuit board (PCB) land patterns to which the packages were to be soldered: Ex. 1015, p Table 1 indicates that there were small size packages, such as a 3x3 mm package, as well as larger size packages, such as those referenced in Figure 11 (i.e., the 7x7 and 10x10 mm packages). Table 1 describes land pattern dimensions, including the dimension of the corresponding solder-wettable portion of the PCB to which the thermal conductor of the package is soldered (i.e., the portion of the

52 PCB constituting the claimed thermal conductor mounting ). The dimension of the thermal conductor mounting is defined by the value A max shown in Figure 3 above. Ex. 1015, p As shown in Table 1, the maximum dimension of the thermal conductor mounting for a 3x3 mm package was 2.02 mm. Notably, this value is smaller than the 2.2 mm square sized openings recommended for 7x7 mm packages, as shown in Fig. 11. Thus, the Amkor MLF Application Notes explicitly teach that the solder printing stencils for smaller packages, such as the 3x3 mm package, would have a single opening that is smaller than one of the multiple openings in stencils used for a bigger package, such as the 7x7 mm package. Such a single stencil opening per MLF component approach would necessarily result in a unitary solder layer for that assembled component Based on these teachings, it is apparent that the smaller Amkor MLF packages used a single solder stencil opening that formed a unitary layer of solder. Because the thermal conductor on the package and the corresponding PCB land were both solder-wettable, the resulting solder layer for smaller packages is unitary and covers all of the PCB land and the thermal pad

53 3. The MLF Application Notes Describe All Features of Dependent Claim Claim 13 depends from claims 1 and 12, which I have addressed above. It further recites that the unitary layer of solder has a substantially uniform thickness of between about 25µm and 50 µm With respect to the requirement of a uniform thickness of between about, the MLF Application Notes makes clear that the layer of solder between the thermal pad and the corresponding land on the PCB would be uniform. The document states that the thermal pad provides a solderable surface on the top surface of the PCB (to solder the package die paddle on the board). Ex. 1015, p. 8. It further teaches that Normally, the size of the thermal pad should at least match the exposed die paddle size. Id. Additionally, Figure 4 of the Application Notes show a layer of solder applied between the terminals of the package and the terminal lands of the PCB: 114. Because the terminals and die paddle are formed from the same copper leadframe (as shown in Figure 1, reproduced above), they are coplanar

54 Accordingly, the thickness of the solder layer between the central die paddle and board is nominally the same thickness as the toe portion of the terminal solder fillets. The solder layer between the die pad and the corresponding land on the board therefore has a substantially uniform thickness With regard to the recited range of about 25µm and 50 µm, the MLF Application Notes states that The surface mount experience conducted by Amkor and Xetel showed good perimeter side joints and about 50 to 75 microns standoff height using these stencil designs for the thermal pad. Ex. 1015, p. 12. The lower end of these reported joints falls within the about 50 µm upper limit of claim I understand that in the ITC Investigation, Tessera has disputed that this teaching of the Amkor MLF Notes meets the requirements of claim 13 on two bases, which I address as follows First, Tessera has relied on testimony of a Broadcom witness, who referred to the standoff reported for the distance by which the terminal and pads of a Broadcom QFN extends beyond the plastic encapsulant. This use of the term standoff was entirely different. The witness did not provide testimony as to the MLF Application Notes, nor was he even shown the document when he was questioned. In the context of the MLF Application Notes, standoff height is expressly discussed in reference to the surface mount experience of Amkor and

55 Xetel, and therefore is plainly describing the distance of the solder joint between the package and board in a finished assembly. See Ex. 1015, p 12 (Section 3.2). This distance is the same as the thickness referenced in claims 13 and 16 and the spacing of claim Second, Tessera has argued that the standoff height reported in the Application Notes was specific to the stencil designs shown in Fig. 11, which are for larger sized packages. However, there is nothing in the reference to suggest that the solder joint thickness would be greater for smaller size packages than the µm range disclosed for the larger size packages. In fact, as I explained above, a person of ordinary skill would have recognized that thinner solder joints would be used for smaller sized packages, because such packages would be less susceptible to reliability issues associated with CTE mismatches between the package and the circuit board. I note that the MLF Application Notes expressly describes use of a heel and toe solder fillet for the perimeter connections as shown in Fig. 4 below:

56 Ex. 1015, p 5. In this regard, the document states that the toe fillet, if formed will improve the solder joint reliability. Id. As I have explained above, the use of the heel and toe fillet permits use of a thin solder layer. Thus, even if the teaching of 50 to 75 microns is (incorrectly) understood as being limited to larger size packages, it would have been obvious to one of ordinary skill to use the same or smaller solder thickness with respect to the smaller size packages disclosed in the MLF Application Notes Third, Tessera has argued that the solder joint reported is for the perimeter solder joints, not the joint between the die pad and the thermal land on the printed circuit board. However, as I have explained above, the perimeter terminals and the die pad on the package are coplanar in the Amkor MLF package, as are the terminal and thermal pad lands on the circuit board. As a result, the designed solder joint thickness at the perimeter terminals and at the center die paddle (thermal conductor) is the same As I indicated previously, I believe that claim 13 requires that there would be no more than a 5 micron variation in the thickness of the solder layer between the thermal conductor of the package and the thermal conductor mounting of the circuit board. While this uniformity is not expressly taught in the MLF Application Notes, the surfaces of the die pad of the MLF package and the corresponding thermal pad on the circuit board are both planar. See Ex. 1015, p

57 It would have been a design goal to solder the MLF package in a manner that would maintain uniformity of the solder layer. Accordingly, this additional feature of the claim would have been obvious For at least these reasons, all features of claim 13 and base claims 1 and 12 are disclosed and/or suggested by the Amkor MLF Application Notes. 4. The MLF Application Notes Describe All Features of Dependent Claim Claim 11 depends from claim 1, which I have addressed above. It additionally recites: (i) a circuit panel having contact pads and a thermal conductor mounting; (ii) unitary layer of solder bonded to the thermal conductor mounting; (iii) the chip carrier being disposed on the circuit panel with the outer face of the chip carrier facing downwardly to the circuit panel; (iv) substantially all of the unitary solder-wettable area of the thermal conductor of the chip carrier is bonded by the unitary layer of solder to the thermal conductor mounting of the circuit panel. Each of these elements is disclosed by the MLF Application Notes With respect to element (i), as set forth above, the MLF Application Notes shows a PCB with perimeter pads and a thermal pad. E.g., Ex. 1015, p. 4 (Section 2.1) and p. 6 (Section 2.2) With respect to element (ii), as discussed with respect to claim 12, the MLF Application Notes describe a unitary layer of solder that is applied to the thermal pad

58 125. With respect to element (iii), the MLF Application Notes make clear that the downwardly facing side of the MLF package is disposed on the PCB. E.g., Ex. 1015, p With respect to element (iv), as discussed above with respect to claim 12, the MLF Application Notes discloses that substantially all of the unitary solder-wettable area of the thermal conductor of the chip carrier is bonded by the unitary layer of solder to the thermal conductor mounting of the circuit panel. 5. The MLF Application Notes Describe All Features of Dependent Claim Claim 16 depends from claims 1 and 11, which I have addressed above. It further recites the same features as claim 13, which are taught by the MLF Application Notes as I have addressed above. 6. The MLF Application Notes Describe All Features of Independent Claim Independent claim 18 recites (a) a semiconductor chip and (b) a chip carrier having the same features as recited in claim 1. These features are disclosed in the MLF Application Notes for the same reasons I have addressed in reference to claim Claim 18 further recites (c) (i) a circuit panel having contact pads and a thermal conductor mounting, the chip carrier being disposed on the circuit panel with the outer face of the chip carrier facing downwardly toward the circuit panel,

59 the terminals of the chip carrier being connected to the contact pads of the circuit panel, and (ii) the thermal conductor of the chip carrier being bonded to the thermal conductor mounting of the circuit panel at a spacing of between about 25 µm and 50 µm Features (c)(i) of the circuit panel are the same as those of the circuit panel recited in claim 11, except that claim 18 does not require a layer of solder. These features of claim 18 are disclosed in the MLF Application Notes for the same reasons I have set forth as to claim Feature (c)(ii) of the circuit panel recites the same about 25 µm and 50 µm spacing as the thickness set forth in claims 13 and 16, but is broader in that it does not require a layer of solder for the bond between the thermal conductors of the carrier and the circuit board. This spacing is disclosed and suggested by the MLF Application Notes for the same reasons as claims 13 and 16, as set forth above. C. Sharma 132. U.S. Patent No. 6,420,779 to Sharma et al., titled Leadframe Based Chip Scale Package and Method of Producing the Same (Ex. 1018) was issued from an application filed September 14, 1999, i.e., almost two years prior to the 007 patent. Sharma describes a QFN package that includes all of the features of the packaged chips recited in the challenged claims. Sharma anticipates claim 1,

60 and the subject matter of claims 11, 12, 13, 16 and 18 would have been obvious in light of Sharma s teachings as understood by a person of ordinary skill, as evidenced by the prior mentioned papers by Luo, Clech, Gustafsson, and Syed Specifically, Sharma discloses a leadframe including leads (perimeter terminals) 130 and 140 and a die pad (thermal conductor) 120 on which is placed an integrated circuit chip 110, which is a semiconductor chip, as shown in Figure 1 reproduced below Sharma teaches that the die pad 120 has an exposed bottom surface 122 that is coplanar with the bottom of the package. Ex. 1018, 3:8-20. The exposed bottom surface 122 of the die pad 120 is plated with a conductive material such as silver solder or palladium, which is a metallic thermal conductor, to facilitate mounting the device to a printed circuit board (PCB). Id. at 4:64 5:4; 5: Sharma explains that exposing the die pad 120 at the bottom of the package allows the die pad 120 to be soldered to the PCB to provide an

61 improvement in thermal, electrical, and mechanical reliability. Id. at 3: Sharma also discloses the claimed unitary layer of solder, which is the layer of solder between the die pad 120 and the PCB. Id. Sharma teaches that the goal is to have a smaller size package. Id. at 1:11-20; 3: Sharma Describe All Features of Independent Claim With respect to element (a) of claim 1, Sharma discloses a packaged semiconductor chip, which is the device 100. Id. at Fig. 1. The first semiconductor chip in Sharma is the integrated circuit chip 110, which has a front face and edges, and a rear face that is facing the die pad 120. Id. The contacts exposed on the front face of the integrated circuit chip 110 are the contacts on the integrated circuit chip 110 that are connected to the wires 170 and 180 as shown in Figures 1 and 2 of Sharma. Id. at Figs. 1 and 2. Annotated versions of Figs. 1 and 11 of Sharma showing items from element (a) of claim 1 are shown below:

62 137. As to element (b), the chip carrier in Sharma is the leadframe including the die pad 120 and leads 130 and 140. Id. at Fig. 1. The plurality of terminals in Sharma are the leads 130 and 140, which extend to the perimeter of the package as shown, for example, in Fig. 11. Id. The metallic thermal conductor in Sharma is the die pad 120, whose exposed bottom surface 122 is plated with conductive material, such as silver solder or palladium, to facilitate mounting the device to a printed circuit board (PCB). Id. at Fig. 1; 4:64-5:4; 5: The leadframe including the die pad 120 in Sharma has inner and outer surfaces as shown in Figure 1. Id. at Fig. 1. The inner surface in Sharma faces in an upward direction toward the integrated circuit chip 110 as shown in Figure 1. Id. An annotated version of Fig. 1 of Sharma showing items from element (b) of claim 1 is shown below:

63 138. As shown in Figures 1 and 11 of Sharma, the unitary solder-wettable area of the conductive material plated on the exposed bottom surface 122 of the die pad 120 has an area larger than the area of each of the leads 130 and 140. Id. at Figs. 1 and 11. The conductive material plated on the exposed bottom surface 122 of the die pad 120 is fully aligned with the integrated circuit chip 110 in Sharma, and at least some of the leads 130 and 140 are electrically connected to at least some of the contacts of the integrated circuit chip as shown by the wires 170 and 180 in Figures 1 and 2 of Sharma. Id. at Figs. 1 and In the ITC Investigation, Patent Owner did not dispute that all elements of claim 1 are disclosed by Sharma. 2. It Would Have Been Obvious to Apply a Unitary Solder Layer to Sharma s QFN Package As Recited In Dependent Claim Claim 12 depends from claim 1. I have addressed the elements of claim 1 above