FEATRES 3MHz Gain Bandwidth V/µs Slew Rate 5µA Supply Current Available in Tiny MSOP Package C-Load TM Op Amp Drives All Capacitive Loads nity-gain Stable Power Saving Shutdown Feature Maximum Input Offset Voltage: 6µV Maximum Input Bias Current: 5nA Maximum Input Offset Current: 5nA Minimum DC Gain, R L = k: 3V/mV Input Noise Voltage: nv/ Hz Settling Time to.%, V Step: 7ns Settling Time to.%, V Step:.5µs Minimum Output Swing into k: ±3V Minimum Output Swing into 5Ω: ±3.V Specified at ±.5V, ±5V and ±5V APPLICATIONS Battery-Powered Systems Wideband Amplifiers Buffers Active Filters Data Acquisition Systems Photodiode Amplifiers TYPICAL APPLICATION Instrumentation Amplifier 5µA, 3MHz, V/µs Operational Amplifier DESCRIPTION The LT 35 is a low power, high speed, high slew rate operational amplifier with outstanding AC and DC performance. The features lower supply current, lower input offset voltage, lower input bias current and higher DC gain than devices with comparable bandwidth. The circuit combines the slewing performance of a current feedback amplifier in a true operational amplifier with matched high impedance inputs. The high slew rate ensures that the large-signal bandwidth is not degraded. The amplifier is a single gain stage with outstanding settling characteristics which make the circuit an ideal choice for data acquisition systems. The output drives a kω load to ±3V with ±5V supplies and a 5Ω load to ±3.V on ±5V supplies. The amplifier is also stable with any capacitive load which makes it useful in buffer or cable driver applications. The is a member of a family of fast, high performance amplifiers using this unique topology and employing Linear Technology Corporation s advanced complementary bipolar processing. For dual and quad amplifier versions of the see the LT35/LT353 data sheet. For higher bandwidth devices with higher supply current see the LT35 through LT365 data sheets. Singles, duals and quads of each amplifier are available., LTC and LT are registered trademarks of Linear Technology Corporation. C-Load is a trademark of Linear Technology Corporation. Large-Signal Response R 5k R 5k R5.k R 5k V IN + R3 5k + + GAIN = [R/R3][ + (/)(R/R + R3/R) + (R + R3)/R5] = TRIM R5 FOR GAIN TRIM R FOR COMMON MODE REJECTION BW = 3kHz V OT 35 TA 35 TA
ABSOLTE MAXIMM RATINGS W W W Total Supply Voltage (V + to V )... 36V Differential Input Voltage (Transient Only, Note )... ±V Input Voltage... ±V S Output Short-Circuit Duration (Note )... Indefinite Operating Temperature Range... C to 85 C Specified Temperature Range (Note 6)... C to 85 C Maximum Junction Temperature (See Below) Plastic Package... 5 C Storage Temperature Range... 65 C to 5 C Lead Temperature (Soldering, sec)... 3 C PACKAGE/ORDER INFORMATION NLL IN +IN 3 V TOP VIEW MS8 PACKAGE 8-LEAD PLASTIC MSOP 8 NLL 7 V + 6 V OT 5 SHDN T JMAX = 5 C, θ JA = 5 C/ W Consult factory for Industrial and Military grade parts. W ORDER PART NMBER CMS8 MS8 PART MARKING LTBT NLL IN +IN 3 V N8 PACKAGE 8-LEAD PDIP TOP VIEW 8 NLL 7 V + 6 V OT 5 SHDN S8 PACKAGE 8-LEAD PLASTIC SO T JMAX = 5 C, θ JA = 3 C/ W (N8) T JMAX = 5 C, θ JA = 9 C/ W (S) ORDER PART NMBER CN8 CS8 S8 PART MARKING 35 ELECTRICAL CHARACTERISTICS, V CM = V unless otherwise noted. SYMBOL PARAMETER CONDITIONS V SPPLY MIN TYP MAX NITS V OS Input Offset Voltage ±5V..6 mv ±5V..6 mv ±.5V.3.8 mv I OS Input Offset Current ±.5V to ±5V 5 5 na I B Input Bias Current ±.5V to ±5V 5 na e n Input Noise Voltage f = khz ±.5V to ±5V nv/ Hz i n Input Noise Current f = khz ±.5V to ±5V.5 pa/ Hz R IN Input Resistance V CM = ±V ±5V 3 6 MΩ Differential ±5V MΩ C IN Input Capacitance ±5V 3 pf Positive Input Voltage Range ±5V. 3.5 V ±5V.5 3.5 V ±.5V.5. V Negative Input Voltage Range ±5V 3.5. V ±5V 3.5.5 V ±.5V..5 V CMRR Common Mode Rejection Ratio V CM = ±V ±5V 8 9 db V CM = ±.5V ±5V 78 86 db V CM = ±.5V ±.5V 68 77 db PSRR Power Supply Rejection Ratio V S = ±.5V to ±5V 9 6 db
ELECTRICAL CHARACTERISTICS, V CM = V unless otherwise noted. SYMBOL PARAMETER CONDITIONS V SPPLY MIN TYP MAX NITS A VOL Large-Signal Voltage Gain V OT = ±V, R L = 5k ±5V 8 V/mV V OT = ±V, R L = k ±5V 3 6 V/mV V OT = ±V, R L = k ±5V V/mV V OT = ±.5V, R L = 5k ±5V 3 6 V/mV V OT = ±.5V, R L = k ±5V 5 5 V/mV V OT = ±.5V, R L = k ±5V 5 3 V/mV V OT = ±V, R L = 5k ±.5V V/mV V OT Output Swing R L = 5k, V IN = ±mv ±5V 3.5. ±V R L = k, V IN = ±mv ±5V 3. 3.8 ±V R L = k, V IN = ±mv ±5V 3. 3. ±V R L = k, V IN = ±mv ±5V 3.5. ±V R L = 5Ω, V IN = ±mv ±5V 3. 3.8 ±V R L = 5k, V IN = ±mv ±.5V.3.7 ±V I OT Output Current V OT = ±3V ±5V 3. 3. ma V OT = ±3.V ±5V 6.8 7.6 ma I SC Short-Circuit Current V OT = V, V IN = ±3V ±5V 3 5 ma SR Slew Rate, R L = 5k (Note 3) ±5V V/µs ±5V 3 5 V/µs Full-Power Bandwidth V Peak (Note ) ±5V 3. MHz 3V Peak (Note ) ±5V.6 MHz GBW Gain Bandwidth f = khz, R L = k ±5V. 3. MHz ± 5V.8.7 MHz ±.5V.5 MHz t r, t f Rise Time, Fall Time A V =, % to 9%,.V ±5V 6 ns ±5V 53 ns Overshoot A V =,.V ±5V 3 % ±5V 6 % Propagation Delay 5% V IN to 5% V OT,.V ±5V ns ±5V 5 ns t s Settling Time V Step,.%, ±5V 7 ns V Step,.%, ±5V 5 ns 5V Step,.%, ±5V 95 ns 5V Step,.%, ±5V ns R O Output Resistance A V =, f = khz ±5V.5 Ω I SHDN Shutdown Input Current SHDN = V EE +.V ±5V µa SHDN = V CC ±5V. µa I S Supply Current ±5V 5 33 µa ±5V 3 µa SHDN = V EE +.V ±5V µa C T A 7 C, V CM = V unless otherwise noted. SYMBOL PARAMETER CONDITIONS V SPPLY MIN TYP MAX NITS V OS Input Offset Voltage ±5V.8 mv ±5V.8 mv ±.5V. mv Input V OS Drift (Note 5) ±.5V to ±5V 3 8 µv/ C I OS Input Offset Current ±.5V to ±5V na I B Input Bias Current ±.5V to ±5V 75 na 3
ELECTRICAL CHARACTERISTICS C T A 7 C, V CM = V unless otherwise noted. SYMBOL PARAMETER CONDITIONS V SPPLY MIN TYP MAX NITS CMRR Common Mode Rejection Ratio V CM = ±V ±5V 78 db V CM = ±.5V ±5V 77 db V CM = ±.5V ±.5V 67 db PSRR Power Supply Rejection Ratio V S = ±.5V to ±5V 89 db A VOL Large-Signal Voltage Gain V OT = ±V, R L = 5k ±5V 5 V/mV V OT = ±V, R L = k ±5V V/mV V OT = ±.5V, R L = 5k ±5V V/mV V OT = ±.5V, R L = k ±5V 5 V/mV V OT = ±.5V, R L = k ±5V V/mV V OT = ±V, R L = 5k ±.5V 5 V/mV V OT Output Swing R L = 5k, V IN = ±mv ±5V 3. ±V R L = k, V IN = ±mv ±5V 3.3 ±V R L = k, V IN = ±mv ±5V. ±V R L = k, V IN = ±mv ±5V 3. ±V R L = 5Ω, V IN = ±mv ±5V 3.3 ±V R L = 5k, V IN = ±mv ±.5V. ±V I OT Output Current V OT = ±V ±5V. ma V OT = ±3.3V ±5V 6.6 ma I SC Short-Circuit Current V OT = V, V IN = ±3V ±5V ma SR Slew Rate, R L = 5k (Note 3) ±5V V/µs ±5V V/µs GBW Gain Bandwidth f = khz, R L = k ±5V.8 MHz ± 5V.6 MHz I SHDN Shutdown Input Current SHDN = V EE +.V ±5V µa SHDN = V CC ±5V 3 µa I S Supply Current ±5V 38 µa ±5V 355 µa SHDN = V EE +.V ±5V µa C T A 85 C, V CM = V unless otherwise noted (Note 6). SYMBOL PARAMETER CONDITIONS V SPPLY MIN TYP MAX NITS V OS Input Offset Voltage ±5V. mv ±5V. mv ±.5V. mv Input V OS Drift (Note 5) ±.5V to ±5V 3 8 µv/ C I OS Input Offset Current ±.5V to ±5V 3 na I B Input Bias Current ±.5V to ±5V na CMRR Common Mode Rejection Ratio V CM = ±V ±5V 76 db V CM = ±.5V ±5V 76 db V CM = ±.5V ±.5V 66 db PSRR Power Supply Rejection Ratio V S = ±.5V to ±5V 87 db A VOL Large-Signal Voltage Gain V OT = ±V, R L = 5k ±5V V/mV V OT = ±V, R L = k ±5V 5 V/mV V OT = ±.5V, R L = 5k ±5V 5 V/mV V OT = ±.5V, R L = k ±5V V/mV V OT = ±.5V, R L = k ±5V 8 V/mV V OT = ±V, R L = 5k ±.5V V/mV
ELECTRICAL CHARACTERISTICS C T A 85 C, V CM = V unless otherwise noted (Note 6). SYMBOL PARAMETER CONDITIONS V SPPLY MIN TYP MAX NITS V OT Output Swing R L = 5k, V IN = ±mv ±5V 3.3 ±V R L = k, V IN = ±mv ±5V 3. ±V R L = k, V IN = ±mv ±5V. ±V R L = k, V IN = ±mv ±5V 3.3 ±V R L = 5Ω, V IN = ±mv ±5V 3. ±V R L = 5k, V IN = ±mv ±.5V. ±V I OT Output Current V OT = ±V ±5V. ma V OT = ±3.V ±5V 6. ma I SC Short-Circuit Current V OT = V, V IN = ±3V ±5V ma SR Slew Rate, R L = 5k (Note 3) ±5V 5 V/µs ±5V 5 V/µs GBW Gain Bandwidth f = khz, R L = k ±5V.6 MHz ± 5V. MHz I SHDN Shutdown Input Current SHDN = V EE +.V ±5V 3 µa SHDN = V CC ±5V 5 µa I S Supply Current ±5V 39 µa ±5V 38 µa SHDN = V EE +.V ±5V 3 µa Note : Differential inputs of ±V are appropriate for transient operation only, such as during slewing. Large, sustained differential inputs will cause excessive power dissipation and may damage the part. See Input Considerations in the Applications Information section of this data sheet for more details. Note : A heat sink may be required to keep the junction temperature below absolute maximum when the output is shorted indefinitely. Note 3: Slew rate is measured between ±8V on the output with ±V input for ±5V supplies and ±V on the output with ±3V input for ±5V supplies. Note : Full-power bandwidth is calculated from the slew rate measurement: FPBW = (Slew Rate)/πV P. Note 5: This parameter is not % tested. Note 6: The is designed, characterized and expected to meet these extended temperature limits, but is not tested at C and at 85 C. Guaranteed I grade parts are available; consult factory. TYPICAL PERFORMANCE CHARACTERISTICS W SPPLY CRRENT (µa) 35 3 5 5 Supply Current vs Supply Voltage and Temperature 5 C 5 C 55 C 5 5 SPPLY VOLTAGE (±V) 35 G COMMON MODE RANGE (V) V +.5..5...5..5 V Input Common Mode Range vs Supply Voltage V OS = mv 5 5 SPPLY VOLTAGE (±V) 35 G INPT BIAS CRRENT (na) 3 5 Input Bias Current vs Input Common Mode Voltage I B = I B + + I B 5 5 5 INPT COMMON MODE VOLTAGE (V) 35 G3 5
TYPICAL PERFORMANCE CHARACTERISTICS W INPT BIAS CRRENT (na) 36 3 8 6 8 5 Input Bias Current vs Temperature I B = I B + + I B 5 5 5 75 5 TEMPERATRE ( C) 35 G INPT VOLTAGE NOISE (nv/ Hz) Input Noise Spectral Density. k k e n i n A V = R S = k 35 G5 INPT CRRENT NOISE (pa/ Hz) OPEN-LOOP GAIN (db) 9 8 7 6 Open-Loop Gain vs Resistive Load k k LOAD RESISTANCE (Ω) V S = ±5V 35 G6 OPEN-LOOP GAIN (db) 99 98 97 96 95 9 5 Open-Loop Gain vs Temperature V O = ±V R L = 5k 5 5 5 75 5 TEMPERATRE ( C) OTPT VOLTAGE SWING (V) V + 3 3 V Output Voltage Swing vs Supply Voltage V IN = ±mv R L = k R L = k R L = k R L = k 5 5 SPPLY VOLTAGE (V) OTPT VOLTAGE SWING (V) V +.5..5...5..5 V Output Voltage Swing vs Load Current V S = ±5V V IN = mv 5 C 85 C C 5 C 85 C C C 5 C 85 C C 5 C 85 C 5 5 5 5 OTPT CRRENT (ma) 35 G7 35 G8 35 G9 OTPT SHORT-CIRCIT CRRENT (ma) 6 55 5 5 35 3 Output Short-Circuit Current vs Temperature SORCE SINK 5 5 5 5 5 75 5 TEMPERATRE ( C) OTPT STEP (V) 8 6 6 8.7 Settling Time vs Output Step (Noninverting) mv mv mv mv A V = OTPT FILTER:.6MHz LPF.8.9...3..5.6 SETTLING TIME (µs) OTPT STEP (V) 8 6 Settling Time vs Output Step (Inverting) mv mv mv mv 6 R G = R F = k 8 C F = 5pF R L = k.5.6.7.8.9....3..5 SETTLING TIME (µs) 35 G 35 G 35 G 6
TYPICAL PERFORMANCE CHARACTERISTICS GAIN (db) 7 6 5 3 Gain and Phase vs Frequency V S = ±5V GAIN PHASE V S = ±5V W R F = R G = 5k k k k M M M 35 G3 8 6 PHASE (DEG) OTPT IMPEDANCE (Ω). Output Impedance vs Frequency A V = A V = A V =. k k k M M 35 G GAIN (db) 8 6 6 8 k Frequency Response vs Capacitive Load R FB = R G = 5k C = 5pF C = pf C = pf C = 5pF C = pf k M M 35 G5 GAIN BANDWIDTH (MHz).5.5. 3.75 3.5 3.5 3..75.5.5. 5 Gain Bandwidth and Phase Margin vs Temperature V S = ±5V PHASE MARGIN GAIN BANDWIDTH V S = ±5V 5 8 6 38 36 3 3 3 5 5 5 75 5 TEMPERATRE ( C) PHASE MARGIN (DEG) GAIN (db) 5 3 3 5 k Frequency Response vs Supply Voltage (A V = ) A V = R L = 5k ±5V ±5V ±.5V k M M GAIN (db) 5 3 3 5 k Frequency Response vs Supply Voltage () R L = R G = 5k ±5V ±5V ±.5V k M M 35 G6 35 G7 35 G8 GAIN BANDWIDTH (MHz).5.5. 3.75 3.5 3.5 3..75.5.5. Gain Bandwidth and Phase Margin vs Supply Voltage PHASE MARGIN GAIN BANDWIDTH 5 8 6 38 36 3 3 3 5 5 SPPLY VOLTAGE (±V) PHASE MARGIN (DEG) POWER SPPLY REJECTION RATIO (db) 8 6 Power Supply Rejection Ratio vs Frequency PSRR = +PSRR k k k M M COMMON MODE REJECTION RATIO (db) 8 6 Common Mode Rejection Ratio vs Frequency k k k M M 35 G9 35 G 35 G 7
TYPICAL PERFORMANCE CHARACTERISTICS W SLEW RATE (V/µs) 5 5 Slew Rate vs Supply Voltage R F = R G = 5k SR = (SR + + SR )/ SLEW RATE (V/µs) 5 5 5 Slew Rate vs Temperature V S = ±5V R F = R G = R L = 5k SR = (SR + + SR )/ SLEW RATE (V/µs) 75 5 5 75 5 5 Slew Rate vs Input Level R FB = R G = 5k SR = (SR + + SR )/ 5 SPPLY VOLTAGE (±V) 5 5 5 5 5 75 5 TEMPERATRE ( C) 8 6 INPT LEVEL (V P-P ) 35 G 35 G3 35 G TOTAL HARMONIC DISTORTION (%)... Total Harmonic Distortion vs Frequency R L = 5k V O = V P-P A V = k k k OTPT VOLTAGE (V P-P ) 3 5 5 ndistorted Output Swing vs Frequency (±5V) 5 R L = 5k THD = % k A V = k M OTPT VOLTAGE (V P-P ) 9 8 7 6 5 3 ndistorted Output Swing vs Frequency (±5V) V S = ±5V R L = 5k THD = % k k A V = M 35 G5 35 G6 35 G7 HARMONIC DISTORTION (db) 3 5 6 7 8 9 k nd and 3rd Harmonic Distortion vs Frequency A V = R L = 5k V O = V P-P 3RD HARMONIC ND HARMONIC 35 G8 M SPPLY CRRENT (µa) 9 8 7 6 5 3 Shutdown Supply Current vs Temperature 5 V SHDN = V EE +. V SHDN = V EE +. V SHDN = V EE 5 5 5 75 5 TEMPERATRE ( C) 35 G9 OVERSHOOT (%) 9 8 7 6 5 3 p Capacitive Load Handling R L = 5k A V = p n n.µ µ CAPACITIVE LOAD (F) 35 G3 8
TYPICAL PERFORMANCE CHARACTERISTICS W Small-Signal Transient (A V = ) Small-Signal Transient () Small-Signal Transient (, C L = pf) 35 G3 35 G3 35 G33 Large-Signal Transient (A V = ) Large-Signal Transient (A V = ) Large-Signal Transient (A V =, C L =,pf) 35 G3 35 G35 35 G36 APPLICATIONS INFORMATION W The may be inserted directly into many high speed amplifier applications improving both DC and AC performance, provided that the nulling circuitry is removed. The suggested nulling circuit for the is shown in Figure. 3 + 8 k V + V 7 6.µF.µF 35 F Figure. Offset Nulling Layout and Passive Components The amplifier is easy to apply and tolerant of less than ideal layouts. For maximum performance (for example fast settling time) use a ground plane, short lead lengths and RF-quality bypass capacitors (.µf to.µf). For high drive current applications use low ESR bypass capacitors (µf to µf tantalum). For details see Design Note 5. The parallel combination of the feedback resistor and gain setting resistor on the inverting input can combine with the input capacitance to form a pole which can cause peaking or even oscillations. For feedback resistors greater than k, a parallel capacitor of value, C F > (R G )(C IN /R F ) should be used to cancel the input pole and optimize dynamic performance. For applications where the DC 9
APPLICATIONS INFORMATION W noise gain is one and a large feedback resistor is used, C F should be greater than or equal to C IN. An example would be an I-to-V converter as shown in the Typical Applications section. Capacitive Loading The is stable with any capacitive load. As the capacitive load increases, both the bandwidth and phase margin decrease so there will be peaking in the frequency domain and in the transient response. Graphs of Frequency Response vs Capacitive Load, Capacitive Load Handling and the transient response photos clearly show these effects. Input Considerations Each of the inputs is the base of an NPN and a PNP transistor whose base currents are of opposite polarity and provide first-order bias current cancellation. Because of variation in the matching of NPN and PNP beta, the polarity of the input bias current can be positive or negative. The offset current does not depend on NPN/PNP beta matching and is well controlled. The use of balanced source resistance at each input is recommended for applications where DC accuracy must be maximized. The inputs can withstand transient differential input voltages up to V without damage and need no clamping or source resistance for protection. Differential inputs, however, generate large supply currents (tens of ma) as required for high slew rates. If the device is used with sustained differential inputs, the average supply current will increase, excessive power dissipation will result and the part may be damaged. The part should not be used as a comparator, peak detector or other open-loop application with large, sustained differential inputs. nder normal, closed-loop operation, an increase of power dissipation is only noticeable in applications with large slewing outputs and is proportional to the magnitude of the differential input voltage and the percent of the time that the inputs are apart. Measure the average supply current for the application in order to calculate the power dissipation. Shutdown The has a Shutdown pin for conserving power. When this pin is open or V above the negative supply the part operates normally. When pulled down to V the supply current will drop to about µa. The current out of the Shutdown pin is also typically µa. In shutdown the amplifier output is not isolated from the inputs so the cannot be used in multiplexing applications using the shutdown feature. A level shift application is shown in the Typical Applications section so that a ground-referenced logic signal can control the Shutdown pin. Circuit Operation The circuit topology is a true voltage feedback amplifier that has the slewing behavior of a current feedback amplifier. The operation of the circuit can be understood by referring to the simplified schematic. The inputs are buffered by complementary NPN and PNP emitter followers which drive R, a k resistor. The input voltage appears across the resistor generating currents which are mirrored into the high impedance node and compensation capacitor C T. Complementary followers form an output stage which buffers the gain node from the load. The output devices Q9 and Q are connected to form a composite PNP and composite NPN. The bandwidth is set by the input resistor and the capacitance on the high impedance node. The slew rate is determined by the current available to charge the capacitance. This current is the differential input voltage divided by R, so the slew rate is proportional to the input. Highest slew rates are therefore seen in the lowest gain configurations. For example, a V output step in a gain of has only a V input step whereas the same output step in unity gain has a times greater input step. The curve of Slew Rate vs Input Level illustrates this relationship. Capacitive load compensation is provided by the R C, C C network which is bootstrapped across the output stage. When the amplifier is driving a light load the network has no effect. When driving a capacitive load (or a low value
APPLICATIONS INFORMATION W resistive load) the network is incompletely bootstrapped and adds to the compensation at the high impedance node. The added capacitance slows down the amplifier and a zero is created by the RC combination, both of which improve the phase margin. The design ensures that even for very large load capacitances the total phase lag can never exceed 8 degrees (zero phase margin) and the amplifier remains stable. SI PLIFIED SCHE ATIC W W V + R R3 Q Q Q Q C Q Q9 R6 Q9 IN Q5 Q6 Q7 R k Q3 Q Q +IN Q7 R C C C OTPT Q8 Q Q3 C T Q8 R7 C Q Q Q5 Q6 Q3 Q R R5 V 35 SS TYPICAL APPLICATIONS khz, th Order Butterworth Filter.6k 7pF 5.9k pf V IN.6k 3.3k pf + 5.9k.3k 7pF + V OT 35 TA3
TYPICAL APPLICATIONS Shutdown Circuit SHDN N8 M G 3 S SST77 D M + G 5 S SST77 D 6 V 35 TA DAC I-to-V Converter pf DAC INPTS 565A TYPE 5k + V OT V OS + I OS (5kΩ) + <.5LSB V OT A VOL 5k 35 TA5
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. MS8 Package 8-Lead Plastic MSOP (LTC DWG # 5-8-66).8 ±.* (3. ±.) 8 7 6 5.9 ±. (.88 ±.).8 ±.** (3. ±.) 3.7 (.8). ±.6 (.53 ±.5) 6 TYP SEATING PLANE. ±.6 (. ±.5). (.3) REF.56 (.65) TYP.3 ±. (.86 ±.).6 ±. (.5 ±.) MSOP (MS8) 97 * DIMENSION DOES NOT INCLDE MOLD FLASH, PROTRSIONS OR GATE BRRS. MOLD FLASH, PROTRSIONS OR GATE BRRS SHALL NOT EXCEED.6" (.5mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH OR PROTRSIONS. INTERLEAD FLASH OR PROTRSIONS SHALL NOT EXCEED.6" (.5mm) PER SIDE 3
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead PDIP (Narrow.3) (LTC DWG # 5-8-5).* (.6) MAX 8 7 6 5.55 ±.5* (6.77 ±.38) 3.3.35 (7.6 8.55).5.65 (.3.65).3 ±.5 (3.3 ±.7).9.5 (.9.38).35 +.35.5 +.889 8.55.38 ( ).65 (.65) TYP. ±. (.5 ±.5) *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED. INCH (.5mm).5 (3.75) MIN.8 ±.3 (.57 ±.76). (.58) MIN N8 97
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic Small Outline (Narrow.5) (LTC DWG # 5-8-6).89.97* (.8 5.) 8 7 6 5.8. (5.79 6.97).5.57** (3.8 3.988) 3.8. (.3.5).. (.5.58) 5 8 TYP.53.69 (.36.75).. (..5).6.5.6.7 *DIMENSION DOES NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED.6" (.5mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.5mm) PER SIDE..9 (.355.83).5 (.7) TYP SO8 996 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 5
TYPICAL APPLICATION Low Power Sample-and-Hold V IN + LTC pf + V OT DROOP: na/pf = mv/ms ACQISITION TIME: V,.% = µs CHARGE INJECTION ERROR: 8pC/pF = mv 35 TA6 RELATED PARTS PART NMBER DESCRIPTION COMMENTS LT35/LT353 Dual/Quad 5µA, 3MHz, V/µs Op Amp Good DC Precision, Stable with All Capacitive Loads LT35 ma, MHz, V/µs Op Amp Good DC Precision, Stable with All Capacitive Loads 6 Linear Technology Corporation 63 McCarthy Blvd., Milpitas, CA 9535-77 (8)3-9 FAX: (8) 3-57 www.linear-tech.com 35fa LT/TP 98 REV A K PRINTED IN SA LINEAR TECHNOLOGY CORPORATION 996