LT1122 Fast Settling, JFET Input Operational Amplifier DESCRIPTIO

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Fast Settling, JFET Input Operational Amplifier FEATRES % Tested Settling Time ns Typ to mv at Sum Node, V Step ns Max Tested with Fixed Feedback Capacitor Slew Rate V/µs Min Gain Bandwidth Product

1 Fast Settling, JFET Input Operational Amplifier FEATRES % Tested Settling Time ns Typ to mv at Sum Node, V Step ns Max Tested with Fixed Feedback Capacitor Slew Rate V/µs Min Gain Bandwidth Product MHz Power Bandwidth (Vp-p). MHz nity Gain Stable; Phase Margin Input Offset Voltage µv Max Input Bias Current C pa Max C pa Max Input Offset Current C pa Max C pa Max Low Distortion APPLICATI O S Fast -Bit D/A Output Amplifiers High Speed Buffers Fast Sample and Hold Amplifiers High Speed Integrators Voltage to Frequency Converters Active Filters Log Amplifiers Peak Detectors DESCRIPTIO The JFET input operational amplifier combines high speed and precision performance. A unique poly-gate JFET process minimizes gate series resistance and gate-to-drain capacitance, facilitating wide bandwidth performance, without degrading JFET transistor matching. It slews at V/µs and settles in ns. The is internally compensated to be unity gain stable, yet it has a bandwidth of MHz at a supply current of only ma. Its speed makes the an ideal choice for fast settling -bit data conversion and acquisition systems. The offset voltage of µv, and voltage gain of, also support the -bit accurate applications. The input bias current of pa and offset current of pa combined with its speed allow the to be used in such applications as high speed sample and hold amplifiers, peak detectors, and integrators. TYPICAL APPLICATI O -Bit Voltage Output D/A Converter Large-Signal Response C f ma TO ma OR ma V OT V TO V V/DIV -BIT CRRENT OTPT D/A CONVERTER C f = pf TO pf (DEPENDING ON D/A CONVERTER SED) TA ns/div AV = TA

2 ABSOLTE AXI RATI GS W W W Supply Voltage... ± V Differential Input Voltage... ± V Input Voltage... ± V Output Short Circuit Duration... Indefinite Lead Temperature (Soldering, sec.)... C Operating Temperature Range AM/BM/CM/DM... C to C AC/BC/CC/DC/CS/DS... C to C Storage Temperature Range All Devices... C to C PACKAGE/ORDER I FOR TOP VIEW V OS TRIM SPEED BOOST/ OVERCOMP IN V IN V OT V OS TRIM N PACKAGE J PACKAGE -LEAD PLASTIC DIP -LEAD HERMETIC DIP T JMAX = C, θ JA = C/W (N) T JMAX = C, θ JA = C/W (J) Consult factory for Industrial grade parts. W ATIO ORDER PART NMBER AMJ CCJ BMJ DCJ CMJ ACN DMJ BCN ACJ CCN BCJ DCN TOP VIEW V OS SPEED BOOST/ TRIM OVERCOMP IN V IN V OT V OS TRIM S PACKAGE -LEAD PLASTIC SOIC T JMAX = C, θ JA = 9 C/W ORDER PART NMBER CS DS PART MARKING C D ELECTRICAL CHARA CTERISTICS V S = ± V,, V CM = V unless otherwise noted. (Note ) CM/DM AM/BM CC/DC AC/BC CS/DS SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX NITS V OS Input Offset Voltage 9 µv I OS Input Offset Current pa I B Input Bias Current pa Input Resistance Differential Ω Common Mode V CM = V to V Ω V CM = V to V Ω Input Capacitance pf S R Slew Rate A V = V/µs Settling Time (Note ) V to V, V to V % Tested: A and C Grades to mv at Sum Node 9 ns B and D Grades to mv at Sum Node ns All Grades to.mv at Sum Node ns GBW Gain Bandwidth Product MHz Power Bandwidth V OT = Vp-p.. MHz A VOL Large Signal Voltage Gain V OT = ± V, R L = kω V/mV V OT = ± V, R L = Ω V/mV CMRR Common Mode Rejection Ratio V CM = ± V 99 9 db Input Voltage Range (Note ) ±. ± ±. ± V PSRR Power Supply Rejection Ratio V S = ± V to ± V db Input Noise Voltage.Hz to Hz.. µv P-P Input Noise Voltage Density f O = Hz nv/ Hz f O = khz nv/ Hz Input Noise Current Density f O = Hz, f O = khz fa/ Hz

3 ELECTRICAL CHARA CTERISTICS V S = ± V,, V CM = V unless otherwise noted. CM/DM AM/BM CC/DC AC/BC CS/DS SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX NITS V OT Output Voltage Swing R L = kω ± ±. ± ±. V R L = Ω ±. ± ±. ± V I S Supply Current.. ma Minimum Supply voltage (Note ) ± ± V Offset Adjustment Range R POT k, Wiper to V ± ± ± ± mv V S = ± V, V CM = V, C T A C, unless otherwise noted. (Note ) CC/DC AC/BC CS/DS SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX NITS V OS Input Offset Voltage µv Average Temperature Coefficient µv/ C of Input Offset Voltage I OS Input Offset Current pa I B Input Bias Current 9 pa A VOL Large Signal Voltage Gain V OT = ± V, R L kω V/mV CMRR Common Mode Rejection Ratio V CM = ± V 9 9 db PSRR Power Supply Rejection Ratio V S = ± V to ± V 99 db Input Voltage Range ± ±. ± ±. V V OT Output Voltage Swing R L = kω ±. ±. ±. ±. V S R Slew Rate A V = V/µs V S = ± V, V CM = V, C T A C, unless otherwise noted. (Note ) AM/BM CM/DM SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX NITS V OS Input Offset Voltage µv Average Temperature Coefficient µv/ C of Input Offset Voltage I OS Input Offset Current.. 9 na I B Input Bias Current na A VOL Large Signal Voltage Gain V OT = ± V, R L kω V/mV CMRR Common Mode Rejection Ratio V CM = ± V 9 9 db PSRR Power Supply Rejection Ratio V S = ± V to ± V 9 db Input Voltage Range ± ±. ± ±. V V OT Output Voltage Swing R L = kω ±. ±. ±. ±. V S R Slew Rate A V = V/µs The denotes the specifications which apply over the full operating temperature range. Note : The is measured in an automated tester in less than one second after application of power. Depending on the package used, power dissipation, heat sinking, and air flow conditions, the fully warmed up chip temperature can be C to C higher than the ambient temperature. Note : Settling time is % tested for A and C grades using the settling time test circuit shown. This test is not included in quality assurance sample testing. Note : Input voltage range functionality is assured by testing offset voltage at the input voltage range limits to a maximum of mv (A, B grades), to.mv (C, D grades). Note : Minimum supply voltage is tested by measuring offset voltage to mv maximum at ± V supplies. Note : The is not tested and not quality-assurance-sampled at C and at C. These specifications are guaranteed by design, correlation and/or inference from C, C, C, C and/or C tests.

4 ELECTRICAL CHARA CTERISTICS V S = ± V, V CM = V, C T A C, unless otherwise noted. (Note ) CC/DC AC/BC CS/DS SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX NITS V OS Input Offset Voltage 9 µv Average Temperature Coefficient µv/ C of Input Offset Voltage I OS Input Offset Current 9 pa I B Input Bias Current pa A VOL Large Signal Voltage Gain V OT = ± V, R L kω 9 V/mV CMRR Common Mode Rejection Ratio V CM = ± V 9 9 db PSRR Power Supply Rejection Ratio V S = ± V to ± V 9 db Input Voltage Range ± ±. ± ±. V V OT Output Voltage Swing R L = kω ±. ±. ±. ±. V S R Slew Rate A V = V/µs Settling Time Test Fixture DEVICE NDER TEST pf LS GROND ALL OTHER INPTS V (REGLATED) V HA V k % k % V V V IN (MEASRE INPT PLSE HERE).k* %.k % TTL IN LTCA 9 V. µ F V V (REGLATED) µ F TANT TYPICAL SPPLY BYPASSING FOR EACH AMP/BFFER NO CONNECTION ON PINS,,,, AND SETTLING TIME OTPT ( TIMES SM NODE OTPT) N k.k V LT V V V 9 HA SMMING NODE OTPT N. µ F µ F TANT *THIS RESISTOR CAN BE ADJSTED TO NLL OT ALL OFFSETS AT THE SETTLING TIME OTPT. THE ATOMATED TESTER SES A SEPARATE ATOZERO CIRCIT. TA

TYPICAL PERFOR A W CE CHARA CTERISTICS Settling Time Settling Time

V to V) mv/div AT SM NODE mv/div AT SM NODE mv/div AT SM NODE

vs (Input From V to V) Large Signal Response Frequency mv/div AT

k M M M FREQENCY (Hz) TPC GAIN (db) Common Mode Rejection vs

(db) C L = pf PHASE SHIFT (DEGREES) COMMON-MODE REJECTION RATIO

5 TYPICAL PERFOR A W CE CHARA CTERISTICS Settling Time Settling Time Settling Time (Input From V to V) (Input From V to V) (Input From V to V) mv/div AT SM NODE mv/div AT SM NODE mv/div AT SM NODE ns/div G ns/div G ns/div G Settling Time ndistorted Output Swing vs (Input From V to V) Large Signal Response Frequency mv/div AT SM NODE ns/div G V/DIV ns/div A V = G PEAK TO PEAK OTPT SWING (V) k M M M FREQENCY (Hz) TPC GAIN (db) Common Mode Rejection vs Voltage Gain vs Frequency Gain, Phase vs Frequency Frequency GAIN (db) C L = pf PHASE SHIFT (DEGREES) COMMON-MODE REJECTION RATIO (db) k k k M M M M M M k k k M M M FREQENCY (Hz) TPC FREQENCY (Hz) TPC FREQENCY (Hz) TPC

6 TYPICAL PERFOR A W CE CHARA CTERISTICS NMBER OF NITS Distribution of Input Offset Input Bias and Offset Currents Bias and Offset Currents Over Voltage Over Temperature The Common-Mode Range 9 NITS TESTED IN ALL PACKAGES (NOT WARMED P) INPT OFFSET VOLTAGE ( µ V) 9 INPT BIAS AND OFFSET CRRENTS (pa) K K K K K V CM = V BIAS CRRENT CHIP TEMPERATRE ( C) OFFSET CRRENT INPT BIAS AND OFFSET CRRENT (pa) OFFSET CRRENT (NOT-WARMED P) BIAS CRRENT COMMON-MODE INPT VOLTAGE (V) TPC TPC TPC CHANGE IN OFFSET VOLTAGE ( µ V) TOTAL HARMONIC DISTORTION NOISE (%).... Warm-up Drift Noise Spectrum.Hz to Hz Noise VOLTAGE NOISE DENSITY (nv/ Hz) k k k FREQENCY (Hz) TPC9 NOISE VOLTAGE ( µ V/DIV) TIME (SECONDS) Total Harmonic Distortion Total Harmonic Distortion Intermodulation Distortion Noise vs Frequency Noise vs Frequency (CCIF Method) vs Frequency Inverting Gain Non-Inverting Gain and LF* Z L = k//pf V O = V RMS A = V A V = A V = SO PACKAGE N PACKAGE J PACKAGE IN STILL AIR (SO PACKAGE SOLDERED ONTO BOARD) TIME AFTER POWER ON (MINTES) TPC k k k TOTAL HARMONIC DISTORTION NOISE (%).... A V = A V = A = V Z L = k//pf V O = V RMS k k k INTERMODLATION DISTORTION (IMD) (%).... k LF k TPC A V = V O = V RMS Z L = k//pf k FREQENCY (Hz) TPC FREQENCY (Hz) TPC FREQENCY (Hz) *SEE LT DATA SHEET FOR DEFINITION OF CCIF TESTING TPC

7 APPLICATI O S Settling Time Measurements I FOR W ATIO Settling time test circuits shown on some competitive devices data sheets require:. A flat top pulse generator. nfortunately, flat top pulse generators are not commercially available.. A variable feedback capacitor around the device under test. This capacitor varies over a four to one range. Presumably, as each op amp is measured for settling time, the capacitor is fine tuned to optimize settling time for that particular device.. A small inductor load to optimize settling. The s settling time is % tested in the test circuit shown. No flat top pulse generator is required. The test circuit can be readily constructed, using commercially available ICs. Of course, standard high frequency board construction techniques should be followed. All s are measured with a constant feedback capacitor. No fine tuning is required. Speed Boost/Overcompensation Terminal Pin of the can be used to change the input stage operating current of the device. Shorting pin to the positive supply (Pin ) increases slew rate and bandwidth by about %, but at the expense of a reduction in phase margin by approximately degrees. nity gain capacitive load handling decreases from typically pf to pf. Conversely, connecting a k resistor from pin to ground pulls ma out of pin (with V = V). This reduces slew rate and bandwidth by %. Phase margin and capacitive load handling improve; the latter typically increasing to pf. High Speed Operation As with most high speed amplifiers, care should be taken with supply decoupling, lead dress and component placement. The power supply connections to the must maintain a low impedance to ground over a bandwidth of MHz. This is especially important when driving a significant resistive or capacitive load, since all current delivered to the load comes from the power supplies. Multiple high quality bypass capacitors are recommended for each power supply line in any critical application. A.µF ceramic and a µf electrolytic capacitor, as shown, placed as close as possible to the amplifier (with short lead lengths to power supply common) will assure adequate high frequency bypassing, in most applications. V V When the feedback around the op amp is resistive (R F ), a pole will be created with R F, the source resistance and capacitance (R S, C S ), and the amplifier input capacitance (C IN pf). In low closed loop gain configurations and with R S and R F in the kilohm range, this pole can create excess phase shift and even oscillation. A small capacitor (C F ) in parallel with R F eliminates this problem. With R S (C S C IN ) = R F C F, the effect of the feedback pole is completely removed. C F R F C IN R S C S µ F. µ F µ F. µ F TA OTPT TA Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights.

8 TYPICAL APPLICATIONS Quartz Stabilized Oscillator With 9ppm Distortion V OTPT.k LT.V khz J CT k LT.k k.k OTPT AMPLITDE µ F TRIM V k pf k DISTORTION TRIM MONT IN CLOSE PROXIMITY LT Ω V / LTC k V Q N9 V M k GROND CRYSTAL CASE = VACTEC VTLC OR CLAIREX CLM k = N TA Wide-Band, Filtered, Full Wave Rectifier k % µ F V IN k % k % k % k % k k E OT DC OTPT DC = RMS VALE OF INPT BANDWIDTH WITH Vp-p INPT = MHz TA PACKAGE DESCRIPTION Please see the 99 Linear Databook Volume III for package descriptions.

DESCRIPTIO. LT1413 Single Supply, Dual Precision Op Amp

DESCRIPTIO. LT1413 Single Supply, Dual Precision Op Amp Single Supply, Dual Precision Op Amp FEATRES Single Supply Operation: Input Goes Below Ground Output Swings to Ground Sinking Current No Pull-Down Resistors Needed Phase Reversal Protection At V, V Low