CoolSET -F3R ICE3BR4765J. Off-Line SMPS Current Mode Controller with integrated 650V CoolMOS and Startup cell (frequency jitter Mode) in DIP-8

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Version 2.5, 19 Nov 2012 CoolSET -F3R Off-Line SMPS Curren Mode Conroller wih inegraed 650V CoolMOS and Sarup cell (frequency jier Mode) in DIP-8 Power Managemen Supply Never sop hinking.

Revision Hisory: 2012-11-19 Daashee Previous Version: 2.4 Page Subjecs (major changes since las revision) 27 revised ouline dimension for PG-DIP-8 package For quesions on echnology, delivery and prices please conac he Infineon Technologies Offices in Germany or he Infineon Technologies Companies and Represenaives worldwide: see our webpage a hp:// www.infineon.com CoolMOS, CoolSET are rademarks of Infineon Technologies AG. Ediion 2012-11-19 Published by Infineon Technologies AG, 81726 Munich, Germany, 2012 Infineon Technologies AG. All Righs Reserved. Legal disclaimer The informaion given in his documen shall in no even be regarded as a guaranee of condiions or characerisics. Wih respec o any examples or hins given herein, any ypical values saed herein and/or any informaion regarding he applicaion of he device, Infineon Technologies hereby disclaims any and all warranies and liabiliies of any kind, including wihou limiaion, warranies of non-infringemen of inellecual propery righs of any hird pary. Informaion For furher informaion on echnology, delivery erms and condiions and prices, please conac your neares Infineon Technologies Office (www.infineon.com). Warnings Due o echnical requiremens, componens may conain dangerous subsances. For informaion on he ypes in quesion, please conac your neares Infineon Technologies Office. Infineon Technologies Componens may be used in life-suppor devices or sysems only wih he express wrien approval of Infineon Technologies, if a failure of such componens can reasonably be expeced o cause he failure of ha life-suppor device or sysem or o affec he safey or effeciveness of ha device or sysem. Life suppor devices or sysems are inended o be implaned in he human body or o suppor and/or mainain and susain and/or proec human life. If hey fail, i is reasonable o assume ha he healh of he user or oher persons may be endangered.

Off-Line SMPS Curren Mode Conroller wih inegraed 650V CoolMOS and Sarup cell (frequency jier Mode) in DIP-8 Produc Highlighs Acive Burs Mode o reach he lowes Sandby Power Requiremens < 50mW Auo Resar proecion for overload, overemperaure, overvolage Exernal auo-resar enable funcion Buil-in sof sar and blanking window Exendable blanking Window for high load jumps Buil-in frequency jier and sof driving for low EMI Green Mould Compound Pb-free lead plaing; RoHS complian Feaures 650V avalanche rugged CoolMOS wih buil-in Sarup Cell Acive Burs Mode for lowes Sandby Power Fas load jump response in Acive Burs Mode 65kHz inernally fixed swiching frequency Auo Resar Proecion Mode for Overload, Open Loop, VCC Undervolage, Overemperaure Overvolage Buil-in Sof Sar Buil-in blanking window wih exendable blanking ime for shor duraion high curren Exernal auo-resar enable pin Max Duy Cycle 75% Overall olerance of Curren Limiing < ±5% Inernal PWM Leading Edge Blanking BiCMOS echnology provide wide VCC range Buil-in Frequency jier and sof driving for low EMI CoolSET -F3R PG-DIP-8 Descripion The CoolSET -F3R jier series (ICE3BRxx65J) is he laes version of CoolSET -F3. I arges for he Off-Line baery adapers and low cos SMPS for lower power range such as applicaion for DVD R/W, DVD Combi, Blue ray DVD player, se op box, ec. Besides inheried he ousanding performance of he CoolSET -F3 in he BiCMOS echnology, acive burs mode, auo-resar proecion, propagaion delay compensaion, ec., CoolSET -F3R series has some new feaures such as buil-in sof sar ime, buil-in blanking window, buil-in frequency jier, sof gae driving, ec. In case a longer blanking ime is needed for high load applicaion, a simple addiion of capacior o BA pin can serve he purpose. Furhermore, an exernal auo-resar enable feaure can provide exra proecion when here is a need of immediae sop of power swiching. Typical Applicaion 85... 270 VAC CBulk Snubber + Converer DC Oupu - VCC CVCC Drain Power Managemen Sarup Cell GND PWM Conroller Curren Mode Precise Low Tolerance Peak Curren Limiaion Conrol Uni Acive Burs Mode Auo Resar Mode CoolMOS CS FB BA CoolSET -F3R (Jier Mode) RSense Type Package Marking V DS F OSC 1) R DSon 230VAC ±15% 2) 85-265 VAC 2) PG-DIP-8 650V 65kHz 4.70 27W 18W 1) yp @ T j =25 C 2) Calculaed maximum inpu power raing a T a =50 C, T i =125 C and wihou copper area as hea sink. Refer o inpu power curve for oher T a. Version 2.5 3 19 Nov 2012

Table of Conens Page 1 Pin Configuraion and Funcionaliy.............................6 1.1 Pin Configuraion wih PG-DIP-8..................................6 1.2 Pin Funcionaliy..............................................6 2 Represenaive Blockdiagram..................................7 3 Funcional Descripion........................................8 3.1 Inroducion..................................................8 3.2 Power Managemen............................................8 3.3 Improved Curren Mode.........................................9 3.3.1 PWM-OP.................................................10 3.3.2 PWM-Comparaor..........................................10 3.4 Sarup Phase...............................................11 3.5 PWM Secion................................................12 3.5.1 Oscillaor.................................................12 3.5.2 PWM-Lach FF1............................................12 3.5.3 Gae Driver...............................................13 3.6 Curren Limiing..............................................13 3.6.1 Leading Edge Blanking......................................14 3.6.2 Propagaion Delay Compensaion..............................14 3.7 Conrol Uni.................................................15 3.7.1 Basic and Exendable Blanking Mode...........................15 3.7.2 Acive Burs Mode..........................................15 3.7.2.1 Enering Acive Burs Mode.................................15 3.7.2.2 Working in Acive Burs Mode...............................16 3.7.2.3 Leaving Acive Burs Mode.................................16 3.7.3 Proecion Modes...........................................17 3.7.3.1 Auo Resar mode wih exended blanking ime.................17 3.7.3.2 Auo Resar wihou exended blanking ime...................18 4 Elecrical Characerisics.....................................19 4.1 Absolue Maximum Raings.....................................19 4.2 Operaing Range.............................................20 4.3 Characerisics...............................................20 4.3.1 Supply Secion.............................................20 4.3.2 Inernal Volage Reference...................................21 4.3.3 PWM Secion..............................................21 4.3.4 Sof Sar ime.............................................21 4.3.5 Conrol Uni...............................................22 4.3.6 Curren Limiing............................................23 4.3.7 CoolMOS Secion.........................................23 5 Typical CoolMOS Performance Characerisic...................24 Version 2.5 4 19 Nov 2012

6 Inpu Power Curve...........................................26 7 Ouline Dimension...........................................27 8 Marking....................................................28 9 Schemaic for recommended PCB layou........................29 Version 2.5 5 19 Nov 2012

1 Pin Configuraion and Funcionaliy 1.1 Pin Configuraion wih PG-DIP-8 Pin Symbol Funcion 1 BA exended Blanking Auo-resar 2 FB FeedBack 3 CS Curren Sense/ 650V 1) CoolMOS Source 4 Drain 650V 1) CoolMOS Drain CoolSET -F3R Pin Configuraion and Funcionaliy 1.2 Pin Funcionaliy BA (exended Blanking Auo-resar) The BA pin combines he funcions of exendable blanking ime for over load proecion and he exernal auo-resar enable. The exendable blanking ime funcion is o exend he buil-in 20 ms blanking ime by adding an exernal capacior a BA pin o ground. The exernal auo-resar enable funcion is an exernal access o sop he gae swiching and force he IC ener auo-resar mode. I is riggered by pulling down he BA pin o less han 0.33V. 5 Drain 650V 1) CoolMOS Drain 6 n.c. No conneced 7 VCC Conroller Supply Volage 8 GND Conroller GrouND 1) a T j =110 C Package PG-DIP-8 FB (Feedback) The informaion abou he regulaion is provided by he FB Pin o he inernal Proecion Uni and o he inernal PWM-Comparaor o conrol he duy cycle. The FB- Signal is he only conrol signal in case of ligh load a he Acive Burs Mode. CS (Curren Sense) The Curren Sense pin senses he volage developed on he series resisor insered in he source of he inegraed CoolMOS If volage in CS pin reaches he inernal hreshold of he Curren Limi Comparaor, he Driver oupu is immediaely swiched off. Furhermore he curren informaion is provided for he PWM- Comparaor o realize he Curren Mode. BA FB 1 2 8 7 GND VCC Drain (Drain of inegraed CoolMOS ) Drain pin is he connecion o he Drain of he inegraed CoolMOS. CS 3 6 n.c. VCC (Power Supply) VCC pin is he posiive supply of he IC. The operaing range is beween 10.5V and 25V. Drain 4 5 Drain GND (Ground) GND pin is he ground of he conroller. Figure 1 Pin Configuraion PG-DIP-8 (op view) Noe: Pin 4 and 5 are shored Version 2.5 6 19 Nov 2012

Represenaive Blockdiagram 2 Represenaive Blockdiagram 85... 270 VAC Auo-resar Enable BA Signal #1 CBK #2 TAE FB CBulk Snubber CVCC VCC Drain 0.9V S1 5.0V RFB 3.25kΩ IBK 25kΩ T2 T1 VCC 20.5V VCC 25.5V 0.33V 4.0V 4.0V C1 C2 C3 C4 5.0V T3 0.6V C9 G1 120us Blanking Time Thermal Shudown Tj >130 C G2 20ms Blanking Time G5 Power Managemen Inernal Bias Volage Reference Spike Blanking 30us Power-Down Rese 1 ms couner Sof Sar Block Auo Resar Mode Sof Sar Sof-Sar Comparaor C7 G7 PWM Comparaor C8 5.0V Undervolage Lockou 18V 10.5V Oscillaor Duy Cycle max Clock Freq. jier 0.72 G8 Propagaion-Delay Compensaion FF1 S R PWM Secion Q CoolMOS Sarup Cell Gae Driver G9 Acive Burs Vcsh 10kΩ C5 20ms Blanking Leading Mode 0.67V C10 1.35V Time Edge 2pF G6 Blanking 1pF D1 x3.3 220ns C6a PWM OP 3.5V G10 C12 0.34V Curren Limiing C6b G11 Curren Mode 3.0V Conrol Uni ICE3BRxx65J / CoolSET -F3R ( Jier Mode ) # : opional exernal componens; #1 : CBK is used o exend he Blanking Time #2 : TAE is used o enable he exernal Auo-resar feaure GND CS RSense Converer DC Oupu VOUT 1 1 + - Figure 2 Represenaive Blockdiagram Version 2.5 7 19 Nov 2012

Funcional Descripion 3 Funcional Descripion All values which are used in he funcional descripion are ypical values. For calculaing he wors cases he min/max values which can be found in secion 4 Elecrical Characerisics have o be considered. 3.1 Inroducion CoolSET -F3R jier series (ICE3BRxx65J) is he laes version of he CoolSET -F3 for he lower power applicaion. The paricular enhanced feaures are he buil-in feaures for sof sar, blanking window and frequency jier. I provides he flexibiliy o increase he blanking window by simply addiion of a capacior in BA pin. In order o furher increase he flexibiliy of he proecion feaure, an exernal auo-resar enable feaures are added. Moreover, he proven ousanding feaures in CoolSET -F3 are sill remained such as he acive burs mode, propagaion delay compensaion, modulaed gae driving, auo-resar proecion for Vcc overvolage, over emperaure, over load, open loop, ec. The inelligen Acive Burs Mode can effecively obain he lowes Sandby Power a ligh load and no load condiions. Afer enering he burs mode, here is sill a full conrol of he power conversion o he oupu hrough he opocoupler, ha is used for he normal PWM conrol. The response on load jumps is opimized and he volage ripple on V ou is minimized. The V ou is on well conrolled in his mode. The usually exernal conneced RC-filer in he feedback line afer he opocoupler is inegraed in he IC o reduce he exernal par coun. Furhermore a high volage Sarup Cell is inegraed ino he IC which is swiched off once he Undervolage Lockou on-hreshold of 18V is exceeded. This Sarup Cell is par of he inegraed CoolMOS. The exernal sarup resisor is no longer necessary as his Sarup Cell is conneced o he Drain. Power losses are herefore reduced. This increases he efficiency under ligh load condiions drasically. Adoping he BiCMOS echnology, i can increase he design flexibiliy as he Vcc volage range is increased o 25V. The CoolSET -F3R has a buil-in 20ms sof sar funcion. I can furher save exernal componen couns. There are 2 modes of blanking ime for high load jumps; he basic mode and he exendable mode. The blanking ime for he basic mode is se a 20ms while he exendable mode will increase he blanking ime by adding an exernal capacior a he BA pin in addiion o he basic mode blanking ime. During his blanking ime window he overload deecion is disabled. Wih his concep no furher exernal componens are necessary o adjus he blanking window. In order o increase he robusness and safey of he sysem, he IC provides Auo Resar proecion. The Auo Resar Mode reduces he average power conversion o a minimum level under unsafe operaing condiions. This is necessary for a prolonged faul condiion which could oherwise lead o a desrucion of he SMPS over ime. Once he malfuncion is removed, normal operaion is auomaically reained afer he nex Sar Up Phase. To make he proecion more flexible, an exernal auo-resar enable pin is provided. When he pin is riggered, he swiching pulse a gae will sop and he IC eners he auo-resar mode afer he pre-defined spike blanking ime. The inernal precise peak curren conrol reduces he coss for he ransformer and he secondary diode. The influence of he change in he inpu volage on he maximum power limiaion can be avoided ogeher wih he inegraed Propagaion Delay Compensaion. Therefore he maximum power is nearly independen on he inpu volage, which is required for wide range SMPS. Thus here is no need for he over-sizing of he SMPS, e.g. he ransformer and he oupu diode. Furhermore, his F3R series implemens he frequency jier mode o he swiching clock such ha he EMI noise will be effecively reduced. 3.2 Power Managemen Drain Figure 3 Power Managemen Inernal Bias Power-Down Rese Sof Sar block Sarup Cell Undervolage Lockou 18V 10.5V Volage Reference Power Managemen Auo Resar Mode Acive Burs Mode VCC Depl. CoolMOS 5.0V Version 2.5 8 19 Nov 2012

Funcional Descripion The Undervolage Lockou moniors he exernal supply volage V VCC. When he SMPS is plugged o he main line he inernal Sarup Cell is biased and sars o charge he exernal capacior C VCC which is conneced o he VCC pin. This VCC charge curren is conrolled o 0.9mA by he Sarup Cell. When he V VCC exceeds he on-hreshold V CCon =18V he bias circui are swiched on. Then he Sarup Cell is swiched off by he Undervolage Lockou and herefore no power losses presen due o he connecion of he Sarup Cell o he Drain volage. To avoid unconrolled ringing a swich-on, a hyseresis sar up volage is implemened. The swich-off of he conroller can only ake place when V VCC falls below 10.5V afer normal operaion was enered. The maximum curren consumpion before he conroller is acivaed is abou 150μA. When V VCC falls below he off-hreshold V CCoff =10.5V, he bias circui is swiched off and he sof sar couner is rese. Thus i is ensured ha a every sarup cycle he sof sar sars a zero. The inernal bias circui is swiched off if Auo Resar Mode is enered. The curren consumpion is hen reduced o 150μA. Once he malfuncion condiion is removed, his block will hen urn back on. The recovery from Auo Resar Mode does no require re-cycling he AC line. When Acive Burs Mode is enered, he inernal Bias is swiched off mos of he ime bu he Volage Reference is kep alive in order o reduce he curren consumpion below 450μA. 3.3 Improved Curren Mode FB Figure 4 Sof-Sar Comparaor 0.67V C8 PWM OP x3.3 Improved Curren Mode Curren Mode PWM-Lach R S CS Q Q Driver Curren Mode means he duy cycle is conrolled by he slope of he primary curren. This is done by comparing he FB signal wih he amplified curren sense signal. Amplified Curren Signal FB 0.67V Driver on Figure 5 Pulse Widh Modulaion In case he amplified curren sense signal exceeds he FB signal he on-ime T on of he driver is finished by reseing he PWM-Lach (see Figure 5). The primary curren is sensed by he exernal series resisor R Sense insered in he source of he inegraed CoolMOS. By means of Curren Mode regulaion, he secondary oupu volage is insensiive o he line variaions. The curren waveform slope will change wih he line variaion, which conrols he duy cycle. The exernal R Sense allows an individual adjusmen of he maximum source curren of he inegraed CoolMOS. To improve he Curren Mode during ligh load condiions he amplified curren ramp of he PWM-OP is superimposed on a volage ramp, which is buil by he swich T2, he volage source V1 and a resisor R1 (see Figure 6). Every ime he oscillaor shus down for maximum duy cycle limiaion he swich T2 is closed by V OSC. When he oscillaor riggers he Gae Driver, T2 is opened so ha he volage ramp can sar. In case of ligh load he amplified curren ramp is oo small o ensure a sable regulaion. In ha case he Volage Ramp is a well defined signal for he comparison wih he FB-signal. The duy cycle is hen conrolled by he slope of he Volage Ramp. By means of he ime delay circui which is riggered by he invered V OSC signal, he Gae Driver is swiched-off unil i reaches approximaely 156ns delay ime (see Figure 7). I allows he duy cycle o be reduced coninuously ill 0% by decreasing V FB below ha hreshold. Version 2.5 9 19 Nov 2012

Funcional Descripion FB Sof-Sar Comparaor Oscillaor V OSC T 2 R 1 C 1 PWM Comparaor C8 ime delay circui (156ns) 0.67V 10kΩ V 1 PWM-Lach Gae Driver X3.3 PWM OP 3.3.1 PWM-OP The inpu of he PWM-OP is applied over he inernal leading edge blanking o he exernal sense resisor R Sense conneced o pin CS. R Sense convers he source curren ino a sense volage. The sense volage is amplified wih a gain of 3.3 by PWM OP. The oupu of he PWM-OP is conneced o he volage source V 1. The volage ramp wih he superimposed amplified curren signal is fed ino he posiive inpus of he PWM- Comparaor C8 and he Sof-Sar-Comparaor (see Figure 6). 3.3.2 PWM-Comparaor The PWM-Comparaor compares he sensed curren signal of he inegraed CoolMOS wih he feedback signal V FB (see Figure 8). V FB is creaed by an exernal opocoupler or exernal ransisor in combinaion wih he inernal pull-up resisor R FB and provides he load informaion of he feedback circuiry. When he amplified curren signal of he inegraed CoolMOS exceeds he signal V FB he PWM-Comparaor swiches off he Gae Driver. Volage Ramp Figure 6 Improved Curren Mode R FB 5V Sof-Sar Comparaor V OSC max. Duy Cycle FB C8 PWM-Lach PWM Comparaor Volage Ramp 0.67V FB Opocoupler 0.67V PWM OP X3.3 CS Gae Driver Improved Curren Mode 156ns ime delay Figure 8 PWM Conrolling Figure 7 Ligh Load Condiions Version 2.5 10 19 Nov 2012

Funcional Descripion 3.4 Sarup Phase Sof Sar couner When he V VCC exceeds he on-hreshold volage, he IC sars he Sof Sar mode (see Figure 10). The funcion is realized by an inernal Sof Sar resisor, an curren sink and a couner. And he ampliude of he curren sink is conrolled by he couner (see Figure 11). Sof Sar finish SofS C7 Sof Sar Sof Sar Sof-Sar Comparaor Gae Driver SofS 5V R SofS G7 0.67V Sof Sar Couner 32I 8I 4I 2I I PWM OP x3.3 CS Figure 9 Sof Sar In he Sarup Phase, he IC provides a Sof Sar period o conrol he primary curren by means of a duy cycle limiaion. The Sof Sar funcion is a buil-in funcion and i is conrolled by an inernal couner.. Figure 11 Sof Sar Circui Afer he IC is swiched on, he V SFOFTS volage is conrolled such ha he volage is increased sepwisely (32 seps) wih he increase of he couns. The Sof Sar couner would send a signal o he curren sink conrol in every 600us such ha he curren sink decrease gradually and he duy raio of he gae drive increases gradually. The Sof Sar will be finished in 20ms ( Sof-Sar ) afer he IC is swiched on. A he end of he Sof Sar period, he curren sink is swiched off. V SofS Sof-Sar VSOFTS32 V SofS V SofS2 V SofS1 Gae Driver Figure 10 Sof Sar Phase Figure 12 Gae drive signal under Sof-Sar Phase Version 2.5 11 19 Nov 2012

Funcional Descripion Wihin he sof sar period, he duy cycle is increasing from zero o maximum gradually (see Figure 12). In addiion o Sar-Up, Sof-Sar is also acivaed a each resar aemp during Auo Resar. 3.5 PWM Secion Oscillaor 0.75 PWM Secion V SOFTS32 V SofS Sof-Sar Duy Cycle max Clock Frequency Jier V FB 4.0V V OUT Sof Sar Block Sof Sar Comparaor PWM Comparaor 1 G8 FF1 S R Q Gae Driver G9 V OUT Curren Limiing Sar-Up Figure 13 Sar Up Phase The Sar-Up ime Sar-Up before he converer oupu volage V OUT is seled, mus be shorer han he Sof- Sar Phase Sof-Sar (see Figure 13). By means of Sof-Sar here is an effecive minimizaion of curren and volage sresses on he inegraed CoolMOS, he clamp circui and he oupu overshoo and i helps o preven sauraion of he ransformer during Sar-Up. Figure 14 PWM Secion Block CoolMOS Gae 3.5.1 Oscillaor The oscillaor generaes a fixed frequency of 65KHz wih frequency jiering of ±4% (which is ±2.6KHz) a a jiering period of 4ms. A capacior, a curren source and curren sink which deermine he frequency are inegraed. In order o achieve a very accurae swiching frequency, he charging and discharging curren of he implemened oscillaor capacior are inernally rimmed. The raio of conrolled charge o discharge curren is adjused o reach a maximum duy cycle limiaion of D max =0.75. Once he Sof Sar period is over and when he IC goes ino normal operaing mode, he swiching frequency of he clock is varied by he conrol signal from he Sof Sar block. Then he swiching frequency is varied in range of 65KHz ± 2.6KHz a period of 4ms. 3.5.2 PWM-Lach FF1 The oupu of he oscillaor block provides coninuous pulse o he PWM-Lach which urns on/off he inegraed CoolMOS. Afer he PWM-Lach is se, i is rese by he PWM comparaor, he Sof Sar comparaor or he Curren -Limi comparaor. When i is in rese mode, he oupu of he driver is shu down immediaely. Version 2.5 12 19 Nov 2012

Funcional Descripion 3.5.3 Gae Driver 3.6 Curren Limiing PWM-Lach VCC 1 PWM Lach FF1 Curren Limiing Gae Propagaion-Delay Compensaion Gae Driver Figure 15 Gae Driver CoolMOS The driver-sage is opimized o minimize EMI and o provide high circui efficiency. The swich on speed is slowed down before i reaches he inegraed CoolMOS urn on hreshold. Tha is a slope conrol of he rising edge a he oupu of he driver (see Figure 16). PWM-OP G10 Acive Burs Mode C10 C12 Vcsh 0.34V 10k D1 Leading Edge Blanking 220ns 1pF (inernal) V Gae 5V ca. = 130ns Figure 16 Gae Rising Slope Thus he leading swich on spike is minimized. Furhermore he driver circui is designed o eliminae cross conducion of he oupu sage. During power up, when VCC is below he undervolage lockou hreshold V VCCoff, he oupu of he Gae Driver is se o low in order o disable power ransfer o he secondary side. CS Figure 17 Curren Limiing Block There is a cycle by cycle peak curren limiing operaion realized by he Curren-Limi comparaor C10. The source curren of he inegraed CoolMOS is sensed via an exernal sense resisor R Sense. By means of R Sense he source curren is ransformed o a sense volage V Sense which is fed ino he CS pin. If he volage V Sense exceeds he inernal hreshold volage V csh, he comparaor C10 immediaely urns off he gae drive by reseing he PWM Lach FF1. A Propagaion Delay Compensaion is added o suppor he immediae shu down of he inegraed CoolMOS wih very shor propagaion delay. Thus he influence of he AC inpu volage on he maximum oupu power can be reduced o minimal. In order o preven he curren limi from disorions caused by leading edge spikes, a Leading Edge Blanking is inegraed in he curren sense pah for he comparaors C10, C12 and he PWM-OP. The oupu of comparaor C12 is acivaed by he Gae G10 if Acive Burs Mode is enered. When i is acivaed, he curren limiing is reduced o 0.34V. This volage level deermines he maximum power level in Acive Burs Mode. Version 2.5 13 19 Nov 2012

Funcional Descripion 3.6.1 Leading Edge Blanking V Sense V csh LEB = 220ns For example, I peak = 0.5A wih R Sense = 2. The curren sense hreshold is se o a saic volage level V csh =1V wihou Propagaion Delay Compensaion. A curren ramp of di/d = 0.4A/µs, or dv Sense /d = 0.8V/µs, and a propagaion delay ime of Propagaion Delay =180ns leads o an I peak overshoo of 14.4%. Wih he propagaion delay compensaion, he overshoo is only around 2% (see Figure 20). wih compensaion wihou compensaion Figure 18 Leading Edge Blanking Whenever he inegraed CoolMOS is swiched on, a leading edge spike is generaed due o he primaryside capaciances and reverse recovery ime of he secondary-side recifier. This spike can cause he gae drive o swich off uninenionally. In order o avoid a premaure erminaion of he swiching pulse, his spike is blanked ou wih a ime consan of LEB = 220ns. 3.6.2 Propagaion Delay Compensaion In case of over-curren deecion, here is always propagaion delay o swich off he inegraed CoolMOS. An overshoo of he peak curren I peak is induced o he delay, which depends on he raio of di/ d of he peak curren (see Figure 19). V Sense V 1,3 1,25 1,2 1,15 1,1 1,05 1 0,95 0,9 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 dv Sense d Figure 20 Overcurren Shudown The Propagaion Delay Compensaion is realized by means of a dynamic hreshold volage V csh (see Figure 21). In case of a seeper slope he swich off of he driver is earlier o compensae he delay. V μs Signal2 Signal1 V OSC max. Duy Cycle I Sense Propagaion Delay I peak2 I peak1 I Overshoo2 off ime I Limi I Overshoo1 V Sense Propagaion Delay V csh Figure 19 Curren Limiing The overshoo of Signal2 is larger han of Signal1 due o he seeper rising waveform. This change in he slope depends on he AC inpu volage. Propagaion Delay Compensaion is inegraed o reduce he overshoo due o di/d of he rising primary curren. Thus he propagaion delay ime beween exceeding he curren sense hreshold V csh and he swiching off of he inegraed CoolMOS is compensaed over emperaure wihin a wide range. Curren Limiing is hen very accurae. Figure 21 Signal1 Signal2 Dynamic Volage Threshold V csh Version 2.5 14 19 Nov 2012

Funcional Descripion 3.7 Conrol Uni The Conrol Uni conains he funcions for Acive Burs Mode and Auo Resar Mode. The Acive Burs Mode and he Auo Resar Mode boh have 20ms inernal Blanking Time. For he Auo Resar Mode, a furher exendable Blanking Time is achieved by adding exernal capacior a BA pin. By means of his Blanking Time, he IC avoids enering ino hese wo modes accidenally. Furhermore hose buffer ime for he overload deecion is very useful for he applicaion ha works in low curren bu requires a shor duraion of high curren occasionally. 3.7.1 Basic and Exendable Blanking Mode BA # C BK I BK 5.0V Afer he 30us spike blanking ime, he Auo Resar Mode is acivaed. For example, if C BK = 0.22uF, I BK = 13uA Blanking ime = 20ms + C BK x (4.0-0.9) / I BK = 72ms In order o make he sarup properly, he maximum C BK capacior is resriced o less han 0.65uF. The Acive Burs Mode has basic blanking mode only while he Auo Resar Mode has boh he basic and he exendable blanking mode. 3.7.2 Acive Burs Mode The IC eners Acive Burs Mode under low load condiions. Wih he Acive Burs Mode, he efficiency increases significanly a ligh load condiions while sill mainaining a low ripple on V OUT and a fas response on load jumps. During Acive Burs Mode, he IC is conrolled by he FB signal. Since he IC is always acive, i can be a very fas response o he quick change a he FB signal. The Sar up Cell is kep OFF in order o minimize he power loss. 0.9V S1 1 G2 Inernal Bias 4.0V C3 Spike Blanking 30us 20 ms Blanking Time Curren Limiing G10 4.0V C4 20ms Blanking Time G5 Auo Resar Mode 4.0V C4 FB 1.35V C5 20ms Blanking Time G6 Acive Burs Mode FB 1.35V C5 G6 Acive Burs Mode Conrol Uni 3.5V C6a Figure 22 Basic and Exendable Blanking Mode There are 2 kinds of Blanking mode; basic mode and he exendable mode. The basic mode is jus an inernal se 20ms blanking ime while he exendable mode has an exra blanking ime by connecing an exernal capacior o he BA pin in addiion o he prese 20ms blanking ime. For he exendable mode, he gae G5 is blocked even hough he 20ms blanking ime is reached if an exernal capacior C BK is added o BA pin. While he 20ms blanking ime is passed, he swich S1 is opened by G2. Then he 0.9V clamped volage a BA pin is charged o 4.0V hrough he inernal I BK consan curren. G5 is enabled by comparaor C3. Figure 23 3.0V C6b Conrol Uni Acive Burs Mode G11 The Acive Burs Mode is locaed in he Conrol Uni. Figure 23 shows he relaed componens. 3.7.2.1 Enering Acive Burs Mode The FB signal is kep monioring by he comparaor C5. During normal operaion, he inernal blanking ime couner is rese o 0. Once he FB signal falls below 1.35V, i sars o coun. When he couner reach 20ms Version 2.5 15 19 Nov 2012

Funcional Descripion and FB signal is sill below 1.35V, he sysem eners he Acive Burs Mode. This ime window prevens a sudden enering ino he Acive Burs Mode due o large load jumps. Afer enering Acive Burs Mode, a burs flag is se and he inernal bias is swiched off in order o reduce he curren consumpion of he IC o approx. 450uA. I needs he applicaion o enforce he VCC volage above he Undervolage Lockou level of 10.5V such ha he Sarup Cell will no be swiched on accidenally. Or oherwise he power loss will increase drasically. The minimum VCC level during Acive Burs Mode depends on he load condiion and he applicaion. The lowes VCC level is reached a no load condiion. V FB 4.0V 3.5V 3.0V 1.35V Blanking Timer Enering Acive Burs Mode 20ms Blanking Time Leaving Acive Burs Mode 3.7.2.2 Working in Acive Burs Mode Afer enering he Acive Burs Mode, he FB volage rises as V OUT sars o decrease, which is due o he inacive PWM secion. The comparaor C6a moniors he FB signal. If he volage level is larger han 3.5V, he inernal circui will be acivaed; he Inernal Bias circui resumes and sars o provide swiching pulse. In Acive Burs Mode he gae G10 is released and he curren limi is reduced o 0.34V, which can reduce he conducion loss and he audible noise. If he load a V OUT is sill kep unchanged, he FB signal will drop o 3.0V. A his level he C6b deacivaes he inernal circui again by swiching off he inernal Bias. The gae G11 is acive again as he burs flag is se afer enering Acive Burs Mode. In Acive Burs Mode, he FB volage is changing like a saw ooh beween 3.0V and 3.5V (see figure 24). V CS 1.03V 0.34V V VCC Curren limi level during Acive Burs Mode 3.7.2.3 Leaving Acive Burs Mode The FB volage will increase immediaely if here is a high load jump. This is observed by he comparaor C4. Since he curren limi is app. 34% during Acive Burs Mode, i needs a cerain load jump o rise he FB signal o exceed 4.0V. A ha ime he comparaor C4 reses he Acive Burs Mode conrol which in urn blocks he comparaor C12 by he gae G10. The maximum curren can hen be resumed o sabilize he V OUT. 10.5V I VCC 2.5mA 450uA V OUT Figure 24 Signals in Acive Burs Mode Version 2.5 16 19 Nov 2012

Funcional Descripion 3.7.3 Proecion Modes The IC provides Auo Resar Mode as he proecion feaure. Auo Resar mode can preven he SMPS from desrucive saes. The following able shows he relaionship beween possible sysem failures and he corresponding proecion modes. 3.7.3.1 Auo Resar mode wih exended blanking ime BA 5.0V VCC Overvolage Overemperaure Overload Open Loop VCC Undervolage Shor Opocoupler Auo resar enable Auo Resar Mode Auo Resar Mode Auo Resar Mode Auo Resar Mode Auo Resar Mode Auo Resar Mode Auo Resar Mode # C BK I BK 0.9V S1 1 G2 C3 4.0V Spike Blanking 30us Before enering he Auo Resar proecion mode, some of he proecions can have exended blanking ime o delay he proecion and some needs o fas reac and will go sraigh o he proecion. Overload and open loop proecion are he one can have exended blanking ime while Vcc Overvolage, Over emperaure, Vcc Undervolage, shor opo-coupler and exernal auo resar enable will go o proecion righ away. Afer he sysem eners he Auo-resar mode, he IC will be off. Since here is no more swiching, he Vcc volage will drop. When i his he Vcc urn off hreshold, he sar up cell will urn on and he Vcc is charged by he sarup cell curren o Vcc urn on hreshold. The IC is on and he sarup cell will urn off. A his sage, i will ener he sarup phase (sof sar) wih swiching cycles. Afer he Sar Up Phase, he faul condiion is checked. If he faul condiion persiss, he IC will go o auo resar mode again. If, oherwise, he faul is removed, normal operaion is resumed. 4.0V FB C4 20ms Blanking Time Figure 25 Auo Resar Mode In case of Overload or Open Loop, he FB exceeds 4.0V which will be observed by comparaor C4. Then he inernal blanking couner sars o coun. When i reaches 20ms, he swich S1 is released. Then he clamped volage 0.9V a V BA can increase. When here is no exernal capacior C BK conneced, he V BA will reach 4.0V immediaely. When boh he inpu signals a AND gae G5 is posiive, he Auo Resar Mode will be acivaed afer he exra spike blanking ime of 30us is elapsed. However, when an exra blanking ime is needed, i can be achieved by adding an exernal capacior, C BK. A consan curren source of I BK will sar o charge he capacior C BK from 0.9V o 4.0V afer he swich S1 is released. The charging ime from 0.9V o 4.0V are he exendable blanking ime. If C BK is 0.22uF and I BK is 13uA, he exendable blanking ime is around 52ms and he oal blanking ime is 72ms. In combining he FB and blanking ime, here is a blanking window generaed which prevens he sysem o ener Auo Resar Mode due o large load jumps. G5 Auo Resar Mode Conrol Uni Version 2.5 17 19 Nov 2012

Funcional Descripion 3.7.3.2 Auo Resar wihou exended blanking ime BA Auo-resar Enable Signal T AE 0.3V 25.5V VCC C9 C2 1ms couner 8us Blanking Time 120us Blanking Time UVLO Sop gae drive Auo Resar Mode Rese VVCC < 10.5V Auo Resar mode a rigger signal o he base of he exernally added ransisor, T AE a he BA pin. When he funcion is enabled, he gae drive swiching will be sopped and hen he IC will ener auo-resar mode if he signal persiss. To ensure his auo-resar funcion will no be mis-riggered during sar up, a 1ms delay ime is implemened o blank he unsable signal. VCC undervolage is he Vcc volage drop below Vcc urn off hreshold. Then he IC will urn off and he sar up cell will urn on auomaically. And his leads o Auo Resar Mode. Shor Opocoupler also leads o VCC undervolage as here is no self supply afer acivaing he inernal reference and bias. VCC C1 20.5V sofs_period G1 Spike Blanking 30us FB 4.0V C4 Thermal Shudown Volage Reference Tj >140 C Conrol Uni Figure 26 Auo Resar mode There are 2 modes of V CC overvolage proecion; one is during sof sar and he oher is a all condiions. The firs one is V VCC volage is > 20.5V and FB is > 4.0V and during sof_sar period and he IC eners Auo Resar Mode. The VCC volage is observed by comparaor C1 and C4. The faul condiions are o deec he abnormal operaing during sar up such as open loop during ligh load sar up, ec. The logic can eliminae he possible of enering Auo Resar mode if here is a small volage overshoos of V VCC during normal operaing. The 2nd one is V VCC >25.5V and las for 120us and he IC eners Auo Resar Mode. This 25.5V Vcc OVP proecion is inacivaed during burs mode. The Thermal Shudown block moniors he juncion emperaure of he IC. Afer deecing a juncion emperaure higher han 130 C, he Auo Resar Mode is enered. In case he pre-defined auo-resar feaures are no sufficien, here is a cusomer defined exernal Auoresar Enable feaure. This funcion can be riggered by pulling down he BA pin o < 0.33V. I can simply add Version 2.5 18 19 Nov 2012

Elecrical Characerisics 4 Elecrical Characerisics Noe: All volages are measured wih respec o ground (Pin 5). The volage levels are valid if oher raings are no violaed. 4.1 Absolue Maximum Raings Noe: Absolue maximum raings are defined as raings, which when being exceeded may lead o desrucion of he inegraed circui. For he same reason make sure, ha any capacior ha will be conneced o pin 4 (VCC) is discharged before assembling he applicaion circui.t a =25 C unless oherwise specified. Parameer Symbol Limi Values Uni Remarks Swiching drain curren, pulse widh p limied by T j =150 C Pulse drain curren, pulse widh p limied by T j =150 C Avalanche energy, repeiive AR limied by max. T j =150 C 1) 1) min. max. I s - 1.67 A I D_Puls - 2.32 A E AR - 0.01 mj Avalanche curren, repeiive AR limied by I AR - 0.5 A max. T j =150 C 1) VCC Supply Volage V VCC -0.3 27 V FB Volage V FB -0.3 5.5 V BA Volage V BA -0.3 5.5 V CS Volage V CS -0.3 5.5 V Juncion Temperaure T j -40 150 C Conroller CoolMOS Sorage Temperaure T S -55 150 C Thermal Resisance R hja - 90 K/W Juncion -Ambien Soldering emperaure, wavesoldering only allowed a leads T sold - 260 C 1.6mm (0.063in.) from case for 10s ESD Capabiliy (incl. Drain Pin) V ESD - 2 kv Human body model 2) Repeiive avalanche causes addiional power losses ha can be calculaed as P AV =E AR *f 2) According o EIA/JESD22-A114-B (discharging a 100pF capacior hrough a 1.5kΩ series resisor) Version 2.5 19 19 Nov 2012

Elecrical Characerisics 4.2 Operaing Range Noe: Wihin he operaing range he IC operaes as described in he funcional descripion. Parameer Symbol Limi Values Uni Remarks min. max. VCC Supply Volage V VCC V VCCoff 25 V Max value limied due o Vcc OVP Juncion Temperaure of Conroller T jcon -25 130 C Max value limied due o hermal shu down of conroller Juncion Temperaure of T jcoolmos -25 150 C CoolMOS 4.3 Characerisics 4.3.1 Supply Secion Noe: The elecrical characerisics involve he spread of values wihin he specified supply volage and juncion emperaure range T J from 25 C o 125 C. Typical values represen he median values, which are relaed o 25 C. If no oherwise saed, a supply volage of V CC = 18 V is assumed. Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Sar Up Curren I VCCsar - 150 250 μa V VCC =17V VCC Charge Curren I VCCcharge1 - - 5.0 ma V VCC = 0V I VCCcharge2 0.55 0.9 1.60 ma V VCC = 1V I VCCcharge3-0.7 - ma V VCC =17V Leakage Curren of Sar Up Cell and CoolMOS I SarLeak - 0.2 50 μa V Drain = 450V a T j =100 C Supply Curren wih Inacive Gae I VCCsup1-1.5 2.5 ma Supply Curren wih Acive Gae I VCCsup2-2.5 3.4 ma I FB = 0A Supply Curren in Auo Resar Mode wih Inacive Gae Supply Curren in Acive Burs Mode wih Inacive Gae I VCCresar - 250 - μa I FB = 0A I VCCburs1-450 950 μa V FB = 2.5V I VCCburs2-450 950 μa V VCC = 11.5V,V FB = 2.5V VCC Turn-On Threshold VCC Turn-Off Threshold VCC Turn-On/Off Hyseresis V VCCon V VCCoff V VCChys 17.0 9.8-18.0 10.5 7.5 19.0 11.2 - V V V Version 2.5 20 19 Nov 2012

Elecrical Characerisics 4.3.2 Inernal Volage Reference Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Trimmed Reference Volage V REF 4.90 5.00 5.10 V measured a pin FB I FB = 0 4.3.3 PWM Secion Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Fixed Oscillaor Frequency f OSC1 56.5 65.0 73.5 khz f OSC2 59.8 65.0 70.2 khz T j = 25 C Frequency Jiering Range f jier - ±2.6 - khz T j = 25 C Frequency Jiering period T jier - 4.0 - ms T j = 25 C Max. Duy Cycle D max 0.70 0.75 0.80 Min. Duy Cycle D min 0 - - V FB < 0.3V PWM-OP Gain A V 3.1 3.3 3.5 Volage Ramp Offse V Offse-Ramp - 0.67 - V V FB Operaing Range Min Level V FBmin - 0.5 - V V FB Operaing Range Max level V FBmax - - 4.3 V CS=1V, limied by Comparaor C4 1) FB Pull-Up Resisor R FB 9 15.4 22 kω 1) The parameer is no subjeced o producion es - verified by design/characerizaion 4.3.4 Sof Sar ime Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Sof Sar ime SS - 20.0 - ms Version 2.5 21 19 Nov 2012

Elecrical Characerisics 4.3.5 Conrol Uni Parameer Symbol Limi Values Uni Tes Condiion Clamped V BA volage during Normal Operaing Mode Blanking ime volage limi for Comparaor C3 Over Load Open Loop Deecion Limi for Comparaor C4 Acive Burs Mode Level for Comparaor C5 Acive Burs Mode Level for Comparaor C6a Acive Burs Mode Level for Comparaor C6b Overvolage Deecion Limi for Comparaor C1 min. yp. max. V BAclmp 0.85 0.9 0.95 V V FB = 4V V BKC3 3.85 4.00 4.15 V V FBC4 3.85 4.00 4.15 V V FBC5 1.25 1.35 1.45 V V FBC6a 3.35 3.50 3.65 V Afer Acive Burs Mode is enered V FBC6b 2.88 3.00 3.12 V Afer Acive Burs Mode is enered V VCCOVP1 19.5 20.5 21.5 V V FB = 5V Overvolage Deecion Limi for Comparaor C2 V VCCOVP2 25.0 25.5 26.5 V Auo-resar Enable level a BA pin V AE 0.25 0.33 0.4 V >30μs Charging curren a BA pin I BK 10.0 13.0 16.9 μa Charge sars afer he buil-in 20ms blanking ime elapsed Thermal Shudown 1) T jsd 130 140 150 C Conroller Buil-in Blanking Time for Overload Proecion or ener Acive Burs Mode Inhibi Time for Auo-Resar enable funcion during sar up Spike Blanking Time before Auo- Resar Proecion BK - 20 - ms wihou exernal capacior a BA pin IHAE - 1.0 - ms Coun when VCC>18V Spike - 30 - μs 1) The parameer is no subjeced o producion es - verified by design/characerizaion. The hermal shudown emperaure refers o he juncion emperaure of he conroller. Noe: The rend of all he volage levels in he Conrol Uni is he same regarding he deviaion excep V VCCOVP. Version 2.5 22 19 Nov 2012

Elecrical Characerisics 4.3.6 Curren Limiing Parameer Symbol Limi Values Uni Tes Condiion Peak Curren Limiaion (incl. Propagaion Delay) Peak Curren Limiaion during Acive Burs Mode min. yp. max. V csh 0.96 1.03 1.10 V dv sense / d = 0.6V/μs (see Figure 20) V CS2 0.29 0.34 0.38 V Leading Edge Blanking LEB - 220 - ns CS Inpu Bias Curren I CSbias -1.5-0.2 - μa V CS =0V 4.3.7 CoolMOS Secion Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Drain Source Breakdown Volage V (BR)DSS 650 - - V T j = 110 C Refer o Figure 30 for oher V (BR)DSS in differen T j Drain Source On-Resisance R DSon - - 1) 4.70 10.0 5.44 12.5 The parameer is no subjeced o producion es - verified by design/characerizaion 2) Measured in a Typical Flyback Converer Applicaion Ω Ω T j = 25 C T j =125 C 1) a I D = 0.5A Effecive oupu capaciance, energy C o(er) - 4.75 - pf V DS = 0V o 480V 1) relaed Rise Time rise - 30 2) - ns Fall Time fall - 30 2) - ns Version 2.5 23 19 Nov 2012

Typical CoolMOS Performance Characerisic 5 Typical CoolMOS Performance Characerisic 10 Safe Operaing Area for ICE3A(B)R4765J I D = f ( V DS ) parameer : D = 0, T C = 25deg.C 1 ID [A] 0.1 0.01 p = 0.1ms p = 1ms p = 10ms p = 100ms p = 1000ms DC 0.001 1 10 100 1000 V DS [V] Figure 27 Safe Operaing area (SOA) curve for 120 SOA emperaure deraing coefficien curve ( package dissipaion ) for F3 F2 CoolSET SOA emperaure deraing coefficien [%] 100 80 60 40 20 Figure 28 0 0 20 40 60 80 100 120 140 Ambien/Case emperaure Ta/Tc [deg.c] Ta : DIP, Tc : TO220 SOA emperaure deraing coefficien curve Version 2.5 24 19 Nov 2012

Typical CoolMOS Performance Characerisic 1.6 Allowable Power Dissipaion for F3 CoolSET in DIP-8 package 1.4 Allowable Power Dissipaion, P o [W] 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 20 40 60 80 100 120 140 Ambien emperaure, T a [deg.c] Figure 29 Power dissipaion; P o =f(t a ) 700 660 V BR(DSS) [V] 620 580 540-60 -20 20 60 100 140 180 T j [ C] Figure 30 Drain-source breakdown volage; V BR(DSS) =f(t j ) Version 2.5 25 19 Nov 2012

Inpu Power Curve 6 Inpu Power Curve Two inpu power curves giving he ypical inpu power versus ambien emperaure are showed below; Vin=85Vac~265Vac (Figure 31) and Vin=230Vac+/-15% (Figure 32). The curves are derived based on a ypical disconinuous mode flyback model which considers eiher 50% maximum duy raio or 100V maximum secondary o primary refleced volage (higher prioriy). The calculaion is based on no copper area as heasink for he device. The inpu power already includes he power loss a inpu common mode choke, bridge recifier and he CoolMOS.The device sauraion curren (I D_Puls @ T j =125 C) is also considered. To esimae he oupu power of he device, i is simply muliplying he inpu power a a paricular operaing ambien emperaure wih he esimaed efficiency for he applicaion. For example, a wide range inpu volage (Figure 31), operaing emperaure is 50 C, esimaed efficiency is 85%, hen he esimaed oupu power is 15.6W (18.4W * 85%). 27 Inpu power (85~265Vac) [W] 24 21 18 15 12 9 6 3 PI-009-_85Vac 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Ambien Temperaure [ C] Figure 31 Inpu power curve Vin=85~265Vac; P in =f(t a ) 33 30 Inpu power (230Vac) [W] 27 24 21 18 15 12 9 6 3 PI-0010-_230Vac 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Ambien Temperaure [ C] Figure 32 Inpu power curve Vin=230Vac+/-15%; P in =f(t a ) Version 2.5 26 19 Nov 2012

Ouline Dimension 7 Ouline Dimension PG-DIP-8 (Plasic Dual In-Line Ouline) Figure 33 PG-DIP-8 (Pb-free lead plaing Plasic Dual-in-Line Ouline) Version 2.5 27 19 Nov 2012

Marking 8 Marking Marking Figure 34 Marking for Version 2.5 28 19 Nov 2012

Schemaic for recommended PCB layou 9 Schemaic for recommended PCB layou TR1 L Spark Gap 1 FUSE1 X-CAP C1 Spark Gap 3 L1 BR1 C11 bulk cap R11 D11 C12 D21 C21 Vo GND Spark Gap 2 N C2 Y-CAP C3 Spark Gap 4 Y-CAP C4 Y-CAP D11 R12 CS BA IC11 DRAIN F3 VCC CoolSET Z11 R13 R14 C16 D13 R23 R22 R21 GND GND FB NC C22 C13 C15 * C14 C23 R24 IC12 IC21 F3 CoolSET schemaic for recommended PCB layou R25 Figure 35 Schemaic for recommended PCB layou General guideline for PCB layou design using F3/F3R CoolSET (refer o Figure 35): 1. Sar Ground a bulk capacior ground, C11: Sar Ground means all primary DC grounds should be conneced o he ground of bulk capacior C11 separaely in one poin. I can reduce he swiching noise going ino he sensiive pins of he CoolSET device effecively. The primary DC grounds include he followings. a. DC ground of he primary auxiliary winding in power ransformer, TR1, and ground of C16 and Z11. b. DC ground of he curren sense resisor, R12 c. DC ground of he CoolSET device, GND pin of IC11; he signal grounds from C13, C14, C15 and collecor of IC12 should be conneced o he GND pin of IC11 and hen sar connec o he bulk capacior ground. d. DC ground from bridge recifier, BR1 e. DC ground from he bridging Y-capacior, C4 2. High volage races clearance: High volage races should keep enough spacing o he nearby races. Oherwise, arcing would incur. a. 400V races (posiive rail of bulk capacior C11) o nearby race: > 2.0mm b. 600V races (drain volage of CoolSET IC11) o nearby race: > 2.5mm 3. Filer capacior close o he conroller ground: Filer capaciors, C13, C14 and C15 should be placed as close o he conroller ground and he conroller pin as possible so as o reduce he swiching noise coupled ino he conroller. Guideline for PCB layou design when >3KV lighning surge es applied (refer o Figure 35): 1. Add spark gap Spark gap is a pair of saw-ooh like copper plae facing each oher which can discharge he accumulaed charge during surge es hrough he sharp poin of he saw-ooh plae. a. Spark Gap 3 and Spark Gap 4, inpu common mode choke, L1: Gap separaion is around 1.5mm (no safey concern) Version 2.5 29 19 Nov 2012

Schemaic for recommended PCB layou b. Spark Gap 1 and Spark Gap 2, Live / Neural o GROUND: These 2 Spark Gaps can be used when he lighning surge requiremen is >6KV. 230Vac inpu volage applicaion, he gap separaion is around 5.5mm 115Vac inpu volage applicaion, he gap separaion is around 3mm 2. Add Y-capacior (C2 and C3) in he Live and Neural o ground even hough i is a 2-pin inpu 3. Add negaive pulse clamping diode, D11 o he Curren sense resisor, R12: The negaive pulse clamping diode can reduce he negaive pulse going ino he CS pin of he CoolSET and reduce he abnormal behavior of he CoolSET. The diode can be a fas speed diode such as IN4148. The principle behind is o drain he high surge volage from Live/Neural o Ground wihou passing hrough he sensiive componens such as he primary conroller, IC11. Version 2.5 30 19 Nov 2012

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