CoolSET F3R80 ICE3AR0680VJZ

Transcription

1 Off-Line SMPS Curren Mode Conroller wih inegraed 800V CoolMOS and Sarup cell (inpu OVP & frequenc y jier) in DIP -7 Daa Shee V Power Managemen & Mulimarke

2 Ediion Published by Infineon Technologies AG, Munich, Germany Infineon Technologies AG All Righs Reserved. LEGAL DISCLAIMER THE INFORMATION GIVEN IN THIS APPLICATION NOTE IS GIVEN AS A HINT FOR THE IMPLEMENTATION OF THE INFINEON TECHNOLOGIES COMPONENT ONLY AND SHALL NOT BE REGARDED AS ANY DESCRIPTION OR WARRANTY OF A CERTAIN FUNCTIONALITY, CONDITION OR QUALITY OF THE INFINEON TECHNOLOGIES COMPONENT. THE RECIPIENT OF THIS APPLICATION NOTE MUST VERIFY ANY FUNCTION DESCRIBED HEREIN IN THE REAL APPLICATION. INFINEON TECHNOLOGIES HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND (INCLUDING WITHOUT LIMITATION WARRANTIES OF NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY) WITH RESPECT TO ANY AND ALL INFORMATION GIVEN IN THIS APPLICATION NOTE. Informaion For furher informaion on echnology, delivery erms and condiions and prices, please conac he neares Infineon Technologies Office ( Warnings Due o echnical requiremens, componens may conain dangerous subsances. For informaion on he ypes in quesion, please conac he neares Infineon Technologies Office. Infineon Technologies componens may be used in life-suppor devices or sysems only wih he express wrien approval of Infineon Technologies, if a failure of such componens can reasonably be expeced o cause he failure of ha life-suppor device or sysem or o affec he safey or effeciveness of ha device or sysem. Life suppor devices or sysems are inended o be implaned in he human body or o suppor and/or mainain and susain and/or proec human life. If hey fail, i is reasonable o assume ha he healh of he user or oher persons may be endangered.

3 Trademarks of Infineon Technologies AG AURIX, C166, CanPAK, CIPOS, CIPURSE, EconoPACK, CoolMOS, CoolSET, CORECONTROL, CROSSAVE, DAVE, DI-POL, EasyPIM, EconoBRIDGE, EconoDUAL, EconoPIM, EconoPACK, EiceDRIVER, eupec, FCOS, HITFET, HybridPACK, I²RF, ISOFACE, IsoPACK, MIPAQ, ModSTACK, my-d, NovalihIC, OpiMOS, ORIGA, POWERCODE ; PRIMARION, PrimePACK, PrimeSTACK, PRO-SIL, PROFET, RASIC, ReverSave, SaRIC, SIEGET, SINDRION, SIPMOS, SmarLEWIS, SOLID FLASH, TEMPFET, hinq!, TRENCHSTOP, TriCore. Oher Trademarks Advance Design Sysem (ADS) of Agilen Technologies, AMBA, ARM, MULTI-ICE, KEIL, PRIMECELL, REALVIEW, THUMB, µvision of ARM Limied, UK. AUTOSAR is licensed by AUTOSAR developmen parnership. Blueooh of Blueooh SIG Inc. CAT-iq of DECT Forum. COLOSSUS, FirsGPS of Trimble Navigaion Ld. EMV of EMVCo, LLC (Visa Holdings Inc.). EPCOS of Epcos AG. FLEXGO of Microsof Corporaion. FlexRay is licensed by FlexRay Consorium. HYPERTERMINAL of Hilgraeve Incorporaed. IEC of Commission Elecroechnique Inernaionale. IrDA of Infrared Daa Associaion Corporaion. ISO of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB of MahWorks, Inc. MAXIM of Maxim Inegraed Producs, Inc. MICROTEC, NUCLEUS of Menor Graphics Corporaion. MIPI of MIPI Alliance, Inc. MIPS of MIPS Technologies, Inc., USA. muraa of MURATA MANUFACTURING CO., MICROWAVE OFFICE (MWO) of Applied Wave Research Inc., OmniVision of OmniVision Technologies, Inc. Openwave Openwave Sysems Inc. RED HAT Red Ha, Inc. RFMD RF Micro Devices, Inc. SIRIUS of Sirius Saellie Radio Inc. SOLARIS of Sun Microsysems, Inc. SPANSION of Spansion LLC Ld. Symbian of Symbian Sofware Limied. TAIYO YUDEN of Taiyo Yuden Co. TEAKLITE of CEVA, Inc. TEKTRONIX of Tekronix Inc. TOKO of TOKO KABUSHIKI KAISHA TA. UNIX of X/Open Company Limied. VERILOG, PALLADIUM of Cadence Design Sysems, Inc. VLYNQ of Texas Insrumens Incorporaed. VXWORKS, WIND RIVER of WIND RIVER SYSTEMS, INC. ZETEX of Diodes Zeex Limied. Las Trademarks Updae Daa Shee 3 V2.1,

4 Revision Hisory Major changes since previous revision Dae Version Changed By Change Descripion 22 Oc New daashee forma We Lisen o Your Commens Is here any informaion in his documen ha you feel is wrong, unclear or missing? Your feedback will help us o coninuously improve he qualiy of our documenaion. Please send your proposal (including a reference o his documen ile/number) o: cdd@infineon.com Daa Shee 4 V2.1,

5 Table of Conens Revision Hisory... 4 Table of Conens... 5 Off-Line SMPS Curren Mode Conroller wih inegraed 800V CoolMOS and Sarup cell (inpu OVP & frequency jier) in DIP Pin Configuraion and Funcionaliy Pin Configuraion wih PG-DIP Pin Funcionaliy Represenaive Block Diagram Funcional Descripion Inroducion Power Managemen Improved Curren Mode PWM-OP PWM-Comparaor Sarup Phase PWM Secion Oscillaor PWM-Lach FF Gae Driver Curren Limiing Leading Edge Blanking Propagaion Delay Compensaion (paened) Conrol Uni Basic and Exendable Blanking Mode Acive Burs Mode (paened) Selecable burs enry level Enering Acive Burs Mode Working in Acive Burs Mode Leaving Acive Burs Mode Proecion Modes Vcc OVP, OTP and Vcc under volage Over load, open loop proecion Inpu OVP Mode Acion sequence a BV pin Elecrical Characerisics Absolue Maximum Raings Operaing Range Characerisics Supply Secion Inernal Volage Reference PWM Secion Sof Sar ime Conrol Uni Curren Limiing Daa Shee 5 V2.1,

6 4.3.7 CoolMOS Secion Typical Conroller Performance Characerisics CoolMOS Performance Characerisics Inpu Power Curve Ouline Dimension Marking Schemaic for recommended PCB layou Daa Shee 6 V2.1,

7 Off-Line SMPS Curren Mode Conroller wih inegraed 800V CoolMOS and Sarup cell (inpu OVP & frequency jier) in DIP-7 Produc Highlighs 800V avalanche rugged CoolMOS wih sarup cell Acive Burs Mode o reach he lowes Sandby Power <100mW Selecable enry and exi burs mode level Adjusable blanking Window for high load jumps Frequency jier and sof driving for low EMI Adjusable inpu OVP Auo Resar proecion for over load, over emperaure and over volage Low Operaing emperaure down o -40 C Pb-free lead plaing, halogen free mold compound, RoHS complian Feaures 800V avalanche rugged CoolMOS wih Sarup Cell Acive Burs Mode for lowes Sandby Power Selecable enry and exi burs mode level 100kHz inernally fixed swiching frequency wih jiering feaure Auo Resar Proecion for Over load, Open Loop, VCC Under volage & Over volage and Over emperaure Over emperaure proecion wih 50 C hyseresis Buil-in 10ms Sof Sar Buil-in 20ms and exendable blanking ime for shor duraion peak power Propagaion delay compensaion for boh maximum load and burs mode Adjusable inpu OVP Overall olerance of Curren Limiing < ±5% BiCMOS echnology for low power consumpion and wide VCC volage range Sof gae drive wih 50Ω urn on resisor Descripion The is a modified version of ICE3ARxx80JZ (CoolSET -F3R 800V) in DIP-7 package. I adds in he inpu OVP feaure bu removes he brownou feaure and exernal proecion enable feaure. In summary, he is a device running a 100kHz, implemened wih inpu OVP feaure, insalled wih 800V MOSFET wih sarup cell and housed in DIP-7 package. I provides good volage margin of MOSFET, lowes sandby power, selecable burs level, reduced oupu ripple during burs mode, robus proecion wih inpu OVP feaure, accurae maximum power conrol for boh maximum power and burs power, low EMI wih frequency jiering and sof gae drive, buil-in and flexible proecions, ec. Applicaions Adaper/Charger Blue Ray/DVD player, Se-op Box, Digial Phoo Frame Auxiliary power supply for Server, PC, Priner, TV, Home heaer/audio Sysem, Whie Goods, ec Typical Applicaion VAC CBulk Snubber + Converer DC Oupu - PG-DIP7 VCC CVCC Drain Power Managemen Sarup Cell ROV1 BV PWM Conroller Curren Mode Precise Low Tolerance Peak Curren Limiaion Conrol Uni Inpu OVP mode Acive Burs Mode Auo Resar Mode CoolMOS CoolSET - F3R80 (Inpu OVP & Jier) CS FBB GND RSense ROV2 Figure 1: Pin configuraion PG-DIP-7(op view) Type Package Marking V DS F OSC 1) R DSon 230VAC ±15% 2) VAC 2) PG-DIP-7 3AR0680VJZ 800V 100kHz W 52W 1) T=25 C 2) Calculaed maximum inpu power raing a T a=50 C, Ti=125 C and wihou copper area as hea sink. Daa Shee 7 V2.1,

8 Pin Configuraion and Funcionaliy 1 Pin Configuraion and Funcionaliy 1.1 Pin Configuraion wih PG-DIP-7 Pin Symbol Funcion 1 BV exended Blanking ime & inpu OVP 2 FBB Feedback & Burs enry/exi conrol 3 CS Curren Sense/ 800V CoolMOS Source 4 n.c. no conneced 5 Drain 800V CoolMOS Drain 6 - (no pin) 7 VCC Conroller Supply Volage 8 GND Conroller Ground BV 1 8 GND FBB 2 7 VCC CS 3 n.c. 4 5 Drain Figure 2: Pin configuraion PG-DIP-7(op view) 1.2 Pin Funcionaliy BV (exended Blanking ime & inpu OVP) The BV pin combines he funcions of inpu OVP and exendable blanking ime for over load proecion. The inpu OVP feaure is o sop he swiching pulse when he inpu line volage is higher han he V OVP_ref afer he resisor divider (Refer o Figure 3). The exendable blanking ime funcion is o exend he buil-in 20 ms blanking ime for over load proecion by adding an exernal capacior o ground. FBB (Feedback & Burs enry conrol) The FBB pin combines he feedback funcion and he burs enry/exi conrol. The regulaion informaion is provided by he FBB pin o he inernal Proecion Uni and he inernal PWM-Comparaor o conrol he duy cycle. The FBB-signal is he only conrol signal in case of ligh load a he Acive Burs Mode. The burs enry/ exi conrol provides an access o selec he enry/exi burs mode level. CS (Curren Sense) The Curren Sense pin senses he volage developed on he shun resisor insered in he source of he inegraed CoolMOS. If CS reaches he inernal hreshold of he Curren Limi Comparaor, he Driver oupu is immediaely swiched off. Furhermore he curren informaion is provided for he PWM comparaor o realize he Curren Mode. Daa Shee 8 V2.1,

9 Pin Configuraion and Funcionaliy Drain (Drain of inegraed CoolMOS ) Pin Drain is he connecion o he Drain of he inegraed CoolMOS. VCC (Power Supply) The VCC pin is he posiive supply of he IC. The operaing range is beween 10.5V and 25V. GND (Ground) The GND pin is he ground of he conroller. Daa Shee 9 V2.1,

10 Represenaive Block Diagram 2 Represenaive Block Diagram Figure 3: Represenaive Block Diagram Daa Shee 10 V2.1,

11 Funcional Descripion 3 Funcional Descripion All values which are used in he funcional descripion are ypical values. For calculaing he wors cases he min/max values which can be found in secion 4 Elecrical Characerisics have o be considered. 3.1 Inroducion inpu OVP and jier 800V version is he modified version of he ICE3ARxx80JZ. I is paricular good for high volage margin low power SMPS applicaion such as whie goods, auxiliary power supply for PC and server. The major characerisics are ha he IC is developed wih 800V CoolMOS wih sar up cell, having adjusable inpu OVP feaure, running a 100kHz swiching frequency and packed in DIP-7 package. The familiar feaures are BiCMOS echnology o reduce power consumpion and increase he Vcc volage range, cycle by cycle curren mode conrol, buil-in 10ms sof sar o reduce he sress of swiching elemens during sar up, buil-in 20ms and exended blanking ime for shor period of peak power before enering proecion, acive burs mode for lowes sandby power and propagaion delay compensaion for close power limi beween high line and low line, frequency jiering for low EMI performance, he buil-in auo-resar mode proecions for open loop, over load, Vcc OVP, Vcc under volage, ec. Besides, i also includes narrowing he feedback volage swing from 0.5V o 0.3V during burs mode so ha he oupu volage ripple can be reduced by 40%, reducion of he fas volage fall ime of he MOSFET by increasing he sof urn-on ime and addiion of 50Ω urn-on resisor, faser sar up ime by opimizing he Vcc capacior o 10uF and over emperaure proecion wih 50 C hyseresis. Furhermore, i includes adjusable inpu OVP o suppress he abnormal inpu sress o damage he device, selecable enry and exi burs mode for smaller enry/exi power o burs mode or even no burs mode is possible and he propagaion delay compensaion for burs mode so ha he enry/exi burs mode power is close beween high line and low line. In summary, he provides good volage margin of MOSFET, lowes sandby power, flexible burs level, reduced oupu ripple during burs mode, robus for abnormal inpu sress wih inpu OVP feaure, accurae power limi for boh maximum power and burs power, low EMI wih frequency jiering and sof gae drive, buil-in and flexible proecions, ec. Therefore, is a complee soluion for he low power SMPS applicaion ypically for whie goods. 3.2 Power Managemen Drain VCC Sarup Cell CoolMOS Power Managemen Inernal Bias Undervolage Lockou 17V 10.5V Power-Down Rese Volage Reference 5.0V Sof Sar block Auo Resar Mode Acive Burs Mode Figure 4: Power Managemen The Undervolage Lockou moniors he exernal supply volage V VCC. When he SMPS is plugged o he main line he inernal Sarup Cell is biased and sars o charge he exernal capacior C VCC which is conneced o he VCC pin. This Daa Shee 11 V2.1,

12 Funcional Descripion VCC charge curren is conrolled o 0.9mA by he Sarup Cell. When he V VCC exceeds he on-hreshold V CCon =17V he bias circui are swiched on. Then he Sarup Cell is swiched off by he Undervolage Lockou and herefore no power losses presen due o he connecion of he Sarup Cell o he Drain volage. To avoid unconrolled ringing a swichon, a hyseresis sar up volage is implemened. The swich-off of he conroller can only ake place when VVCC falls below 10.5V afer normal operaion was enered. The maximum curren consumpion before he conroller is acivaed is abou 200µA. When V VCC falls below he off-hreshold V CCoff =10.5V, he bias circui is swiched off and he sof sar couner is rese. Thus i ensures ha a every sarup cycle he sof sar sars a zero. The inernal bias circui is swiched off if Auo Resar Mode is enered. The curren consumpion is hen reduced o 320µA. Once he malfuncion condiion is removed, his block will hen urn back on. The recovery from Auo Resar Mode does no require re-cycling he AC line. When Acive Burs Mode is enered, he inernal Bias is swiched off mos of he ime bu he Volage Reference is kep alive in order o reduce he curren consumpion below 620µA. 3.3 Improved Curren Mode Sof-Sar Comparaor FBB C8 PWM-Lach R Q Driver S Q 0.6V PWM OP x3.25 Improved Curren Mode CS Figure 5: Curren Mode Curren Mode means he duy cycle is conrolled by he slope of he primary curren. This is done by comparing he FBB signal wih he amplified curren sense signal. Amplified Curren Signal FBB 0.6V Driver on Figure 6: Pulse Widh Modulaion In case he amplified curren sense signal exceeds he FBB signal he on-ime on of he driver is finished by reseing he PWM-Lach (Figure 6). Daa Shee 12 V2.1,

13 Funcional Descripion The primary curren is sensed by he exernal series resisor R Sense insered in he source of he inegraed CoolMOS. By means of Curren Mode regulaion, he secondary oupu volage is insensiive o he line variaions. The curren waveform slope will change wih he line variaion, which conrols he duy cycle. The exernal R Sense allows an individual adjusmen of he maximum source curren of he inegraed CoolMOS. To improve he Curren Mode during ligh load condiions he amplified curren ramp of he PWM-OP is superimposed on a volage ramp, which is buil by he swich T2, he volage source V1 and a resisor R1 (see Figure 7). Every ime he oscillaor shus down for maximum duy cycle limiaion he swich T2 is closed by V OSC. When he oscillaor riggers he Gae Driver, T2 is opened so ha he volage ramp can sar. FBB Sof-Sar Comparaor Oscillaor V OSC T 2 R 1 PWM Comparaor C8 ime delay circui (156ns) 0.6V 10k V 1 PWM-Lach Gae Driver X3.25 PWM OP Volage Ramp Figure 7: Improved Curren Mode In case of ligh load he amplified curren ramp is oo small o ensure a sable regulaion. In ha case he Volage Ramp is a well defined signal for he comparison wih he FBB-signal. The duy cycle is hen conrolled by he slope of he Volage Ramp. By means of he ime delay circui which is riggered by he invered VOSC signal, he Gae Driver is swiched-off unil i reaches approximaely 156ns delay ime (Figure 8). I allows he duy cycle o be reduced coninuously ill 0% by decreasing VFBB below ha hreshold. V OSC max. Duy Cycle Volage Ramp 0.6V FBB Gae Driver 156ns ime delay Figure 8: Ligh Load Condiions Daa Shee 13 V2.1,

14 Funcional Descripion PWM-OP The inpu of he PWM-OP is applied over he inernal leading edge blanking o he exernal sense resisor R Sense conneced o pin CS. R Sense convers he source curren ino a sense volage. The sense volage is amplified wih a gain of 3.25 by PWM OP. The oupu of he PWM-OP is conneced o he volage source V 1. The volage ramp wih he superimposed amplified curren signal is fed ino he posiive inpus of he PWM-Comparaor C8 and he Sof-Sar- Comparaor (Figure 9) PWM-Comparaor The PWM-Comparaor compares he sensed curren signal of he inegraed CoolMOS wih he feedback signal VFBB (Figure 9). V FBB is creaed by an exernal opocoupler or exernal ransisor in combinaion wih he inernal pull-up resisor R FB and provides he load informaion of he feedback circuiry. When he amplified curren signal of he inegraed CoolMOS exceeds he signal V FBB he PWM-Comparaor swiches off he Gae Driver. 5V R FB Sof-Sar Comparaor FBB C8 PWM-Lach PWM Comparaor Opocoupler 0.6V PWM OP X3.25 CS Improved Curren Mode Figure 9: PWM Conrolling 3.4 Sarup Phase Sof Sar couner Sof Sar finish SofS C7 Sof Sar Sof Sar Sof-Sar Comparaor & Gae Driver G7 0.6V PWM OP x3.25 CS Figure 10: Sof Sar Daa Shee 14 V2.1,

15 Funcional Descripion In he Sarup Phase, he IC provides a Sof Sar period o conrol he primary curren by means of a duy cycle limiaion. The Sof Sar funcion is a buil-in funcion and i is conrolled by an inernal couner. Figure 11: Sof Sar Phase When he V VCC exceeds he on-hreshold volage, he IC sars he Sof Sar mode (Figure 10). The funcion is realized by an inernal Sof Sar resisor, a curren sink and a couner. And he ampliude of he curren sink is conrolled by he couner (Figure 12). 5V R SofS SofS Sof Sar Couner 32I 8I 4I 2I I Figure 12: Sof Sar Circui Afer he IC is swiched on, he V SofS volage is conrolled such ha he volage is increased sep-wisely (32 seps) wih he increase of he couns. The Sof Sar couner would send a signal o he curren sink conrol in every 300µs such ha he curren sink decrease gradually and he duy raio of he gae drive increases gradually. The Sof Sar will be finished in 10ms ( Sof-Sar ) afer he IC is swiched on. A he end of he Sof Sar period, he curren sink is swiched off. Wihin he sof sar period, he duy cycle is increasing from zero o maximum gradually (see Figure 13). Daa Shee 15 V2.1,

16 Funcional Descripion V SofS Sof-Sar VSOFTS32 Gae Driver Figure 13: Gae drive signal under Sof-Sar Phase In addiion o Sar-Up, Sof-Sar is also acivaed a each resar aemp during Auo Resar. V SofS V SOFTS32 Sof-Sar V FB 4.5V V OUT V OUT Sar-Up Figure 14: Sar Up Phase The Sar-Up ime Sar-Up before he converer oupu volage V OUT is seled, mus be shorer han he Sof-Sar Phase Sof-Sar (Figure 14). By means of Sof-Sar here is an effecive minimizaion of curren and volage sresses on he inegraed CoolMOS, he clamp circui and he oupu recifier and i helps o preven sauraion of he ransformer during Sar-Up. Daa Shee 16 V2.1,

17 Funcional Descripion 3.5 PWM Secion Oscillaor 0.75 PWM Secion Duy Cycle max Clock Frequency Jier Sof Sar Block Sof Sar Comparaor PWM Comparaor 1 G8 FF1 S R Q Gae Driver & G9 Curren Limiing CoolMOS Gae Figure 15: PWM Secion Block Oscillaor The oscillaor generaes a fixed frequency of 100kHz wih frequency jiering of ±4% (which is ±4KHz) a a jiering period of 4ms. A capacior, a curren source and curren sink which deermine he frequency are inegraed. The charging and discharging curren of he implemened oscillaor capacior are inernally rimmed in order o achieve a very accurae swiching frequency. The raio of conrolled charge o discharge curren is adjused o reach a maximum duy cycle limiaion of D max =0.75. Once he Sof Sar period is over and when he IC goes ino normal operaing mode, he swiching frequency of he clock is varied by he conrol signal from he Sof Sar block. Then he swiching frequency is varied in range of 100kHz ± 4KHz a period of 4ms PWM-Lach FF1 The oupu of he oscillaor block provides coninuous pulse o he PWM-Lach which urns on/off he inegraed CoolMOS. Afer he PWM-Lach is se, i is rese by he PWM comparaor, he Sof Sar comparaor or he Curren -Limi comparaor. When i is in rese mode, he oupu of he driver is shu down immediaely Gae Driver VCC PWM-Lach 1 50 Gae CoolMOS Gae Driver Figure 16: Gae Driver Daa Shee 17 V2.1,

18 Funcional Descripion The driver-sage is opimized o minimize EMI and o provide high circui efficiency. This is done by reducing he swich on slope when exceeding he inegraed CoolMOS hreshold. This is achieved by a slope conrol of he rising edge a he driver s oupu (Figure 17) and adding a 50Ω gae urn on resisor (Figure 15). Thus he leading swich on spike is minimized. (inernal) V Gae yp. = 160ns 4.6V Figure 17: Gae Rising Slope Furhermore he driver circui is designed o eliminae cross conducion of he oupu sage. During power up, when VCC is below he undervolage lockou hreshold V VCCoff, he oupu of he Gae Driver is se o low in order o disable power ransfer o he secondary side. 3.6 Curren Limiing PWM Lach FF1 Curren Limiing Propagaion-Delay Compensaion PWM-OP & G10 C10 C12 Vcsh LEB 220ns LEB 180ns S4 VCSh_burs Acive Burs Mode Propagaion-Delay Compensaion-Burs or VFB_burs C5 G13 10k D1 1pF Figure 18: FBB Curren Limiing Block CS There is a cycle by cycle peak curren limiing operaion realized by he Curren-Limi comparaor C10. The source curren of he inegraed CoolMOS is sensed via an exernal sense resisor R Sense. By means of R Sense he source curren is ransformed o a sense volage V Sense which is fed ino he pin CS. If he volage V Sense exceeds he inernal hreshold volage V csh, he comparaor C10 immediaely urns off he gae drive by reseing he PWM Lach FF1. A Propagaion Delay Compensaion is added o suppor he immediae shu down of he inegraed CoolMOS wih very shor propagaion delay. Thus he influence of he AC inpu volage on he maximum oupu power can be reduced o minimal. This compensaion applies o boh he peak load and burs mode. In order o preven he curren limi from disorions caused by leading edge spikes, a Leading Edge Blanking (LEB) is inegraed in he curren sense pah for he comparaors C10, C12 and he PWM-OP. The oupu of comparaor C12 is acivaed by he Gae G10 if Acive Burs Mode is enered. When i is acivaed, he curren limiing is reduced o V csh_burs. This volage level deermines he maximum power level in Acive Burs Mode. Daa Shee 18 V2.1,

19 Funcional Descripion Leading Edge Blanking V Sense Vcsh LEB = 220ns/180ns Figure 19: Leading Edge Blanking Whenever he inegraed CoolMOS is swiched on, a leading edge spike is generaed due o he primary-side capaciances and reverse recovery ime of he secondary-side recifier. This spike can cause he gae drive o swich off uninenionally. In order o avoid a premaure erminaion of he swiching pulse, his spike is blanked ou wih a ime consan of LEB = 220ns for normal load and LEB = 180ns for burs mode Propagaion Delay Compensaion (paened) In case of overcurren deecion, here is always propagaion delay o swich off he inegraed CoolMOS. An overshoo of he peak curren Ipeak is induced o he delay, which depends on he raio of di/ d of he peak curren (Figure 20). I Sense I peak2 I peak1 I Limi Signal2 I Overshoo2 Signal1 Propagaion Delay I Overshoo1 Figure 20: Curren Limiing The overshoo of Signal2 is larger han of Signal1 due o he seeper rising waveform. This change in he slope is depending on he AC inpu volage. Propagaion Delay Compensaion is inegraed o reduce he overshoo due o di/d of he rising primary curren. Thus he propagaion delay ime beween exceeding he curren sense hreshold Vcsh and he swiching off of he inegraed CoolMOS is compensaed over emperaure wihin a wide inpu range. Curren Limiing is hen very accurae. For example, I peak = 0.5A wih R Sense = 2. The curren sense hreshold is se o a saic volage level V csh =1V wihou Propagaion Delay Compensaion. A curren ramp of di/d = 0.4A/µs, or dvsense/d = 0.8V/µs, and a propagaion delay ime of Propagaion Delay =180ns leads o an I peak overshoo of 14.4%. Wih he propagaion delay compensaion, he overshoo is only around 2% (Figure 21). wih compensaion wihou compensaion Figure 21: V Sense 1,3 1,25 1,2 1,15 1,1 1,05 1 0,95 Overcurren Shudown V 0,9 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 dv Sense d V s Daa Shee 19 V2.1,

20 Funcional Descripion The Propagaion Delay Compensaion is realized by means of a dynamic hreshold volage V csh (Figure 22). In case of a seeper slope he swich off of he driver is earlier o compensae he delay. V OSC max. Duy Cycle off ime V Sense Propagaion Delay V csh Signal1 Signal2 Figure 22: Dynamic Volage Threshold Vcsh Similarly, he same concep of propagaion delay compensaion is also implemened in burs mode wih reduced level, V csh_burs (Figure 18). Wih his implemenaion, he enry and exi burs mode power can be very close beween low line and high line inpu volage. 3.7 Conrol Uni The Conrol Uni conains he funcions for Acive Burs Mode and Auo Resar Mode. The Acive Burs Mode and he Auo Resar Mode boh have 20ms inernal blanking ime. For he over load Auo Resar Mode, he 20ms blanking ime can be furher exended by adding an exernal capacior a BV pin. Wih he blanking ime, he IC avoids enering ino hose wo modes accidenally. Tha buffer ime is very useful for he applicaion which works in shor duraion of peak power occasionally Basic and Exendable Blanking Mode 5.0V Ichg_EB Auo Resar Mode R OV2 # C BK BV S1 4.5V V C11 C3 Couner CT1 Spike Blanking 30us & G5 S2 FBB 4.5V C4 20ms Blanking Time Conrol Uni Figure 23: Basic and Exendable Blanking Mode There are 2 kinds of Blanking mode; basic mode and he exendable mode. The basic mode is a buil-in 20ms blanking ime while he exendable mode can exend his blanking ime by connecing an exernal capacior o he BV pin. For he exendable mode, he gae G5 remains blocked even hough he 20ms blanking ime is reached. Afer reaching he 20ms blanking ime he couner is acivaed and he swich S1 is urned on o charge he volage of BV pin by he consan curren source, I chg_eb. When he volage of BV pin his 4.5V, which is sensed by Daa Shee 20 V2.1,

21 Funcional Descripion comparaor C11, he couner will increase he couner by 1. Then i swiches off he swich S1 and urns on he swich S2. The volage a BV pin will be discharged hrough a 500Ω resisor. When he volage drops o 0.9V which is sensed by comparaor C3, he swich S2 will be urned off and he swich S1 will be urned on. Then he consan curren I chg_eb will charge he CBK capacior again. When he volage a BV his 4.5V which is sensed by comparaor C11, he couner will increase he coun o 2. The process repeas unil i reaches oal coun of 256 (Figure 24). Then he couner will release a high oupu signal. When he AND gae G5 deecs boh high signals a he inpus, i will acivae he 30µs spike blanking circui and finally he auo-resar mode will be acivaed. Figure 24: Waveform a exended blanking ime For example, if C BK =0.1µF, I chg_eb =720µA, R OV2 =15KΩ, I chg_eb =I chg_eb -(4.5V+0.9V)/(2*R OV2 )=540 µa Exended blanking ime = 256*(C BK *(4.5V-0.9V)/ I chg_eb + C BK *500*ln(4.5/0.9)) = 192ms Toal blanking ime = 20ms+192 = 212ms where I chg_eb =ne charging curren o C BK Noe: The above calculaion does no include he effec of he inpu OVP circui where here is exra biasing curren flowing from he inpu. Tha means he exended blanking ime will be shorened wih he line volage change if inpu OVP circui is implemened Acive Burs Mode (paened) To increase he efficiency of he sysem a ligh load, he mos effecive way is o operae a burs mode. Saring from CoolSET F3, he IC has been employing he acive burs mode and i can achieve he lowes sandby power. adops he same concep wih some more innovaive improvemens o he feaure. I includes he adjusable enry burs level, close power conrol beween high line and low line and he smaller oupu ripple during burs mode. Mos of he burs mode design in he marke will provide a fixed enry burs mode level which is a raio o he maximum power of he design. provides a more flexible level which can be seleced exernally. The provision also includes no enering burs mode. Propagaion delay is he major conribuor for he power conrol variaion for DCM flyback converer. I is proved o be effecive in he maximum power conrol. also apply he same concep in he burs mode. Therefore, he enry and exi burs mode power is also finely conrolled during burs mode. The feedback conrol swing during burs mode will affec he oupu ripple volage direcly. reduces he swing from 0.5V o 0.3V. Therefore, i would have around 40% improvemen for he oupu ripple. Daa Shee 21 V2.1,

22 Funcional Descripion CS Vcsh_burs C12 G10 & FF1 Curren Limiing Burs deec and adjus Inernal Bias VFB_burs C5 20 ms Blanking Time FBB C FB 4.0V C13 Acive Burs Mode 3.5V C6a 3.2V C6b & G11 Conrol Uni Figure 25: Acive Burs Mode The Acive Burs Mode is locaed in he Conrol Uni. Figure 24 shows he relaed componens Selecable burs enry level The burs mode enry level can be seleced by changing he differen capacior C FB a FBB pin. There are 4 levels o be seleced wih differen capacior which are argeed for 10%, 6.67%, 4.38% and 0% of he maximum inpu power. A he same ime, he exi burs levels are argeed o 20%, 13.3%, 9.6% and 0% of he maximum power accordingly. The corresponding capaciance range is from 6.8nF o 100pF. The below able is he recommended capaciance range for he enry and exi level wih he C FB capacior. CFB Enry level Exi level % of Pin_max VFB_burs % of Pin_max Vcsh_burs >=6.8nF (5%,X7R) 10% 1.60V 20% 0.45V 1nF~2.2nF (1%,COG) 6.67% 1.42V 13.3% 0.37V 220pF~470pF (1%,COG) 4.38% 1.27V 9.6% 0.31V <=100pF (1%,COG) 0% never 0% always The selecion is a he 1s 1ms of he UVLO ON (Vcc > 17V) during he 1s sar up bu i does no deec in he subsequen re-sar due o auo-resar proecion. In case here is proecion riggered such as inpu OVP before sars up, he deecion will be held unil he proecion is removed. When he Vcc reaches he UVLO ON in he 1s sar up, he capacior C FB a FBB pin is charged by a 5V volage source hrough he RFB resisor. When he volage a FBB pin his 4.5V, he FF4 will be se, he swich S9 is urned ON and he couner will increase by 1. Then he CFB is discharged hrough a 500Ω resisor. Afer reaching 0.5V, he FF4 is rese and he swich S9 is urned OFF. Then he CFB capacior is charged by he 5V volage source again unil i reaches 4.5V. The process repeas unil he end of 1ms. Then he deecion is ended. Afer ha, he oal number of coun in he couner is compared and he V FB-burs and he V cs_burs are seleced accordingly (Figure 26) Daa Shee 22 V2.1,

23 Funcional Descripion 5V VFB_burs VCSh_burs Comparaor logic couner FBB R FB 4.5V C19 UVLO S Q C FB V C20 FF4 R S9 UVLO during 1 s sarup 1ms imer Conrol Uni Figure 26: Enry Burs Mode deecion Enering Acive Burs Mode The FBB signal is kep monioring by he comparaor C5 (Figure 25). During normal operaion, he inernal blanking ime couner is rese o 0. When FBB signal falls below V FB_burs, i sars o coun. When he couner reaches 20ms and FBB signal is sill below V FB_burs, he sysem eners he Acive Burs Mode. This ime window prevens a sudden enering ino he Acive Burs Mode due o large load jumps. Afer enering Acive Burs Mode, a burs flag is se and he inernal bias is swiched off in order o reduce he curren consumpion of he IC o abou 620µA. I needs he applicaion o enforce he VCC volage above he Undervolage Lockou level of 10.5V such ha he Sarup Cell will no be swiched on accidenally. Or oherwise he power loss will increase drasically. The minimum VCC level during Acive Burs Mode depends on he load condiion and he applicaion. The lowes VCC level is reached a no load condiion Working in Acive Burs Mode Afer enering he Acive Burs Mode, he FBB volage rises as V OUT sars o decrease, which is due o he inacive PWM secion. The comparaor C6a moniors he FBB signal. If he volage level is larger han 3.5V, he inernal circui will be acivaed; he Inernal Bias circui resumes and sars o provide swiching pulse. In Acive Burs Mode he gae G10 is released and he curren limi is reduced o V csh_burs (Figure 3 and Figure 25). In one hand, i can reduce he conducion loss and he oher hand, i can reduce he audible noise. If he load a V OUT is sill kep unchanged, he FBB signal will drop o 3.2V. A his level he C6b deacivaes he inernal circui again by swiching off he Inernal Bias. The gae G11 is acive again as he burs flag is se afer enering Acive Burs Mode. In Acive Burs Mode, he FBB volage is changing like a saw ooh beween 3.2V and 3.5V (Figure 27) Leaving Acive Burs Mode The FBB volage will increase immediaely if here is a high load jump. This is observed by he comparaor C13 (Figure 25). Since he curren limi is reduced o 31%~45% of he maximum curren during acive burs mode, i needs a cerain load jump o raise he FBB signal o exceed 4.0V. A ha ime he comparaor C5 reses he Acive Burs Mode conrol which in urn blocks he comparaor C12 by he gae G10. The maximum curren can hen be resumed o sabilize V OUT. Daa Shee 23 V2.1,

24 Funcional Descripion VFBB 4.0V 3.5V 3.2V Enering Acive Burs Mode Leaving Acive Burs Mode VFB_burs Blanking Timer 20ms Blanking Time V CS Vcsh Curren limi level during Acive Burs Mode Vcsh_burs VVCC 10.5V IVCC 5.7mA 620uA V OUT Figure 27: Signals in Acive Burs Mode Proecion Modes The IC provides Auo Resar mode as he major proecion feaure. Auo Resar mode can preven he SMPS from desrucive saes. There are 3 kinds of auo resar mode; normal auo resar mode, odd skip auo resar mode and non swich auo resar mode. Odd skip auo resar mode is ha here is no deec of faul and no swiching pulse for he odd number resar cycle. A he even number of resar cycle he faul deec and sof sar swiching pulses mainained. If he faul persiss, i would coninue he auo-resar mode. However, if he faul is removed, i can release o normal operaion only a he even number auo resar cycle (Figure 28). VVCC Faul deeced No deec Sarup and deec No deec 17V 10.5V VCS Figure 28: Odd skip auo resar waveform Daa Shee 24 V2.1,

25 Funcional Descripion Non swich auo resar mode is similar o odd skip auo resar mode excep he sar up swiching pulses are also suppressed a he even number of he resar cycle. The deecion of faul sill remains a he even number of he resar cycle. When he faul is removed, he IC will resume o normal operaion a he even number of he resar cycle (Figure 29). VVCC Faul deeced No deec Sarup and deec No deec 17V 10.5V VCS No swiching Figure 29: Non swich auo resar waveform The main purpose of he odd skip auo resar is o exend he resar ime such ha he power loss during auo resar proecion can be reduced. This feaure is paricularly good for smaller Vcc capacior where he resar ime is shorer. The following able liss he possible sysem failures and he corresponding proecion modes. VCC Over volage (1) VCC Over volage (2) Over load Open Loop VCC Undervolage Shor Opocoupler Over emperaure Odd skip Auo Resar Mode Odd skip Auo Resar Mode Odd skip Auo Resar Mode Odd skip Auo Resar Mode Normal Auo Resar Mode Normal Auo Resar Mode Non swich Auo Resar Mode Vcc OVP, OTP and Vcc under volage Thermal Shudown Tj >130 C Auo Resar Mode Rese VVCC < 10.5V 25.5V C2 120μs blanking ime Spike Blanking 30μs Auo Resar mode VCC 20.5V C1 & Volage Reference FBB 4.5V C4 G1 Conrol Uni sofs_period Figure 30: Vcc OVP and OTP There are 2 ypes of Vcc over volage proecion; Vcc OVP (1) and Vcc OVP (2). The Vcc OVP (1) akes acion only during he sof sar period. The Vcc OVP (2) akes he acion in any condiions. Vcc OVP (1) condiion is when VVCC volage is > 20.5V, VFBB volage is > 4.5V and during sof sar period, he IC eners ino odd skip Auo Resar Mode. This condiion likely happens during sar up a open loop faul (Figure 30). Daa Shee 25 V2.1,

26 Funcional Descripion Vcc OVP (2) condiion is when VVCC volage is > 25.5V, he IC eners ino odd skip Auo Resar Mode (Figure 30). The over emperaure proecion OTP is sensed inside he conroller IC. The Thermal Shudown block keeps on monioring he juncion emperaure of he conroller. Afer deecing a juncion emperaure higher han 130 C, he IC will ener ino he non swich Auo Resar mode. The has also implemened wih a 50 C hyseresis. Tha means he IC can only be recovered when he conroller juncion emperaure is dropped 50 C lower han he over emperaure rigger poin (Figure 30). The VCC undervolage and shor opo-coupler will go ino he normal auo resar mode inherenly. In case of VCC undervolage, he Vcc volage drops indefiniely. When i drops below he Vcc under volage lock ou OFF volage (10.5V), he IC will urn off he IC and he sarup cell will urn on again. Then he Vcc volage will be charged up o UVLO ON volage (17V) and he IC urns on again provided he sarup cell charge up curren is no drained by he faul. If he faul is no removed, he Vcc will coninue o drop unil i his UVLO OFF volage and he resar cycle repeas. Shor Opocoupler can lead o Vcc undervolage because once he opo-coupler (ransisor side) is shored, he feedback volage will drop o zero and here will be no swiching pulse. Then he Vcc volage will drop same as he Vcc undervolage Over load, open loop proecion 5.0V Volage Reference S1 Ichg_EB Auo Resar Mode Rese VVCC < 10.5V Auo Resar Mode R OV2 # C BK BV 4.5V C11 couner Spike Blanking 30us S V C3 CT1 & G5 FBB 4.5V C4 20ms Blanking Time Conrol Uni Figure 31: Over load, open loop proecion In case of Overload or Open Loop, he FBB exceeds 4.5V which will be observed by comparaor C4. Then he builin blanking ime couner sars o coun. When i reaches 20ms, he exended blanking ime couner CT1 is acivaed. The swich S2 is urned on and he volage a he BV pin will be discharged hrough 500Ω resisor. When i drops o 0.9V, he swich S2 is urned off and he Swich S1 is urned on. Then a consan curren source I chg_eb will sar o charge up BV pin. When he volage his 4.5V which is moniored by comparaor C11, he swich S1 is urned off and he coun will increase by 1. Then he swich S2 will urn on again and he volage will drop o 0.9V and rise o 4.5V again. The coun will hen increase by 1 again. When he oal coun reaches 256, he couner CT1 will sop and i will release a high oupu signal. When boh he inpu signals a AND gae G5 is high, he odd skip Auo Resar Mode is acivaed afer he 30µs spike blanking ime (Figure 31). The oal blanking ime depends on he addiion of he buil-in and he exended blanking ime. If here is no CBK capacior a BV pin, he coun will finish wihin 0.1ms and he equivalen blanking ime is jus he buil-in ime of 20ms. Since he BV pin is a muli-funcion pin, i would share wih differen funcions. The resisor R OV2 from inpu OVP feaure applicaion may however affec he exendable blanking ime (Figure 31). Thus i should ake he ROV2 ino he calculaion of he exendable blanking ime. For example he exended blanking ime may be changed from 181ms o 212ms for 42.2KΩ o 15KΩ R OV2 resisor. The lis below shows one paricular C BK, R OV2 vs blanking ime. Daa Shee 26 V2.1,

27 Funcional Descripion C BK R OV2 Exended blanking ime Overall blanking ime 0.1uF 42.2KΩ 161ms 181ms 0.1uF 39.6KΩ 162ms 182ms 0.1uF 15KΩ 192ms 212ms Anoher facor o affec he exended blanking ime is he inpu volage hrough he R OV1 and R OV2. I would, on he conrary, reduce he exended blanking ime Inpu OVP Mode When he AC inpu volage is ou of he designed operaing range (e.g. > 300Vac), he volage a he inpu bulk capacior will increase a he same ime. If he MOSFET keeps on swiching, he drain volage may be oo high and he MOSFET will exceed he maximum volage raing and causes damages. The inpu OVP mode is o preven his phenomenon. The IC will sense he inpu volage hrough he inpu bulk capacior o he BV pin by 2 poenial divider resisors, R OV1 and R OV2 (Figure 32). During normal operaion, he BV pin volage is lower han V OVP_ref (1.98V). The oupu of C14a is low and he oupu of G21 is high. Togeher wih UVLO high signal (IC operaing) he S inpu of FF5 is low. The Q oupu of FF5 is low and he inpu OVP mode remains no acivaed. When here is an inpu over volage case, he inpu bulk capacior volage is increased and he BV volage is increased o larger han V OVP_ref. The oupu of C14a is high and he oupu of G21 is low. If he OVP persiss for 400µs (blanking ime) and he UVLO signal is sill high, he oupu of G20 is high. Then he S inpu of FF5 is high and he Q oupu of FF5 is high. The inpu OVP mode is se. The case of UVLO signal low is no considered as i means he IC is no working. UVLO G20 S Q Vbulk 400µs Blanking ime R Q 1.98V G21 FF5 ROV1 C14a Inpu OVP BV ROV2 1.91V C14b G22 5µs Blanking ime Conrol Uni Figure 32: Inpu OVP deecion circui Once he sysem eners he inpu OVP mode, here will be no swiching pulse and he IC keeps on monioring he BV signal. If he inpu OVP signal is no rese, here is no swiching pulse in each resar cycle (Figure 33). VBV Inpu OVP deeced Inpu OVP released 1.98V 1.91V VVCC 17V Swiching sar a he following resar cycle 10.5V VCS No swiching Figure 33: Inpu OVP mode waveform Daa Shee 27 V2.1,

28 Funcional Descripion The IC implemened wih hyseresis volage o leave he inpu OVP proecion. The hyseresis volage a BV pin is V OVP_hys (0.07V) and he inpu OVP rese volage a BV pin is V OVP_ref - V OVP_hys ; i.e. 1.91V. Afer he inpu OVP proecion is riggered, he volage a BV pin needs o drop V OVP_hys from V OVP_ref before i can be rese. When he BV volage drops below 1.91V, he oupu of C14b and G22 are high (Figure 32). The R inpu of he FF5 is high. Then he Q oupu of FF5 is low. The inpu OVP is rese. The sysem will urn on wih sof sar in he coming resar cycle when Vcc reaches he Vcc ON volage a 17V. The inpu OVP feaure can also be applied o cusomer defined proecion circui by pulling up he BV pin o larger han V OVP_ref. The formula o calculae he R OV1 and R OV2 are as below. Se R OV1 o a paricular value. R OV2 = R OV1 * V OVP_ref /(V OVP - V OVP_ref ) The formula o calculae he inpu OVP rese volage is as below. V OVP_rese =(V OVP_ref - V OVP_hys)*( R OV1 +ROV2)/ROV2 where V OVP: inpu over volage; V OVP_rese : inpu over rese volage; V OVP_ref : IC reference volage for OVP; V OVP_hys : IC hyseresis volage for OVP; R OV1 and R OV2 : resisors divider from inpu volage o BV pin. For example, V OVP_ref =1.98V, V OVP_hys =0.07V If inpu OVP volage, V OVP =424Vdc (300Vac), R OV1 =9MΩ, R OV2 =42.2KΩ Inpu OVP rese, V OVP_rese =408Vdc (289Vac) To disable inpu OVP feaure, he BV pin mus be conneced wih a resisor R OV2 15KΩ o IC ground and remove R OV1. (Remark: R OV2 mus be always 15KΩ in all condiions, oherwise overload proecion may no work) Acion sequence a BV pin Since here are 2 funcions a he same BV pin; inpu OVP and exended blanking ime, he acion of sequence is whichever sars firs akes he prioriy. When he Exended blanking ime is riggered by OLP and follows wih he Inpu OVP riggering, hen he OLP will coninue o work unil i ends. The IC would recheck he signal a BV pin afer one skip cycle. If he BV signal exceeds he inpu OVP hreshold, i would go o inpu OVP mode. Daa Shee 28 V2.1,

29 Funcional Descripion OLP deeced OLP released VFB 4.5V VBV 4.5V Exended OLP blanking ime Buil in 20ms OLP blanking ime Inpu OVP faul sared( bu overridden by exended blanking OLP ime) Inpu OVP deeced Inpu OVP Inpu OVP released 1.98V 1.91V 0.9V VVCC 17V Swiching sar a he following resar cycle 10.5V VCS No swiching Figure 34: Inpu OVP during exended blanking ime One ypical case happened is ha he overload happened firs and i follows wih he Inpu OVP feaure a he 1 s 20ms blanking ime. Since he overload proecion is sill no riggered a he 1 s 20ms blanking ime period and he exended blanking ime is no running, he inpu OVP mode will rigger righ away. OLP deeced OLP released VFB 4.5V Buil in 20ms OLP blanking ime Inpu OVP VBV Inpu OVP deeced Inpu OVP released 1.98V 1.91V VVCC 17V Swiching sar a he following resar cycle 10.5V VCS No swiching Figure 35: Inpu OVP during firs 20ms blanking ime Daa Shee 29 V2.1,

30 Elecrical Characerisics 4 Elecrical Characerisics Noe: All volages are measured wih respec o ground (Pin 8). The volage levels are valid if oher raings are no violaed. 4.1 Absolue Maximum Raings Noe: Absolue maximum raings are defined as raings, which when being exceeded may lead o desrucion of he inegraed circui. For he same reason make sure, ha any capacior ha will be conneced o pin 7 (VCC) is discharged before assembling he applicaion circui. T a =25 C unless oherwise specified. Parameer Symbol Limi Values Uni Remarks min. max. Drain Source Volage V DS V Pulse drain curren, p limied by Tjmax I D_Puls - 20 A Avalanche energy, repeiive AR limied E AR mj by max. T j =150 C 1) Avalanche curren, repeiive AR limied by max. Tj=150 C I AR - 4 A VCC Supply Volage V VCC V FBB Volage V FBB V BV Volage V BV V CS Volage V CS V Juncion Temperaure T j Sorage Temperaure T S C Conroller & CoolMOS C Thermal Resisance Juncion -Ambien R hja - 96 K/W Soldering emperaure, wavesoldering only allowed a leads T sold C 1.6mm (0.063in.) from case for 10s ESD Capabiliy (incl. Drain Pin) V ESD - 2 kv Human body model 2) 1) Repeiive avalanche causes addiional power losses ha can be calculaed as P AV =E AR *f 2) According o EIA/JESD22-A114-B (discharging a 100pF capacior hrough a 1.5KΩ series resisor) Daa Shee 30 V2.1,

31 Elecrical Characerisics 4.2 Operaing Range Noe: Wihin he operaing range he IC operaes as described in he funcional descripion. Parameer Symbol Limi Values Uni Remarks min. VCC Supply Volage V VCC V VCCoff 25 V Max value limied due o Vcc OVP Juncion Temperaure of Conroller Juncion Temperaure of CoolMOS max. T jcon T jcoolmos C Max value limied due o hermal shu down of conroller C 4.3 Characerisics Supply Secion Noe: The elecrical characerisics involve he spread of values wihin he specified supply volage and juncion emperaure range TJ from 40 C o 125 C. Typical values represen he median values, which are relaed o 25 C. If no oherwise saed, a supply volage of VCC = 17 V is assumed. Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Sar Up Curren I VCCsar μ A V VCC =16V VCC Charge Curren I VCCcharge ma V VCC = 0V Leakage Curren of Sar Up Cell and CoolMOS Supply Curren wih Inacive Gae I VCCcharge ma V VCC = 1V I VCCcharge ma V VCC =16V I SarLeak μ A I VCCsup ma V Drain = 650V a T j =100 C 1) Supply Curren wih Acive Gae I VCCsup ma I FBB = 0A Supply Curren in Auo Resar Mode wih Inacive Gae Supply Curren in Acive Burs Mode wih Inacive Gae VCC Turn-On ThresholdVCC Turn-Off Threshold VCC Turn-On/Off Hyseresis I VCCresar μ A I FBB = 0A I VCCburs μ A V FBB = 2.5V I VCCburs μ A V VCC = 11.5V, V FBB = 2.5V V VCCon V VCCoff V VCChys ) The parameer is no subjeced o producion es - verified by design/characerizaion V V V Daa Shee 31 V2.1,

32 Elecrical Characerisics Inernal Volage Reference Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Trimmed Reference Volage V REF V measured a pin FBB I FBB = PWM Secion Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Fixed Oscillaor Frequency f OSC khz f OSC khz T j = 25 C Frequency Jiering Range f jier - ±4.0 - khz T j = 25 C Frequency Jiering period T jier ms T j = 25 C Max. Duy Cycle D max Min. Duy Cycle D min VFBB < 0.3V PWM-OP Gain A V Volage Ramp Offse V Offse-Ramp V V FBB Operaing Range Min Level V FBB Operaing Range Max level V FBmin V V FBmax V CS=1V, limied by Comparaor C4 1) FBB Pull-Up Resisor R FB k Ω 1) The parameer is no subjeced o producion es - verified by design/characerizaion Sof Sar ime Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Sof Sar ime SS ms Daa Shee 32 V2.1,

33 Elecrical Characerisics Conrol Uni Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Inpu OVP reference volage for comparaor C14a V OVP_ref V T j = 25 C Inpu OVP hyseresis C14b V OVP_hys 0.07 V Tj = 25 C Blanking ime volage lower limi for Comparaor C3 V BKC V Blanking ime volage upper limi for Comparaor C11 V BKC V Over Load Limi for Comparaor C4 V FBC V Enry Burs selec High level for Comparaor C19 Enry Burs selec Low level for Comparaor C20 Acive Burs Mode Enry Level for Comparaor C5 Acive Burs Mode High Level for Comparaor C6a Acive Burs Mode Low Level for Comparaor C6b Acive Burs Mode Level for Comparaor C13 Overvolage Deecion Limi for Comparaor C1 Overvolage Deecion Limi for Comparaor C2 Charging curren for exended blanking ime V FBC V V FBC V 10% Pin_max V FB_burs V < 7 couns 6.67% Pin_max V FB_burs V 8 ~ 39 couns 4.38% Pin_max V FB_burs V 40 ~ 191 couns V FBC6a V In Acive Burs Mode V FBC6b V V FBC V V VCCOVP V VFBB = 5V, during sof sar V VCCOVP V I chg_eb μ A Thermal Shudown1) T jsd Hyseresis for hermal Shudown1) T jsd_hys Buil-in Blanking Time for Overload Proecion or ener Acive Burs Mode C Conroller C BK ms Timer for enry burs selec EBS ms Spike Blanking Time for Auo-Resar Proecion Spike μ s 1) The parameer is no subjeced o producion es - verified by design/characerizaion. The hermal shudown emperaure refers o he juncion emperaure of he conroller. Noe: The rend of all he volage levels in he Conrol Uni is he same regarding he deviaion excep VVCCOVP and VVCCPD Daa Shee 33 V2.1,

34 Elecrical Characerisics Curren Limiing Peak Curren Limiaion (incl. Propagaion Delay) Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. V csh V dv sense / d = 0.6V/µs (Figure 21) Peak Curren Limiaion during Acive Burs Mode Leading Edge Blanking 20% Pin_max V csh_burs V < 7 couns 13.3% Pin_max V csh_burs V 8 ~ 39 couns 9.6% Pin_max V csh_burs V 40 ~ 191 couns Normal mode LEB_normal ns Burs mode LEB_burs ns CS Inpu Bias Curren I CSbias μ A V CS =0V CoolMOS Secion Parameer Symbol Limi Values Uni Tes Condiion Drain Source Breakdown Volage V (BR)DSS Drain Source On-Resisance R DSon Effecive oupu capaciance, energy relaed min. yp. max V V Ω Ω T j = 25 C Tj = 110 C 1) Tj = 25 C Tj=125 C 1) a ID = 2.2A C o(er) pf VDS = 0V o 480V Rise Time rise ) - ns Fall Time fall ) - ns 1) The parameer is no subjeced o producion es - verified by design/characerizaion 2) Measured in a Typical Flyback Converer Applicaion Daa Shee 34 V2.1,

35 Typical Conroller Performance Characerisics 5 Typical Conroller Performance Characerisics Characerisric graphs are normalized a T a =25 C Figure 36: Line OVP (V OVP_ref ) vs. T a Figure 37: Hysersis of Line OVP (V OVP_hys ) vs. T a Daa Shee 35 V2.1,

36 CoolMOS Performance Characerisics 6 CoolMOS Performance Characerisics Figure 38: Safe Operaing Area (SOA) curve for Figure 39: SOA emperaure deraing coefficien curve Daa Shee 36 V2.1,

37 CoolMOS Performance Characerisics Figure 40: Power dissipaion; P o =f(t a ) Figure 41: Drain-source breakdown volage; V BR(DSS)= f(t j ), I D =0.25mA Daa Shee 37 V2.1,

38 Inpu Power Curve 7 Inpu Power Curve Two inpu power curves giving he ypical inpu power versus ambien emperaure are showed below; Vin=85Vac~265Vac (Figure 42) and Vin=230Vac+/-15% (Figure 43). The curves are derived based on a ypical disconinuous mode flyback model which considers eiher 50% maximum duy raio or 100V maximum secondary o primary refleced volage (higher prioriy). The calculaion is based on no copper area as heasink for he device. The inpu power already includes he power loss a inpu common mode choke, bridge recifier and he CoolMOS.The device sauraion curren Tj=125 C) is also considered. To esimae he oupu power of he device, i is simply muliplying he inpu power a a paricular operaing ambien emperaure wih he esimaed efficiency for he applicaion. For example, a wide range inpu volage (Figure 42), operaing emperaure is 50 C, esimaed efficiency is 85%, hen he esimaed oupu power is 44W (52W * 85%). Figure 42: Inpu power curve Vin=85~265Vac; P in =f(t a ) Figure 43: Inpu power curve Vin=230Vac; P in =f(t a ) Daa Shee 38 V2.1,

39 Ouline Dimension 8 Ouline Dimension Figure 44: PG-DIP-7 (Pb-free lead plaing Plasic Dual-in-Line Ouline) Daa Shee 39 V2.1,

40 Marking 9 Marking Figure 45: Marking for Daa Shee 40 V2.1,

41 Schemaic for recommended PCB layou 10 Schemaic for recommended PCB layou Figure 46: Schemaic for recommended PCB layou General guideline for PCB layou design using F3 CoolSET (refer o Figure 46): 1. Sar Ground a bulk capacior ground, C11: Sar Ground means all primary DC grounds should be conneced o he ground of bulk capacior C11 separaely in one poin. I can reduce he swiching noise going ino he sensiive pins of he CoolSET device effecively. The primary DC grounds include he followings. a. DC ground of he primary auxiliary winding in power ransformer, TR1, and ground of C16 and Z11. b. DC ground of he curren sense resisor, R12 c. DC ground of he CoolSET device, GND pin of IC11; he signal grounds from C13, C14, C15 and collecor of IC12 should be conneced o he GND pin of IC11 and hen sar connec o he bulk capacior ground. d. DC ground from bridge recifier, BR1 e. DC ground from he bridging Y-capacior, C4 2. High volage races clearance: High volage races should keep enough spacing o he nearby races. Oherwise, arcing would incur. a. 400V races (posiive rail of bulk capacior C11) o nearby race: > 2.0mm b. 600V races (drain volage of CoolSET IC11) o nearby race: > 2.5mm 3. Filer capacior close o he conroller ground: Filer capaciors, C13, C14 and C15 should be placed as close o he conroller ground and he conroller pin as possible so as o reduce he swiching noise coupled ino he conroller. Daa Shee 41 V2.1,