DTSHEET X286 2-Wire RT, 256k (32k x 8) Real Time lock/alendar/pu Supervisor wih EEPROM FN80 Rev.00 FETURES Real Time lock/alendar Tracks ime in Hours, Minues, Seconds and Hundredhs of a Second Day of he Week, Day, Monh, and Year 2 Polled larms (Non-volaile) Seable on he Second, Minue, Hour, Day of he Week, Day, or Monh Repea Mode (periodic inerrups) Oscillaor ompensaion on chip Inernal feedback resisor and compensaion capaciors 64 posiion Digially onrolled Trim apacior 6 digial frequency adjusmen seings o ±30ppm Baery Swich or Super ap Inpu 32 x 8 Bis of EEPROM 28-Bye Page Wrie Mode 8 modes of Block Lock Proecion Single Bye Wrie apabiliy High Reliabiliy Daa Reenion: 00 years Endurance: 00,000 cycles per bye 2-Wire Inerface ineroperable wih I 2 * 400kHz daa ransfer rae Frequency Oupu (SW Selecable: Off, Hz, 00Hz, or 32.768kHz) Low Power MOS.25µ Operaing urren (Typical) Small Package Opions 8 Ld EIJ SOI and 4 Ld TSSOP Repeiive larms Temperaure ompensaion PPLITIONS Uiliy Meers HV Equipmen udio/video omponens Se Top Box/Television Modems Nework Rouers, Hubs, Swiches, Bridges ellular Infrasrucure Equipmen Fixed Broadband Wireless Equipmen Pagers/PD POS Equipmen Tes Meers/Fixures Office uomaion (opiers, Fax) Home ppliances ompuer Producs Oher Indusrial/Medical/uomoive BLO DIGRM OS ompensaion X 32.768kHz X2 PHZ/IRQ Selec Oscillaor Frequency Divider Hz Timer alendar Logic Time eeping Regisers (SRM) Baery Swich ircuiry V V B SL SD Serial Inerface Decoder onrol Decode Logic onrol/ Regisers (EEPROM) Saus Regisers (SRM) larm Mask ompare larm Regs (EEPROM) 8 256 EEPROM RRY FN80 Rev.00 Page of 25
PIN DESRIPTIONS 8 LD EIJ SOI 4 LD TSSOP X X2 PHZ/IRQ V SS 2 3 4 8 7 6 5 V V B SL SD X X2 N N N PHZ/IRQ 2 3 4 5 6 4 3 2 0 9 V V B N N N SL V SS 7 8 SD Ordering Informaion PRT NUMBER PRT MRING V RNGE (V) TEMP. RNGE ( ) PGE PG. DWG. # X2868* X286 2.7 o 5.5 0 o 70 8 Ld EIJ SOI X2868I* X286 I -40 o 85 8 Ld EIJ SOI X286V4* X286 V 0 o 70 4 Ld TSSOP (4.4mm) MDP0044 X286V4Z* (Noe) X286 VZ 0 o 70 4 Ld TSSOP (4.4mm) (Pb-free) MDP0044 X286V4I* X286 VI -40 o 85 4 Ld TSSOP (4.4mm) MDP0044 X286V4IZ* (Noe) X286 VIZ -40 o 85 4 Ld TSSOP (4.4mm) (Pb-free) MDP0044 *dd "T" suffix for ape and reel. NOTE: Inersil Pb-free plus anneal producs employ special Pb-free maerial ses; molding compounds/die aach maerials and 00% mae in plae erminaion finish, which are RoHS complian and compaible wih boh SnPb and Pb-free soldering operaions. Inersil Pb-free producs are MSL classified a Pb-free peak reflow emperaures ha mee or exceed he Pb-free requiremens of IP/JEDE J STD-020. FN80 Rev.00 Page 2 of 25
PIN SSIGNMENTS Pin Number EIJ SOI TSSOP Symbol Brief Descripion X X. The X pin is he inpu of an invering amplifier. n exernal 32.768kHz quarz crysal is used wih he X286 o supply a imebase for he real ime clock. The recommended crysal is a iizen FS206-32.768DZF. Inernal compensaion circuiry is included o form a complee oscillaor circui. are should be aken in he placemen of he crysal and he layou of he circui. Pleny of ground plane around he device and shor races o X are highly recommended. See pplicaion secion for more recommendaions. 2 2 X2 X2. The X2 pin is he oupu of an invering amplifier. n exernal 32.768kHz quarz crysal is used wih he X286 o supply a imebase for he real ime clock. The recommended crysal is a iizen FS206-32.768DZF. Inernal compensaion circuiry is included o form a complee oscillaor circui. are should be aken in he placemen of he crysal and he layou of he circui. Pleny of ground plane around he device and shor races o X2 are highly recommended. See pplicaion secion for more recommendaions. 3 6 PHZ/IRQ Programmable Frequency/Inerrup Oupu PHZ/IRQ. This is eiher an oupu from he inernal oscillaor or an inerrup signal oupu. I is a MOS oupu. When used as frequency oupu, his signal has a frequency of 32.768kHz, 00Hz, Hz or inacive. When used as inerrup oupu, his signal noifies a hos processor ha an alarm has occurred and an acion is required. I is an acive LOW oupu. The conrol bis for his funcion are FO and FO0 and are found in address 00h of he lock onrol Memory map. See Programmable Frequency Oupu Bis FO, FO0 on page 3. 4 7 V SS V SS. 5 8 SD Serial Daa (SD). SD is a bidirecional pin used o ransfer daa ino and ou of he device. I has an open drain oupu and may be wire ORed wih oher open drain or open collecor oupus. The inpu buffer is always acive (no gaed). n open drain oupu requires he use of a pull-up resisor. The oupu circuiry conrols he fall ime of he oupu signal wih he use of a slope conrolled pulldown. The circui is designed for 400kHz 2-wire inerface speed. 6 9 SL Serial lock (SL). The SL inpu is used o clock all daa ino and ou of he device. The inpu buffer on his pin is always acive (no gaed). 7 3 V B V B. This inpu provides a backup supply volage o he device. V B supplies power o he device in he even he V supply fails. This pin can be conneced o a baery, a Supercap or ied o ground if no used. 8 4 V V. FN80 Rev.00 Page 3 of 25
BSOLUTE MXIMUM RTINGS Temperaure Under Bias... -65 o +35 Sorage Temperaure... -65 o +50 Volage on V, V B and PHZ/IRQ pin (respec o ground)...-0.5v o 7.0V Volage on SL, SD, X and X2 pin (respec o ground)... -0.5V o 7.0V or 0.5V above V or V B (whichever is higher) D Oupu urren... 5 m Lead Temperaure (Soldering, 0s)... 300 Sresses above hose lised under bsolue Maximum Raings may cause permanen damage o he device. This is a sress raing only and he funcional operaion of he device a hese or any oher condiions above hose indicaed in he operaional secions of his specificaion is no implied. Exposure o absolue maximum raing condiions for exended periods may affec device reliabiliy. D OPERTING HRTERISTIS (Temperaure = -40 o +85, unless oherwise saed.) Symbol Parameer ondiions Min Typ Max Uni Noes V Main Power Supply 2.7 5.5 V V B Backup Power Supply.8 5.5 V V B Swich o Backup Supply V B -0.2 V B -0. V V B Swich o Main Supply V B V B +0.2 V OPERTING HRTERISTIS Symbol Parameer ondiions Min Typ Max Uni Noes I Read cive Supply urren V = 2.7V 400 µ, 5, 7, 4 V = 5.0V 800 µ I 2 Program Supply urren V = 2.7V 2.5 m 2, 5, 7, 4 (nonvolaile) V = 5.0V 3.0 m I 3 Main Timekeeping V = 2.7V 0 µ 3, 7, 8, 4, 5 urren V = 5.0V 20 µ I B Timekeeping urren V B =.8V.25 µ 3, 6, 9, 4, 5 V See Performance Daa B = 3.3V.5 µ I LI Inpu Leakage urren 0 µ 0 I LO Oupu Leakage urren 0 µ 0 V IL Inpu LOW Volage -0.5 V x 0.2 or V B x 0.2 V 3 V IH Inpu HIGH Volage V x 0.7 or V B x 0.7 V HYS Schmi Trigger Inpu V relaed level Hyseresis V OL V OL2 V OH2 Oupu LOW Volage for SD Oupu LOW Volage for PHZ/IRQ Oupu HIGH Volage for PHZ/IRQ V + 0.5 or V B + 0.5 V 3.05 x V or V 3.05 x V B V = 2.7V 0.4 V V = 5.5V 0.4 V = 2.7V V x 0.3 V V = 5.5V V x 0.3 V = 2.7V V x 0.7 V 2 V = 5.5V V x 0.7 FN80 Rev.00 Page 4 of 25
Noes: () The device eners he cive sae afer any sar, and remains acive: for 9 clock cycles if he Device Selec Bis in he Slave ddress Bye are incorrec or unil 200nS afer a sop ending a read or wrie operaion. (2) The device eners he Program sae 200nS afer a sop ending a wrie operaion and coninues for W. (3) The device goes ino he Timekeeping sae 200nS afer any sop, excep hose ha iniiae a nonvolaile wrie cycle; W afer a sop ha iniiaes a nonvolaile wrie cycle; or 9 clock cycles afer any sar ha is no followed by he correc Device Selec Bis in he Slave ddress Bye. (4) For reference only and no esed. (5) V IL = V x 0., V IH = V x 0.9, f SL = 400Hz (6) V = 0V (7) V B = 0V (8) V SD = V SL =V, Ohers = GND or V (9) V SD =V SL =V B, Ohers = GND or V B (0)V SD = GND or V, V SL = GND or V, V RESET = GND or V ()I OL = 3.0m a 5.5V,.5m a 2.7V (2) I OH = -.0m a 5.5V, -0.4m a 2.7V (3)Threshold volages based on he higher of Vcc or Vback. (4)Using recommended crysal and oscillaor nework applied o X and X2 (25 ). (5)Typical values are for T = 25 apaciance T = 25, f =.0 MHz, V = 5V Symbol Parameer Max. Unis Tes ondiions () OUT Oupu apaciance (SD, PHZ/IRQ) 0 pf V OUT = 0V () IN Inpu apaciance (SL) 0 pf V IN = 0V Noes: () This parameer is no 00% esed. (2) The inpu capaciance beween x and x2 pins can be varied beween 5pF and 9.75pF by using analog rimming regisers HRTERISTIS Tes ondiions Inpu Pulse Levels V x 0. o V x 0.9 Inpu Rise and Fall Times 0ns Inpu and Oupu Timing V x 0.5 Levels Oupu Load Sandard Oupu Load Figure. Sandard Oupu Load for esing he device wih V = 5.0V Equivalen Oupu Load ircui for V = 5V 5.0V 5.0V 533 For V OL = 0.4V and I OL = 3 m 36 SD PHZ/IRQ 00pF 806 00pF FN80 Rev.00 Page 5 of 25
Specificaions (T = -40 o +85, V = +2.7V o +5.5V, unless oherwise specified.) Symbol Parameer Min. Max. Unis f SL SL lock Frequency 400 khz IN Pulse widh Suppression Time a inpus 50 () ns SL LOW o SD Daa Ou Valid 0.9 s BUF Time he bus mus be free before a new ransmission can sar.3 s LOW lock LOW Time.3 s HIGH lock HIGH Time 0.6 s SU:ST Sar ondiion Seup Time 0.6 s HD:ST Sar ondiion Hold Time 0.6 s SU:DT Daa In Seup Time 00 ns HD:DT Daa In Hold Time 0 s SU:STO Sop ondiion Seup Time 0.6 s DH Daa Oupu Hold Time 50 ns R SD and SL Rise Time 20 +.b ()(2) 300 ns F SD and SL Fall Time 20 +.b ()(2) 300 ns b apaciive load for each bus line 400 pf Noes: () This parameer is no 00% esed. (2) b = oal capaciance of one bus line in pf. TIMING DIGRMS Bus Timing F HIGH LOW R SL SU:DT SU:ST HD:ST HD:DT SU:STO SD IN DH BUF SD OUT FN80 Rev.00 Page 6 of 25
Wrie ycle Timing SL SD 8h Bi of Las Bye Sop ondiion W Sar ondiion Power-up Timing Noes: () Delays are measured from he ime V is sable unil he specified operaion can be iniiaed. These parameers are no 00% esed. V slew rae should be beween 0.2mV/µsec and 50mV/µsec. (2) Typical values are for T = 25 and V = 5.0V Nonvolaile Wrie ycle Timing Noe: Symbol Parameer Min. Typ. (2) Max. Unis () PUR Time from Power-up o Read ms () PUW Time from Power-uppower-up o Wrie 5 ms Symbol Parameer Min. Typ. () Max. Unis W () Wrie ycle Time 5 0 ms () W is he ime from a valid sop condiion a he end of a wrie sequence o he end of he self-imed inernal nonvolaile wrie cycle. I is he minimum cycle ime o be allowed for any nonvolaile wrie by he user, unless cknowledge Polling is used. FN80 Rev.00 Page 7 of 25
DESRIPTION The X286 device is a Real Time lock wih clock/calendar, wo polled alarms wih inegraed 32kx8 EEPROM, oscillaor compensaion, and baery backup swich. The oscillaor uses an exernal, low-cos 32.768kHz crysal. ll compensaion and rim componens are inegraed on he chip. This eliminaes several exernal discree componens and a rim capacior, saving board area and componen cos. The Real-Time lock keeps rack of ime wih separae regisers for Hours, Minues, Seconds and /00 of a second. The alendar has separae regisers for Dae, Monh, Year and Day-of-week. The calendar is correc hrough 2099, wih auomaic leap year correcion. The powerful Dual larms can be se o any lock/alendar value for a mach. For insance, every minue, every Tuesday, or 5:23 M on March 2. The alarms can be polled in he Saus Regiser or provide a hardware inerrup (IRQ Pin). There is a repea mode for he alarms allowing a periodic inerrup. The PHZ/IRQ pin may be sofware seleced o provide a frequency oupu of Hz, 00 Hz, or 32,768 Hz. The device offers a backup power inpu pin. This V B pin allows he device o be backed up by baery or Superap. The enire X286 device is fully operaional from 2.7 o 5.5 vols and he clock/calendar porion of he X286 device remains fully operaional down o.8 vols (Sandby Mode). The X286 device provides 256 bis of EEPROM wih 8 modes of BlockLock conrol. The BlockLock allows a safe, secure memory for criical user and configuraion daa, while allowing a large user sorage area. PIN DESRIPTIONS X X2 PHZ/IRQ V SS 8-pin EIJ SOI 2 3 4 8 7 6 5 X286 V X V B X2 SL N N SD N PHZ/IRQ V SS 4- pin TSSOP 4 V 2 3 V B 3 2 N 4 N 5 0 N 6 9 SL 7 8 SD Serial lock (SL) The SL inpu is used o clock all daa ino and ou of he device. The inpu buffer on his pin is always acive (no gaed). Serial Daa (SD) SD is a bidirecional pin used o ransfer daa ino and ou of he device. I has an open drain oupu and may be wire ORed wih oher open drain or open collecor oupus. The inpu buffer is always acive (no gaed). n open drain oupu requires he use of a pull-up resisor. The oupu circuiry conrols he fall ime of he oupu signal wih he use of a slope conrolled pull-down. The circui is designed for 400kHz 2-wire inerface speed. V B This inpu provides a backup supply volage o he device. V B supplies power o he device in he even he V supply fails. This pin can be conneced o a baery, a Supercap or ied o ground if no used. Programmable Frequency/Inerrup Oupu PHZ/IRQ This is eiher an oupu from he inernal oscillaor or an inerrup signal oupu. I is a MOS oupu. When used as frequency oupu, his signal has a frequency of 32.768kHz, 00Hz, Hz or inacive. When used as inerrup oupu, his signal noifies a hos processor ha an alarm has occurred and an acion is required. I is an acive LOW oupu. The conrol bis for his funcion are FO and FO0 and are found in address 00h of he lock onrol Memory map. See Programmable Frequency Oupu Bis FO, FO0 on page 3. X, X2 The X and X2 pins are he inpu and oupu, respecively, of an invering amplifier. n exernal 32.768kHz quarz crysal is used wih he X286 o supply a imebase for he real ime clock. The recommended crysal is a iizen FS206-32.768DZF. Inernal compensaion circuiry is included o form a complee oscillaor circui. are should be aken in he placemen of he crysal and he layou of he circui. Pleny of ground plane around he device and shor races o X and X2 are highly recommended. See pplicaion secion for more recommendaions. FN80 Rev.00 Page 8 of 25
Figure 2. Recommended rysal connecion POWER ONTROL OPERTION The power conrol circui acceps a V and a V B inpu. The power conrol circui powers he clock from V B when V < V B - 0.2V. I will swich back o power he device from V when V exceeds V B. Figure 3. Power onrol V B Off V X X2 Volage REL TIME LO OPERTION The Real Time lock (RT) uses an exernal 32.768kHz quarz crysal o mainain an accurae inernal represenaion of he /00 of a second, second, minue, hour, day, dae, monh, and year. The RT has leap-year correcion. The clock also correcs for monhs having fewer han 3 days and has a bi ha conrols 24 hour or M/PM forma. When he X286 powers up afer he loss of boh V and V B, he clock will no operae unil a leas one bye is wrien o he clock regiser. Reading he Real Time lock The RT is read by iniiaing a Read command and specifying he address corresponding o he regiser of he Real Time lock. The RT Regisers can hen be read in a Sequenial Read Mode. Since he clock runs coninuously and a read akes a finie amoun of ime, here is he possibiliy ha he clock could change during he course of a read operaion. In his device, he ime is lached by he read command (falling edge of he clock on he bi prior o RT daa oupu) ino a separae lach o avoid ime changes during he read operaion. The clock coninues o run. larms occurring during a read are unaffeced by he read operaion. Wriing o he Real Time lock The ime and dae may be se by wriing o he RT regisers. To avoid changing he curren ime by an uncompleed wrie operaion, he curren ime value is loaded ino a separae buffer a he falling edge of he clock on he bi before he RT daa inpu byes, he clock coninues o run. The new serial inpu daa replaces he values in he buffer. This new RT value is loaded back ino he RT Regiser by a sop bi a he end of a valid wrie sequence. n invalid wrie operaion abors he On In ime updae procedure and he conens of he buffer are discarded. fer a valid wrie operaion he RT will reflec he newly loaded daa beginning wih he SSE regiser rese o 0 a he nex sub-second updae afer he sop bi is wrien. The Hz frequency oupu from he PHZ/IRQ pin will be rese o resar afer he sop bi is wrien. The RT coninues o updae he ime while an RT regiser wrie is in progress and he RT coninues o run during any nonvolaile wrie sequences. single bye may be wrien o he RT wihou affecing he oher byes. ccuracy of he Real Time lock The accuracy of he Real Time lock depends on he frequency of he quarz crysal ha is used as he ime base for he RT. Since he resonan frequency of a crysal is emperaure dependen, he RT performance will also be dependen upon emperaure. The frequency deviaion of he crysal is a funcion of he urnover emperaure of he crysal from he crysal s nominal frequency. For example, a >20ppm frequency deviaion ranslaes ino an accuracy of > minue per monh. hese parameers are available from he crysal manufacurer. Inersil s RT family provides onchip crysal compensaion neworks o adjus loadcapaciance o une oscillaor frequency from +6 ppm o - 37 ppm when using a 2.5 pf load crysal. For more deail informaion see he pplicaion secion. LO/ONTROL REGISTERS (R) The onrol/lock Regisers are locaed in an area separae from he EEPROM array and are only accessible following a slave bye of 0x and reads or wries o addresses [0000h:003Fh]. The clock/conrol memory map has memory addresses from 0000h o 003Fh. The defined addresses are described in he Table. Wriing o and reading from he undefined addresses are no recommended. R access The conens of he R can be modified by performing a bye or a page wrie operaion direcly o any address in he R. Prior o wriing o he R (excep he saus regiser), however, he WEL and RWEL bis mus be se using a wo sep process (See secion Wriing o he lock/onrol Regisers. ) The R is divided ino 5 secions. These are:. larm 0 (8 byes; non-volaile) 2. larm (8 byes; non-volaile) 3. onrol (4 byes; non-volaile) 4. Real Time lock (8 byes; volaile) 5. Saus ( bye; volaile) FN80 Rev.00 Page 9 of 25
Each regiser is read and wrien hrough buffers. The nonvolaile porion (or he couner porion of he RT) is updaed only if RWEL is se and only afer a valid wrie operaion and sop bi. sequenial read or page wrie operaion provides access o he conens of only one secion of he R per operaion. ccess o anoher secion requires a new operaion. oninued reads or wries, once reaching he end of a secion, will wrap around o he sar of he secion. read or wrie can begin a any address in he R. I is no necessary o se he RWEL bi prior o wriing he saus regiser. Secion 5 suppors a single bye read or wrie only. oninued reads or wries from his secion erminaes he operaion. The sae of he R can be read by performing a random read a any address in he R a any ime. This reurns he conens of ha regiser locaion. ddiional regisers are read by performing a sequenial read. The read insrucion laches all lock regisers ino a buffer, *n = 0 for larm 0: N = for larm so an updae of he clock does no change he ime being read. sequenial read of he R will no resul in he oupu of daa from he memory array. he end of a read, he maser supplies a sop condiion o end he operaion and free he bus. fer a read of he R, he address remains a he previous address + so he user can execue a curren address read of he R and coninue reading he nex Regiser. LRM REGISTERS There are wo alarm regisers whose conens mimic he conens of he RT regiser, bu add enable bis and exclude he 24 hour ime selecion bi. The enable bis specify which regisers o use in he comparison beween he larm and Real Time Regisers. For example: Seing he Enable Monh bi (EMOn*) bi in combinaion wih oher enable bis and a specific alarm ime, he user can esablish an alarm ha riggers a he same ime once a year. Table. lock/onrol Memory Map ddr. Type Reg Name 7 6 5 4 3 2 Bi 0 (opional) 003F Saus SR BT L L0 0 0 RWEL WEL RTF 0h 0037 RT SSE SS23 SS22 SS2 SS20 SS3 SS2 SS SS0 0-99 xxh 0036 (SRM) DW 0 0 0 0 0 DY2 DY DY0 0-6 xxh 0035 YR Y23 Y22 Y2 Y20 Y3 Y2 Y Y0 0-99 xxh 0034 MO 0 0 0 G20 G3 G2 G G0-2 xxh 0033 DT 0 0 D2 D20 D3 D2 D D0-3 xxh 0032 HR MIL 0 H2 H20 H3 H2 H H0 0-23 xxh 003 MN 0 M22 M2 M20 M3 M2 M M0 0-59 xxh 0030 S 0 S22 S2 S20 S3 S2 S S0 0-59 xxh 003 onrol DTR 0 0 0 0 0 DTR2 DTR DTR0 00h 002 (EEPROM) TR 0 0 TR5 TR4 TR3 TR2 TR TR0 00h 00 INT IM LE L0E FO FO0 Read Only Read Only Read Only 00h 000 BL BP2 BP BP0 WD WD0 Read Only Read Only Read Only 00h 000F larm Y2 Read-only - Defaul = 20h 20 20h 000E (EEPROM) DW EDW 0 0 0 0 DY2 DY DY0 0-6 00h 000D YR Unused - Defaul = RT Year value (No EEPROM) - Fuure expansion 000 MO EMO 0 0 G20 G3 G2 G G0-2 00h 000B DT EDT 0 D2 D20 D3 D2 D D0-3 00h 000 HR EHR 0 H2 H20 H3 H2 H H0 0-23 00h 0009 MN EMN M22 M2 M20 M3 M2 M M0 0-59 00h 0008 S ES S22 S2 S20 S3 S2 S S0 0-59 00h Range Defaul FN80 Rev.00 Page 0 of 25
Table. lock/onrol Memory Map (oninued) Reg 0 ddr. Type Name 7 6 5 4 3 2 (opional) Range 0007 larm0 Y20 Read-only - Defaul = 20h 20 20h 0006 (EEPROM) DW0 EDW0 0 0 0 0 DY2 DY DY0 0-6 00h 0005 YR0 Unused - Defaul = RT Year value (No EEPROM) Fuure expansion 0004 MO0 EMO0 0 0 0G20 0G3 0G2 0G 0G0-2 00h 0003 DT0 EDT0 0 0D2 0D20 0D3 0D2 0D 0D0-3 00h 0002 HR0 EHR0 0 0H2 0H20 0H3 0H2 0H 0H0 0-23 00h 000 MN0 EMN0 0M22 0M2 0M20 0M3 0M2 0M 0M0 0-59 00h 0000 S0 ES0 0S22 0S2 0S20 0S3 0S2 0S 0S0 0-59 00h Bi Defaul When here is a mach, an alarm flag is se. The occurrence of an alarm can be deermined by polling he L0 and L bis or by enabling he IRQ oupu, using i as hardware flag. The alarm enable bis are locaed in he MSB of he paricular regiser. When all enable bis are se o 0, here are no alarms. The user can se he X286 o alarm every Wednesday a 8:00 M by seing he EDWn*, he EHRn* and EMNn* enable bis o and seing he DWn*, HRn* and MNn* larm regisers o 8:00 M Wednesday. daily alarm for 9:30PM resuls when he EHRn* and EMNn* enable bis are se o and he HRn* and MNn* regisers are se o 9:30 PM. *n = 0 for larm 0: N = for larm REL TIME LO REGISTERS lock/alendar Regisers (SSE, S, MN, HR, DT, MO, YR) These regisers depic BD represenaions of he ime. s such, SSE (/00 Second) range from 00 o 99, S (Seconds) and MN (Minues) range from 00 o 59, HR (Hour) is o 2 wih an M or PM indicaor (H2 bi) or 0 o 23 (wih MIL=), DT (Dae) is o 3, MO (Monh) is o 2, YR (Year) is 0 o 99. The SSE regiser is readonly. Dae of he Week Regiser (DW) This regiser provides a Day of he Week saus and uses hree bis DY2 o DY0 o represen he seven days of he week. The couner advances in he cycle 0--2-3- 4-5-6-0--2- The assignmen of a numerical value o a specific day of he week is arbirary and may be decided by he sysem sofware designer. The defaul value is defined as 0. 24 Hour Time If he MIL bi of he HR regiser is, he RT uses a 24- hour forma. If he MIL bi is 0, he RT uses a 2-hour forma and H2 bi funcions as an M/PM indicaor wih a represening PM. The clock defauls o sandard ime wih H2=0. Leap Years Leap years add he day February 29 and are defined as hose years ha are divisible by 4. Years divisible by 00 are no leap years, unless hey are also divisible by 400. This means ha he year 2000 is a leap year, he year 200 is no. The X286 does no correc for he leap year in he year 200. STTUS REGISTER (SR) The Saus Regiser is locaed in he R memory map a address 003Fh. This is a volaile regiser only and is used o conrol he WEL and RWEL wrie enable laches, read wo power saus and wo alarm bis. This regiser is separae from boh he array and he lock/onrol Regisers (R). Table 2. Saus Regiser (SR) ddr 7 6 5 4 3 2 0 003Fh Defaul B T L L 0 0 0 RWEL WEL RTF 0 0 0 0 0 0 0 BT: Baery Supply Volaile This bi se o indicaes ha he device is operaing from V B, no V. I is a read-only bi and is se/rese by hardware (X286 inerally). Once he device begins operaing from V, he device ses his bi o 0. FN80 Rev.00 Page of 25
L, L0: larm bis Volaile These bis announce if eiher alarm 0 or alarm mach he real ime clock. If here is a mach, he respecive bi is se o. The falling edge of he las daa bi in a SR Read operaion reses he flags. Noe: Only he L bis ha are se when an SR read sars will be rese. n alarm bi ha is se by an alarm occurring during an SR read operaion will remain se afer he read operaion is complee. RWEL: Regiser Wrie Enable Lach Volaile This bi is a volaile lach ha powers up in he LOW (disabled) sae. The RWEL bi mus be se o prior o any wries o he lock/onrol Regisers. Wries o RWEL bi do no cause a nonvolaile wrie cycle, so he device is ready for he nex operaion immediaely afer he sop condiion. wrie o he R requires boh he RWEL and WEL bis o be se in a specific sequence. WEL: Wrie Enable Lach Volaile The WEL bi conrols he access o he R and memory array during a wrie operaion. This bi is a volaile lach ha powers up in he LOW (disabled) sae. While he WEL bi is LOW, wries o he R or any array address will be ignored (no acknowledge will be issued afer he Daa Bye). The WEL bi is se by wriing a o he WEL bi and zeroes o he oher bis of he Saus Regiser. Once se, WEL remains se unil eiher rese o 0 (by wriing a 0 o he WEL bi and zeroes o he oher bis of he Saus Regiser) or unil he par powers up again. Wries o WEL bi do no cause a nonvolaile wrie cycle, so he device is ready for he nex operaion immediaely afer he sop condiion. RTF: Real Time lock Fail Bi Volaile This bi is se o a afer a oal power failure. This is a read only bi ha is se by hardware (X286 inernally) when he device powers up afer having los all power o he device (boh V and V B go o 0V). The bi is se regardless of wheher V or V B is applied firs. The loss of only one of he supplies does no se he RTF bi o. On power up afer a oal power failure, all regisers are se o heir defaul saes and he clock will no incremen unil a leas one bye is wrien o he clock regiser. The firs valid wrie o he RT secion afer a complee power failure reses he RTF bi o 0 (wriing one bye is sufficien). Unused Bis: This device does no use bis 3 or 4 in he SR, bu mus have a zero in hese bi posiions. The Daa Bye oupu during a SR read will conain zeros in hese bi locaions. ONTROL REGISTERS The onrol Bis and Regisers, described under his secion, are nonvolaile. Block Proec Bis BP2, BP, BP0 The Block Proec Bis, BP2, BP and BP0, deermine which blocks of he array are wrie proeced. wrie o a proeced block of memory is ignored. The block proec bis will preven wrie operaions o one of eigh segmens of he array. The pariions are described in Table 3. Table 3. Block Proec Bis Proeced ddresses X286 rray Lock 0 0 0 None None (defaul) 0 0 6000h - 7FFFh Upper /4 0 0 4000h - 7FFFh Upper /2 0 0000h - 7FFFh Full rray 0 0 0000h - 007Fh Firs Page 0 0000h - 00FFh Firs 2 pgs 0 0000h - 0FFh Firs 4 pgs 0000h - 03FFh Firs 8 Pgs BP2 BP BP0 Wachdog Timer onrol Bis WD, WD0 The bis WD and WD0 conrol he period of he Wachdog Timer. See Table 4 for opions. Table 4. Wachdog Timer Time-Ou Opions WD WD0 Wachdog Time-Ou Period 0 0.75 seconds (defaul) 0 750 milliseconds 0 250 milliseconds Disabled FN80 Rev.00 Page 2 of 25
INTERRUPT ONTROL ND FREQUENY OUTPUT REGISTER (INT) Inerrup onrol and Saus Bis (IM, LE, L0E) There are wo Inerrup onrol bis, larm Inerrup Enable (LE) and larm 0 Inerrup Enable (L0E) o specifically enable or disable he alarm inerrup signal oupu (IRQ). The inerrups are enabled when eiher LE and L0E are se o, respecively. Two volaile bis (L and L0), associaed wih he wo alarms respecively, indicae if an alarm has happened. These bis are se on an alarm condiion regardless of wheher he IRQ inerrup is enabled. The L and L0 bis in he saus regiser are rese by he falling edge of he eighh clock of a read of he regiser conaining he bis. Pulse Inerrup Mode The pulsed inerrup mode allows for repeiive or recurring alarm funcionaliy. Hence an repeiive or recurring alarm can be se for every n h second, or n h minue, or n h hour, or n h dae, or for he same day of he week. The pulsed inerrup mode can be considered a repeiive inerrup mode, wih he repeiion rae se by he ime seing fo he alarm. The Pulse Inerrup Mode is enabled when he IM bi is se. IM Bi Inerrup/larm Frequency 0 Single Time Even Se By larm Repeiive/Recurring Time Even Se By larm The larm IRQ oupu will oupu a single pulse of shor duraion (approximaely 0-40ms) once he alarm condiion is me. If he inerrup mode bi (IM bi) is se, hen his pulse will be periodic. Programmable Frequency Oupu Bis FO, FO0 These are wo oupu conrol bis. They selec one of hree divisions of he inernal oscillaor, ha is applied o he PHZ oupu pin. Table 5 shows he selecion bis for his oupu. When using he PHZ oupu funcion, he larm IRQ oupu funcion is disabled. Table 5. Programmable Frequency Oupu Bis FO FO0 Oupu Frequency (average of 00 samples) 0 0 larm IRQ oupu 0 32.768kHz 0 00Hz Hz ON-HIP OSILLTOR OMPENSTION Digial Trimming Regiser (DTR) DTR2, DTR and DTR0 (Non-Volaile) The digial rimming Bis DTR2, DTR and DTR0 adjus he number of couns per second and average he ppm error o achieve beer accuracy. DTR2 is a sign bi. DTR2=0 means frequency compensaion is > 0. DTR2= means frequency compensaion is < 0. DTR and DTR0 are scale bis. DTR gives 0 ppm adjusmen and DTR0 gives 20 ppm adjusmen. range from -30ppm o +30ppm can be represened by using hree bis above. Table 6. Digial Trimming Regisers DTR Regiser DTR2 DTR DTR0 Esimaed frequency PPM 0 0 0 0 0 0 +0 0 0 +20 0 +30 0 0 0 0-0 0-20 -30 nalog Trimming Regiser (TR) (Non-volaile) Six analog rimming Bis from TR5 o TR0 are provided o adjus he on-chip loading capaciance range. The onchip load capaciance ranges from 3.25pF o 8.75pF. Each bi has a differen weigh for capaciance adjusmen. Using a iizen FS-206 crysal wih differen TR bi combinaions provides an esimaed ppm range from +6ppm o -37ppm o he nominal frequency compensaion. The combinaion of digial and analog rimming can give up o +46ppm adjusmen. The on-chip capaciance can be calculaed as follows: TR = [(TR value, decimal) x 0.25pF] +.0pF Noe ha he TR values are in wo s complemen, wih TR(000000) =.0pF, so he enire range runs from 3.25pF o 8.75pF in 0.25pF seps. The values calculaed above are ypical, and oal load capaciance seen by he crysal will include approximaely 2pF of package and board capaciance in addiion o he TR value. See pplicaion secion and Inersil s applicaion Noe N54 for more informaion. FN80 Rev.00 Page 3 of 25
WRITING TO THE LO/ONTROL REGISTERS hanging any of he nonvolaile bis of he clock/ conrol regiser requires he following seps: Wrie a 02h o he Saus Regiser o se he Wrie Enable Lach (WEL). This is a volaile operaion, so here is no delay afer he wrie. (Operaion preceeded by a sar and ended wih a sop). Wrie a 06h o he Saus Regiser o se boh he Regiser Wrie Enable Lach (RWEL) and he WEL bi. This is also a volaile cycle. The zeros in he daa bye are required. (Operaion preceeded by a sar and ended wih a sop). Wrie one o 8 byes o he lock/onrol Regisers wih he desired clock, alarm, or conrol daa. This sequence sars wih a sar bi, requires a slave bye of 00 and an address wihin he R and is erminaed by a sop bi. wrie o he R changes EEPROM values so hese iniiae a nonvolaile wrie cycle and will ake up o 0ms o complee. Wries o undefined areas have no effec. The RWEL bi is rese by he compleion of a nonvolaile wrie cycle, so he sequence mus be repeaed o again iniiae anoher change o he R conens. If he sequence is no compleed for any reason (by sending an incorrec number of bis or sending a sar insead of a sop, for example) he RWEL bi is no rese and he device remains in an acive mode. Wriing all zeros o he saus regiser reses boh he WEL and RWEL bis. read operaion occurring beween any of he previous operaions will no inerrup he regiser wrie operaion. SERIL OMMUNITION Inerface onvenions The device suppors a bidirecional bus oriened proocol. The proocol defines any device ha sends daa ono he bus as a ransmier, and he receiving device as he receiver. The device conrolling he ransfer is called he maser and he device being conrolled is called he slave. The maser always iniiaes daa ransfers, and provides he clock for boh ransmi and receive operaions. Therefore, he devices in his family operae as slaves in all applicaions. lock and Daa Daa saes on he SD line can change only during SL LOW. SD sae changes during SL HIGH are reserved for indicaing sar and sop condiions. See Figure 4. Sar ondiion ll commands are preceded by he sar condiion, which is a HIGH o LOW ransiion of SD when SL is HIGH. The device coninuously moniors he SD and SL lines for he sar condiion and will no respond o any command unil his condiion has been me. See Figure 5. Sop ondiion ll communicaions mus be erminaed by a sop condiion, which is a LOW o HIGH ransiion of SD when SL is HIGH. The sop condiion is also used o place he device ino he Sandby power mode afer a read sequence. sop condiion can only be issued afer he ransmiing device has released he bus. See Figure 5. cknowledge cknowledge is a sofware convenion used o indicae successful daa ransfer. The ransmiing device, eiher maser or slave, will release he bus afer ransmiing eigh bis. During he ninh clock cycle, he receiver will pull he SD line LOW o acknowledge ha i received he eigh bis of daa. Refer o Figure 6. The device will respond wih an acknowledge afer recogniion of a sar condiion and if he correc Device Idenifier and Selec bis are conained in he Slave ddress Bye. If a wrie operaion is seleced, he device will respond wih an acknowledge afer he receip of each subsequen eigh bi word. The device will acknowledge all incoming daa and address byes, excep for: The Slave ddress Bye when he Device Idenifier and/or Selec bis are incorrec ll Daa Byes of a wrie when he WEL in he Wrie Proec Regiser is LOW The 2nd Daa Bye of a Saus Regiser Wrie Operaion (only daa bye is allowed) In he read mode, he device will ransmi eigh bis of daa, release he SD line, hen monior he line for an acknowledge. If an acknowledge is deeced and no sop condiion is generaed by he maser, he device will coninue o ransmi daa. The device will erminae furher daa ransmissions if an acknowledge is no deeced. The maser mus hen issue a sop condiion o reurn he device o Sandby mode and place he device ino a known sae. FN80 Rev.00 Page 4 of 25
Figure 4. Valid Daa hanges on he SD Bus SL SD Daa Sable Daa hange Daa Sable Figure 5. Valid Sar and Sop ondiions SL SD Sar Sop Figure 6. cknowledge Response From Receiver SL from Maser 8 9 Daa Oupu from Transmier Daa Oupu from Receiver Sar cknowledge DEVIE DDRESSING Following a sar condiion, he maser mus oupu a Slave ddress Bye. The firs four bis of he Slave ddress Bye specify access o eiher he EEPROM array or o he R. Slave bis 00 access he EEPROM array. Slave bis 0 access he R. When shipped from he facory, EEPROM array is UNDEFINED, and should be programmed by he cusomer o a known sae. Bi 3 hrough Bi of he slave bye specify he device selec bis. These are se o. The las bi of he Slave ddress Bye defines he operaion o be performed. When his R/W bi is a one, hen a read operaion is seleced. zero selecs a wrie operaion. Refer o Figure 7. fer loading he enire Slave ddress Bye from he SD bus, he X286 compares he device idenifier and device selec bis wih 00 or 0. Upon a correc compare, he device oupus an acknowledge on he SD line. Following he Slave Bye is a wo bye word address. The word address is eiher supplied by he maser device or obained from an inernal couner. On powerup he inernal address couner is se o address 0h, so a curren address read of he EEPROM array sars a address 0. When required, as par of a random read, he maser mus supply he 2 Word ddress Byes as shown in Figure 7. In a random read operaion, he slave bye in he dummy wrie porion mus mach he slave bye in he read secion. Tha is if he random read is from he array he slave bye mus be 00x in boh insances. Similarly, for a random read of he lock/onrol Regisers, he slave bye mus be 0x in boh places. FN80 Rev.00 Page 5 of 25
Figure 7. Slave ddress, Word ddress, and Daa Byes (28 Bye pages) Device Idenifier rray R 0 0 0 R/W Slave ddress Bye Bye 0 0 4 3 2 0 9 8 Word ddress Bye 7 6 5 4 3 2 0 Word ddress 0 Bye 2 D7 D6 D5 D4 D3 D2 D D0 Daa Bye Bye 3 Wrie Operaions Bye Wrie For a wrie operaion, he device requires he Slave ddress Bye and he Word ddress Byes. This gives he maser access o any one of he words in he array or R. (Noe: Prior o wriing o he R, he maser mus wrie a 02h, hen 06h o he saus regiser in wo preceding operaions o enable he wrie operaion. See Wriing o he lock/onrol Regisers. Upon receip of each address bye, he X286 responds wih an acknowledge. fer receiving boh address byes he X286 awais he eigh bis of daa. fer receiving he 8 daa bis, he X286 again responds wih an acknowledge. The maser hen erminaes he ransfer by generaing a sop condiion. The X286 hen begins an inernal wrie cycle of he daa o he nonvolaile memory. During he inernal wrie cycle, he device inpus are disabled, so he device will no respond o any requess from he maser. The SD oupu is a high impedance. See Figure 8. wrie o a proeced block of memory is ignored, bu will sill receive an acknowledge. he end of he wrie command, he X286 will no iniiae an inernal wrie cycle, and will coninue o commands. Page Wrie The X286 has a page wrie operaion. I is iniiaed in he same manner as he bye wrie operaion; bu insead of erminaing he wrie cycle afer he firs daa bye is ransferred, he maser can ransmi up o 27 more byes o he memory array and up o 7 more byes o he clock/conrol regisers. (Noe: Prior o wriing o he R, he maser mus wrie a 02h, hen 06h o he saus regiser in wo preceding operaions o enable he wrie operaion. See Wriing o he lock/onrol Regisers. fer he receip of each bye, he X286 responds wih an acknowledge, and he address is inernally incremened by one. When he couner reaches he end of he page, i rolls over and goes back o he firs address on he same page. This means ha he maser can wrie 28 byes o a memory array page or 8 byes o a R secion saring a any locaion on ha page. For example, if he maser begins wriing a locaion 05 of he memory and loads 30 byes, hen he firs 23 byes are wrien o addresses 05 hrough 27, and he las 7 byes are wrien o columns 0 hrough 6. ferwards, he address couner would poin o locaion 7 on he page ha was jus wrien. If he maser supplies more han he maximum byes in a page, hen he previously loaded daa is over wrien by he new daa, one bye a a ime. Refer o Figure 9. The maser erminaes he Daa Bye loading by issuing a sop condiion, which causes he X286 o begin he nonvolaile wrie cycle. s wih he bye wrie operaion, all inpus are disabled unil compleion of he inernal wrie cycle. Refer o Figure 0 for he address, acknowledge, and daa ransfer sequence. Sops and Wrie Modes Sop condiions ha erminae wrie operaions mus be sen by he maser afer sending a leas full daa bye and i s associaed signal. If a sop is issued in he middle of a daa bye, or before full daa bye + is sen, hen he X286 reses iself wihou performing he wrie. The conens of he array are no affeced. FN80 Rev.00 Page 6 of 25
Figure 8. Bye Wrie Sequence Signals from he Maser S a r Slave ddress Word ddress Word ddress 0 Daa S o p SD Bus 0 0 Signals From The Slave Figure 9. Wriing 30 byes o a 28-bye memory page saring a address 05. 7 Byes 23 Byes ddress = 6 ddress Poiner Ends Here ddr = 7 ddress 05 ddress 27 Figure 0. Page Wrie Sequence Signals from he Maser S a r Slave ddress Word ddress Word ddress 0 n 28 for EEPROM array n 8 for R Daa () Daa (n) S o p SD Bus 0 0 Signals from he Slave FN80 Rev.00 Page 7 of 25
cknowledge Polling Disabling of he inpus during nonvolaile wrie cycles can be used o ake advanage of he ypical 5mS wrie cycle ime. Once he sop condiion is issued o indicae he end of he maser s bye load operaion, he X286 iniiaes he inernal nonvolaile wrie cycle. cknowledge polling can begin immediaely. To do his, he maser issues a sar condiion followed by he Slave ddress Bye for a wrie or read operaion. If he X286 is sill busy wih he nonvolaile wrie cycle hen no will be reurned. When he X286 has compleed he wrie operaion, an is reurned and he hos can proceed wih he read or wrie operaion. Refer o he flow char in Figure 2. Read Operaions There are hree basic read operaions: urren ddress Read, Random Read, and Sequenial Read. urren ddress Read Inernally he X286 conains an address couner ha mainains he address of he las word read incremened by one. Therefore, if he las read was o address n, he nex read operaion would access daa from address n+. On power-up, he sixeen bi address is iniialized o 0h. In his way, a curren address read immediaely afer he power-onpower-on rese can download he enire conens of memory saring a he firs locaion.upon receip of he Slave ddress Bye wih he R/W bi se o one, he X286 issues an acknowledge, hen ransmis eigh daa bis. The maser erminaes he read operaion by no responding wih an acknowledge during he ninh clock and issuing a sop condiion. Refer o Figure for he address, acknowledge, and daa ransfer sequence. Figure 2. cknowledge Polling Sequence Bye load compleed by issuing STOP. Ener Polling Issue STRT Issue Slave ddress Bye (Read or Wrie) reurned? YES nonvolaile wrie ycle complee. oninue command sequence? YES oninue normal Read or Wrie command sequence PROEED NO NO Issue STOP Issue STOP Figure. urren ddress Read Sequence Signals from he Maser S a r Slave ddress S o p SD Bus Signals from he Slave Daa FN80 Rev.00 Page 8 of 25
I should be noed ha he ninh clock cycle of he read operaion is no a don care. To erminae a read operaion, he maser mus eiher issue a sop condiion during he ninh cycle or hold SD HIGH during he ninh clock cycle and hen issue a sop condiion. Random Read Random read operaions allows he maser o access any locaion in he X286. Prior o issuing he Slave ddress Bye wih he R/W bi se o zero, he maser mus firs perform a dummy wrie operaion. The maser issues he sar condiion and he slave address bye, receives an acknowledge, hen issues he word address byes. fer acknowledging receip of each word address bye, he maser immediaely issues anoher sar condiion and he slave address bye wih he R/W bi se o one. This is followed by an acknowledge from he device and hen by he eigh bi daa word. The maser erminaes he read operaion by no responding wih an acknowledge and hen issuing a sop condiion. Refer o Figure 3 for he address, acknowledge, and daa ransfer sequence. In a similar operaion called Se urren ddress, he device ses he address if a sop is issued insead of he second sar shown in Figure 3. The X286 hen goes ino sandby mode afer he sop and all bus aciviy will be ignored unil a sar is deeced. This operaion loads he new address ino he address couner. The nex urren ddress Read operaion will read from he newly loaded address. This operaion could be useful if he maser knows he nex address i needs o read, bu is no ready for he daa. Sequenial Read Sequenial reads can be iniiaed as eiher a curren address read or random address read. The firs daa bye is ransmied as wih he oher modes; however, he maser now responds wih an acknowledge, indicaing i requires addiional daa. The device coninues o oupu daa for each acknowledge received. The maser erminaes he read operaion by no responding wih an acknowledge and hen issuing a sop condiion. The daa oupu is sequenial, wih he daa from address n followed by he daa from address n +. The address couner for read operaions incremens hrough all page and column addresses, allowing he enire memory conens o be serially read during one operaion. he end of he address space he couner rolls over o he sar of he address space and he X286 coninues o oupu daa for each acknowledge received. Refer o Figure 4 for he acknowledge and daa ransfer sequence. Figure 3. Random ddress Read Sequence Signals from he Maser S a r Slave ddress Word ddress Word ddress 0 S a r Slave ddress S o p SD Bus Signals from he Slave 0 0 Daa Figure 4. Sequenial Read Sequence Signals from he Maser Slave ddress S o p SD Bus Signals from he Slave Daa () Daa (2) Daa (n-) Daa (n) (n is any ineger greaer han ) FN80 Rev.00 Page 9 of 25
PPLITION SETION RYSTL OSILLTOR ND TEMPERTURE OM- PENSTION Inersil has now inegraed he oscillaor compensaion circuiy on-chip, o eliminae he need for exernal componens and adjus for crysal drif over emperaure and enable very high accuracy ime keeping (<5ppm drif). The Inersil RT family uses an oscillaor circui wih onchip crysal compensaion nework, including adjusable load-capaciance. The only exernal componen required is he crysal. The compensaion nework is opimized for operaion wih cerain crysal parameers which are common in many of he surface moun or uning-fork crysals available oday. Table 6 summarizes hese parameers. Table 7 conains some crysal manufacurers and par numbers ha mee he requiremens for he Inersil RT producs. The urnover emperaure in Table 7 describes he emperaure where he apex of he of he drif vs. emperaure curve occurs. This curve is parabolic wih he drif increasing as (T-T0) 2. For an Epson M-405 device, for example, he urnover emperaure is ypically 25 deg, and a peak drif of >0ppm occurs a he emperaure exremes of -40 and +85 deg. I is possible o address his variable drif by adjusing he load capaciance of he crysal, which will resul in predicable change o he crysal frequency. The Inersil RT family allows his adjusmen over emperaure since he devices include on-chip load capacior rimming. This conrol is handled by he nalog Trimming Regiser, or TR, which has 6 bis of conrol. The load capaciance range covered by he TR circui is approximaely 3.25pF o 8.75pF, in 0.25pf incremens. Noe ha acual capaciance would also include abou 2pF of package relaed capaciance. In-circui ess wih commercially available crysals demonsrae ha his range of capaciance allows frequency conrol from +6ppm o -37ppm, using a 2.5pF load crysal. In addiion o he analog compensaion afforded by he adjusable load capaciance, a digial compensaion feaure is available for he Inersil RT family. There are hree bis known as he Digial Trimming Regiser or DTR, and hey operae by adding or skipping pulses in he clock signal. The range provided is ±30ppm in incremens of 0ppm. The defaul seing is 0ppm. The DTR conrol can be used for coarse adjusmens of frequency drif over emperaure or for crysal iniial accuracy correcion. Table 7. rysal Parameers Required for Inersil RT s Parameer Min Typ Max Unis Noes Frequency 32.768 khz Freq. Tolerance ±00 ppm Down o 20ppm if desired Turnover Temperaure 20 25 30 Typically he value used for mos crysals Operaing Temperaure Range -40 85 Parallel Load apaciance 2.5 pf Equivalen Series Resisance 50 k For bes oscillaor performance Table 8. rysal Manufacurers Manufacurer Par Number Temp Range +25 Freq Toler. iizen M20, M202, M200S -40 o +85 ±20ppm Epson M-405, M-406-40 o +85 ±20ppm Ralron RSM-200S- or B -40 o +85 ±20ppm SaRonix 32S2 or B -40 o +85 ±20ppm Eclipek EPSM29T-32.768-0 o +60 ±20ppm ES EX-306/EX-306I -0 o +60 ±20ppm Fox FSM-327-40 o +85 ±20ppm FN80 Rev.00 Page 20 of 25
final applicaion for he TR conrol is in-circui calibraion for high accuracy applicaions, along wih a emperaure sensor chip. Once he RT circui is powered up wih baery backup, he PHZ oupu is se a 32.768kHz and frequency drif is measured. The TR conrol is hen adjused o a seing which minimizes drif. Once adjused a a paricular emperaure, i is possible o adjus a oher discree emperaures for minimal overall drif, and sore he resuling seings in he EEPROM. Exremely low overall emperaure drif is possible wih his mehod. The Inersil evaluaion board conains he circuiry necessary o implemen his conrol. For more deailed operaion see Inersil s applicaion noe N54 on Inersil s websie a www.inersil.com. Layou onsideraions The crysal inpu a X has a very high impedance and will pick up high frequency signals from oher circuis on he board. Since he X2 pin is ied o he oher side of he crysal, i is also a sensiive node. These signals can couple ino he oscillaor circui and produce double clocking or mis-clocking, seriously affecing he accuracy of he RT. are needs o be aken in layou of he RT circui o avoid noise pickup. Below in Figure 5 is a suggesed layou for he X286 or X288 devices. Figure 5. Suggesed Layou for Inersil RT in SO-8 XTL 32.768kGz R 0k U X286/X288 The X and X2 connecions o he crysal are o be kep as shor as possible. hick ground race around he crysal is advised o minimize noise inrusion, bu ground near he X and X2 pins should be avoided as i will add o he load capaciance a hose pins. eep in mind hese guidelines for oher PB layers in he viciniy of he RT device. small decoupling capacior a he Vcc pin of he chip is mandaory, wih a solid connecion o ground. The X286 produc has a special consideraion. The PHZ/IRQ- pin on he 8 Ld SOI package is locaed nex o he X2 pin. When his pin is used as a frequency oupu (PHZ) and is se o 32.768kHz oupu frequency, 0.µF noise can couple o he X or X2 pins and cause doubleclocking. The layou in figure 5 can help minimize his by running he PHZ oupu away from he X and X2 pins. lso, minimizing he swiching curren a his pin by careful selecion of he pullup resisor value will reduce noise. Inersil suggess a minimum value of 5.k for 32.768kHz, and higher values (i.e. 20k ) for lower frequency PHZ oupus. For oher RT producs, he same rules saed above should be observed, bu adjused slighly since he packages and pinous are slighly differen. ssembly Mos elecronic circuis do no have o deal wih assembly issues, bu wih he RT devices assembly includes inserion or soldering of a live baery ino an unpowered circui. If a socke is soldered o he board, and a baery is insered in final assembly, hen here are no issues wih operaion of he RT. If he baery is soldered o he board direcly, hen he RT device Vback pin will see some ransien upse from eiher soldering ools or inermien baery connecions which can sop he circui from oscillaing. Once he baery is soldered o he board, he only way o assure he circui will sar up is o momenarily (very shor period of ime!) shor he Vback pin o ground and he circui will begin o oscillae. Oscillaor Measuremens When a proper crysal is seleced and he layou guidelines above are observed, he oscillaor should sar up in mos circuis in less han one second. Some circuis may ake slighly longer, bu sarup should definiely occur in less han 5 seconds. When esing RT circuis, he mos common impulse is o apply a scope probe o he circui a he X2 pin (oscillaor oupu) and observe he waveform. DO NOT DO THIS! lhough in some cases you may see a useable waveform, due o he parasiics (usually 0pF o ground) applied wih he scope probe, here will be no useful informaion in ha waveform oher han he fac ha he circui is oscillaing. The X2 oupu is sensiive o capaciive impedance so he volage levels and he frequency will be affeced by he parasiic elemens in he scope probe. pplying a scope probe can possibly cause a fauly oscillaor o sar up, hiding oher issues (alhough in he Inersil RT s, he inernal circuiry assures sarup when using he proper crysal and layou). The bes way o analyze he RT circui is o power i up and read he real ime clock as ime advances, or if he chip has he PHZ oupu, look a he oupu of ha pin on an oscilloscope (afer enabling i wih he conrol regiser, and using a pullup resisor for an open-drain oupu). lernaively, he X226/X286/288 devices have an IRQ- oupu which can be checked by seing an alarm FN80 Rev.00 Page 2 of 25