Features Floating channel designed for bootstrap operation Fully operational to +00V Tolerant to negative transient voltage dv/dt immune Gate drive supply range from 0 to 0V Undervoltage lockout for both channels chmitt triggered input logic Matched propagation delay for both channels Logic and power ground +/- V offset. Lower di/dt gate driver for better noise immunity Outputs in phase with inputs (I0/I0) Outputs out of phase with inputs (I0/I0) Description The I0/I0/I0/I0 are high voltage, high speed power MOSFET and IGBT drivers with independent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 00 volts. Typical Connection Preliminary Data Sheet No. PD0I HIGH AND W SIDE DIVE Product Summary V OFFSET I O +/- V OUT t on/off (typ.) Delay matching Packages Lead SOIC Lead PDIP I0/I0 I0/I0 00V max. 0 ma / 0 ma 0-0V 0 ns 0 ns Lead SOIC Lead PDIP up to 00V / / TO AD up to 00V I0/I0 I0/I0 / / TO AD S S
I0/I0/I0/I0 Absolute Maximum atings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units High side floating absolute voltage -0. High side floating supply offset voltage - + 0. V High side floating output voltage - 0. + 0. Low side and logic fixed supply voltage -0. V Low side output voltage -0. + 0. V IN Logic input voltage ( & - I0/I0) ( & - I0/I0) S - 0. + 0. S Logic ground (I0/I0 only) - + 0. d /dt Allowable offset supply voltage transient 0 V/ns P D Package power dissipation @ T A + C ( lead PDIP).0 ( lead SOIC) 0. ( lead PDIP). W ( lead SOIC).0 th JA Thermal resistance, junction to ambient ( lead PDIP) ( lead SOIC) 00 ( lead PDIP) C/W ( lead SOIC) 0 T J Junction temperature 0 T S Storage temperature -0 0 C T L Lead temperature (soldering, 0 seconds) 00 ecommended Operating Conditions The Input/Output logic timing diagram is shown in figure. For proper operation the device should be used within the recommended conditions. The and S offset rating are tested with all supplies biased at V differential. Symbol Definition Min. Max. Units VB High side floating supply absolute voltage + 0 + 0 High side floating supply offset voltage Note 00 V High side floating output voltage Low side and logic fixed supply voltage 0 0 V Low side output voltage 0 V V IN Logic input voltage ( & - I0/I0) ( & - I0/I0) S S Logic ground (I0/I0 only) - T A Ambient temperature -0 C Note : Logic operational for of - to +00V. Logic state held for of -V to -S. V
Dynamic Electrical Characteristics IAS (, S ) = V, S =, C L = 000 pf, T A = C. I0/I0/I0/I0 Symbol Definition Min. Typ. Max. Units Test Conditions ton Turn-on propagation delay 0 0 = 0V toff Turn-off propagation delay 0 0 = 0V or 00V MT Delay matching, HS & LS turn-on/off 0 0 nsec tr Turn-on rise time 0 0 = 0V tf Turn-off fall time 0 0 = 0V Static Electrical Characteristics IAS (, S ) = V, S = and T A = C unless otherwise specified. The V IL, V IH and I IN parameters are referenced to S / and are applicable to the respective input leads: and (I0/I0) and and (I0/I0). The V O, I O and on parameters are referenced to and are applicable to the respective output leads: and. Symbol Definition Min. Typ. Max. Units Test Conditions V IH Logic input voltage (I0/I0) Logic 0 input voltage (I0/I0) V IL Logic 0 input voltage (I0/I0) Logic input voltage (I0/I0). 0. V = 0V to 0V = 0V to 0V V OH High level output voltage, IAS - V O 0.. I O = 0 ma V OL Low level output voltage, V O 0. 0. I O = 0 ma I LK Offset supply leakage current 0 = = 00V I QBS Quiescent S supply current 0 0 0 V IN = 0V or V I QCC Quiescent supply current 0 0 0 ma V IN = 0V or V I IN+ Logic input bias current 0 0 µa V IN = V (I0()) V IN = 0V (I0()) I IN- Logic 0 input bias current V IN = 0V (I0()).0 V IN = V (I0()) + and S supply undervoltage positive going.0.9 9. S+ threshold - and S supply undervoltage negative going.. 9.0 S- threshold V H Hysteresis 0. 0. SH I O+ Output high short circuit pulsed current 0 00 V O = 0V, PW 0 µs I O- Output low short circuit pulsed current 0 0 ma V O = V, PW 0 µs
I0/I0/I0/I0 Functional Block Diagram 0 DELAY VCC VS VB FILTE HV E S Q GENEATO / / 0 DELAY VCC VS VB FILTE HV E S Q GENEATO / /
I0/I0/I0/I0 0 DELAY VCC VS VB FILTE HV E S Q GENEATO / / +V +V 0 DELAY VCC VS VB FILTE HV E S Q GENEATO / / +V +V
I0/I0/I0/I0 Lead Definitions Symbol Description Logic input for high side gate driver output (), in phase (I0/I0) Logic input for high side gate driver output (), out of phase (I0/I0) Logic input for low side gate driver output (), in phase (I0/I0) Logic input for low side gate driver output (), out of phase (I0/I0) Logic Ground (I0 and I0 only) High side floating supply High side gate drive output High side floating supply return Low side and logic fixed supply Low side gate drive output Low side return Lead Assignments Lead PDIP Lead SOIC I0 I0S 0 0 9 9 Lead PDIP Lead SOIC I0 I0S
I0/I0/I0/I0 Lead PDIP Lead SOIC I0 I0S 0 0 9 9 Lead PDIP Lead SOIC I0 I0S
I0/I0/I0/I0 Lead PDIP 0-00 0 Lead SOIC 0-00 0
I0/I0/I0/I0 Lead PDIP 0-00 0 Lead SOIC (narrow body) 9 0-0 00
I0/I0/I0/I0 0% 0% Figure. Input/Output Timing Diagram t on 0% 0% t r t off t f 90% 90% 0% 0% 0% 0% Figure. Switching Time Waveform Definitions 0% 0% 0% MT MT 90% Figure. Delay Matching Waveform Definitions WOLD HEADQUATES: Kansas St., El Segundo, California 90 Tel: (0) I GEAT BITAIN: Hurst Green, Oxted, Surrey H 9BB, UK Tel: ++ 00 I CANADA: Lincoln Court, Brampton, Ontario LT Z Tel: (90) -00 I GEMANY: Saalburgstrasse, 0 Bad Homburg Tel: ++ 9 990 I ITALY: Via Liguria 9, 00 Borgaro, Torino Tel: ++ 9 0 I FA EAST: K&H Bldg., F, 0- Nishi-Ikebukuro -Chome, Toshima-Ku, Tokyo, Japan Tel: 9 00 I SOUTHEAST ASIA: Kim Seng Promenade, Great World City West Tower, -, Singapore 99 Tel: 0 I TAIWAN: Fl. Suite D..0, Sec., Tun Haw South oad, Taipei, 0, Taiwan Tel: ---99 http://www.irf.com/ Data and specifications subject to change without notice. //99 0