HOW TO CONTINUE COST SCALING. Hans Lebon

Similar documents
Outline. Introduction on IMEC & IMEC cooperation model. Program Challenges in CMOS scaling

450mm and Moore s Law Advanced Packaging Challenges and the Impact of 3D

IC Knowledge LLC, PO Box 20, Georgetown, MA Ph: (978) , Fx: (978)

PUSHING LITHOGRAPHY TO ENABLE ULTIMATE NANO-ELECTRONICS. LUC VAN DEN HOVE President & CEO imec

Thermal Management in the 3D-SiP World of the Future

Enabling Breakthroughs In Technology

FinFET vs. FD-SOI Key Advantages & Disadvantages

Innovation to Advance Moore s Law Requires Core Technology Revolution

The Development of the Semiconductor CVD and ALD Requirement

NEXT GENERATION SILICON PHOTONICS FOR COMPUTING AND COMMUNICATION PHILIPPE ABSIL

MAPPER: High throughput Maskless Lithography

Device architectures for the 5nm technology node and beyond Nadine Collaert

Fin-Shaped Field Effect Transistor (FinFET) Min Ku Kim 03/07/2018

Advanced PDK and Technologies accessible through ASCENT

Lecture: Integration of silicon photonics with electronics. Prepared by Jean-Marc FEDELI CEA-LETI

ATV 2011: Computer Engineering

NANOELECTRONIC TECHNOLOGY: CHALLENGES IN THE 21st CENTURY

Parameter Optimization Of GAA Nano Wire FET Using Taguchi Method

Semiconductor Memory: DRAM and SRAM. Department of Electrical and Computer Engineering, National University of Singapore

Nanotechnology, the infrastructure, and IBM s research projects

Intel's 65 nm Logic Technology Demonstrated on 0.57 µm 2 SRAM Cells

ICT Micro- and nanoelectronics technologies

Technological Challenges in Semiconductor Lithography

How material engineering contributes to delivering innovation in the hyper connected world

Coordination Action to enable an effective European 450 mm Equipment & Materials Network

Competitive in Mainstream Products

Integrated Photonics using the POET Optical InterposerTM Platform

SoC Technology in the Era of 3-D Tri-Gate Transistors for Low Power, High Performance, and High Density Applications

ITRS MOSFET Scaling Trends, Challenges, and Key Technology Innovations

III-V CMOS: Quo Vadis?

Alternatives to standard MOSFETs. What problems are we really trying to solve?

Si and InP Integration in the HELIOS project

IMI Labs Semiconductor Applications. June 20, 2016

The future of lithography and its impact on design

In pursuit of high-density storage class memory

III-V on Si for VLSI. 200 mm III-V on Si. Accelerating the next technology revolution. III-V nfet on 200 mm Si

SiNANO-NEREID Workshop:

SOI technology platforms for 5G: Opportunities of collaboration

EECS130 Integrated Circuit Devices

Multiple Patterning for Immersion Extension and EUV Insertion. Chris Bencher Distinguished Member of Technical Staff Applied Materials CTO group

ITRS Update (and the European situation) Mart Graef Delft University of Technology

Chapter 7 Introduction to 3D Integration Technology using TSV

Opportunities and Challenges for Nanoelectronic Devices and Processes

Towards a Reconfigurable Nanocomputer Platform

Integration of III-V heterostructure tunnel FETs on Si using Template Assisted Selective Epitaxy (TASE)

Limitations and Challenges to Meet Moore's Law

Silicon Photonics Technology Platform To Advance The Development Of Optical Interconnects

Sub-micron technology IC fabrication process trends SOI technology. Development of CMOS technology. Technology problems due to scaling

A Perspective on Semiconductor Equipment. R. B. Herring March 4, 2004

EUROSOI+- FP of 38 30/06/ FINAL PUBLISHABLE SUMMARY REPORT

FinFET Devices and Technologies

TWINSCAN XT:1950i Water-based immersion taken to the max Enabling fast, single-exposure lithography at sub 40 nm

Newer process technology (since 1999) includes :

45nm Foundry CMOS with Mask-Lite Reduced Mask Costs

Si photonics for the Zettabyte Era. Marco Romagnoli. CNIT & TeCIP - Scuola Superiore Sant Anna

Technology & Manufacturing

New silicon photonics technology delivers faster data traffic in data centers

EECS 151/251A Spring 2019 Digital Design and Integrated Circuits. Instructors: Wawrzynek. Lecture 8 EE141

Low-Power VLSI. Seong-Ook Jung VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering

Fabricating 2.5D, 3D, 5.5D Devices

Transistor Scaling in the Innovation Era. Mark Bohr Intel Senior Fellow Logic Technology Development August 15, 2011

New Process Technologies Will silicon CMOS carry us to the end of the Roadmap?

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices

Silicon Photonics Photo-Detector Announcement. Mario Paniccia Intel Fellow Director, Photonics Technology Lab

InAs Quantum-Well MOSFET for logic and microwave applications

INSPECTION AND REVIEW PORTFOLIO FOR 3D FUTURE

Process Variability and the SUPERAID7 Approach

Sustaining the Si Revolution: From 3D Transistors to 3D Integration

EECS130 Integrated Circuit Devices

PERSPECTIVES FOR DISRUPTIVE 200MM/8-INCH GAN POWER DEVICE AND GAN-IC TECHNOLOGY DR. DENIS MARCON SR. BUSINESS DEVELOPMENT MANAGER

3-D Modelling of the Novel Nanoscale Screen-Grid Field Effect Transistor (SGFET)

Nanometer-Scale InGaAs Field-Effect Transistors for THz and CMOS Technologies

Tunneling Field Effect Transistors for Low Power ULSI

Session 3: Solid State Devices. Silicon on Insulator

Beyond Moore the challenge for Europe

HfO 2 Based Resistive Switching Non-Volatile Memory (RRAM) and Its Potential for Embedded Applications

Near/Mid-Infrared Heterogeneous Si Photonics

A 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistors

Practical Information

IMEC's Collaboration Models for Nanoelectronics Research and Role of the PRINS Research Infrastructure

Practical Information

32nm Technology and Beyond

Silicon Photonics in Optical Communications. Lars Zimmermann, IHP, Frankfurt (Oder), Germany

Introduction to CMC 3D Test Chip Project

Project SUPERAID7: Stability Under Process Variability for Advanced Interconnects and Devices Beyond 7nm node

EUV Supporting Moore s Law

Leading at the edge TECHNOLOGY AND MANUFACTURING DAY

Innovative ultra-broadband ubiquitous Wireless communications through terahertz transceivers ibrow

Envisioning the Future of Optoelectronic Interconnects:

THE WAFER FAB CLEANS IN SEMICONDUCTOR INDUSTRY FROM A MATERIALS SUPPLIER PERSPECTIVE

Direct printing tools for flexible hybrid electronics assembly. David Grierson, Ph.D. President & CTO of systemech, LLC

Progress due to: Feature size reduction - 0.7X/3 years (Moore s Law). Increasing chip size - 16% per year. Creativity in implementing functions.

Silicon Photonics: an Industrial Perspective

Low Energy Communication: NanoPhotonic & Electrical. Prof. Eli Yablonovitch EECS Dept. UC Berkeley

Highlights in Microtechnology HiM 2014, EPFL IMT-NE, June 18 th, 2014

Changing the Approach to High Mask Costs

FOR SEMICONDUCTORS 2009 EDITION

Used Semiconductor Manufacturing Equipment: Looking for Sales in All the Right Places. Study Number MA108-09

Lithography in our Connected World

III-V CMOS: the key to sub-10 nm electronics?

Transcription:

HOW TO CONTINUE COST SCALING Hans Lebon

OUTLINE Scaling & Scaling Challenges Imec Technology Roadmap Wafer size scaling : 450 mm 2

COST SCALING IMPROVED PERFORMANCE 3

GLOBAL TRAFFIC FORECAST Cloud Traffic MOBILE DATA Exabytes per month (10 18 ) Zettabytes per year (10 21 ) 4 How will we make this happen at an IMEC affordable 2014 / CONFIDENTIAL INDIVIDUAL cost? USE

MOORE S LAW CONTINOUS 1970: Lithography enabled scaling 2002: Materials enabled scaling 14nm: 3D enabled scaling Wafer size scaling : 450 mm 5

INCREASING TECHNOLOGY COMPLEXITY Scaling down to <10nm EUV Litho Multi pat. HKMG FDSOI FinFET Ge / IIIV TFET Nanowire STT-MRAM RRAM 3D SONOS... 60 70 80 90 00 10 6

7

Scaling & Scaling Challenges Imec Technology Roadmap Wafer size scaling : 450 mm 8

LOGIC SCALING ROADMAP Vdd 1.0-1.1V 0.9-1.0V 0.8-0.9V 0.7-0.8V 0.6-0.7V 0.5-0.6V < 0.5V MATERIAL DEVICE MATERIAL DEVICE MATERIAL METAL GATE HIGH K FINFET FINFET HIGH MOBILITY CHANNELS NANOWIRE/ TUNNEL FETs 2D MATERIALS MG High-k Si substrate 45nm 32/28nm 22/20nm 14nm 10nm 7nm 5nm... Tech Node 9

LOGIC : 14 nm 10 nm FinFET Conducting channel is wrapped by a thin silicon fin Fully depleted device: better short channel control Strain engineering to boost performance and scale down to 10nm 10

LOGIC : 10 nm 7 nm Ge InGa As InP GaAs Ge Si High-mobility channels Boost channel mobility by using Ge and III-V materials in the channel Two options: Ge-Ge and Ge-InGaAs for p-n channels 11

LOGIC : 10 nm 7 nm Gate-all around finfet Nanowire transistors with channel completely wrapped by the gate Superior gate leakage control 12

LOGIC : BEYOND 7 nm InAs Nano wire on <111> Si Vertical finfet FinFET with vertical nanowires 13

LOGIC : BEYOND 7 nm TunnelFET Sub-60mV/decade subtreshold slope, allowing further reduction of supply voltage and power reduction 14

LOGIC : BEYOND 5 nm Many different options under research: Graphene FET, spintronics, BISFET, Ge tunnelfet, InAs tunnelfet, Graphene FET, spintorque,... 15

MEMORY : BEYOND 20 nm STT RAM STT RAM DRAM replacement beyond 20nm <20 nm Non-volatile memory for both embedded and stand-alone applications Information is stored by using spin current of electrons instead of charge current 16

MEMORY : TO 10 nm 3D SONOS Flash replacement to 10nm G D Non-volatile memory Memory cells implemented in vertical plugs consisting of 8,16,32... stacks S Successful processing of macaroni cell 17

MEMORY : BEYOND 10 nm G D S Resistive RAM Flash replacement beyond 10nm Non-volatile memory High speed, low energy, superior scalability, CMOS compatible Hourglass model: - Fundamental understanding of filament properties - Captures all main features of HfO2 RRAM device operation and reliability - Key for development of RRAM 18

3D enabled SCALING Gen.1 2012-2013 Gen.2 2014-2015 Gen.3 2016 -... 19

SILICON PHOTONICS World-first sub-100nm photonics components on 300mm Si technology with optical lithography in 28nm imec silicon photonics platform: cost-effective R&D of silicon photonics ICs for telecom, datacom, and life science applications 20

3D & OPTICAL IO Optical IO: extension of 3D stacking Further performance boosting, extreme high-bandwidth Optical interconnects using silicon photonics instead of electrical interconnects Fabrication of optical components by using CMOS processing techniques and equipment Need for best-in-class optical components 21

LITHOGRAPHY ENABLED SCALING EUV : 13.5 nm LITHOGRAPHY World-first sub-100nm photonics components on 300mm Si technology with optical lithography in 28nm imec silicon photonics platform: cost-effective R&D of silicon photonics ICs for telecom, datacom, and life science applications 22

DIRECTED SELF-ASSEMBLY Extending optical lithography beyond current limits Promising candidate for more effective frequency multiplication by using block co-polymer chemistry True bottom up approach for high resolution patterning 23

RESEARCH COMPLEXITY Technology complexity increases: Multitude of material options & processing techniques Combination of new materials & architectures System/circuit level implications Increasing amount of options 24

INCREASING R&D COST 25

CORE CMOS PARTNERS Logic & Memory IDM & Foundries Fablite & Fabless & OSAT Lam RESEARCH Share the R&D effort = Cost Sharing 26

STATE-OF-THE-ART RESEARCH FACILITIES 200mm pilot line Silicon solar cell line Organic solar cell line NERF lab Nano biolabs 300mm pilot line 450mm ready 27

EXPANSION OF OUR RESEARCH FACILITIES Silicon 200mm solar cell pilot line line Organic solar cell line NERF lab Nano biolabs 300mm pilot line 2016H1: 300/450 R&D ~ 10 000 m2 Clean Room/Pilot line line Continuous operation: 24hrs / 7 days 2011 expansion IMEC TOWER: Expansion of 14,208 m2 16 floors /450 people & lab space 28

CONSTRUCTION START H1 2014 CONSTRUCTION FINISH END 2015 29

Scaling & Scaling Challenges Imec Technology Roadmap Wafer size scaling : 450 mm 30

450mm x 2.25 300 mm 450 mm 31 Does Wafer Size Migration result in cost scaling?

WAFER BASED PROCESSING DEPOSITION, ETCHING, CLEANING,... (SERIAL) DIE BASED PROCESSING LITHOGRAPHY, IMPLANT, INSPECTION,... EFFICIENCY BENEFIT: 2.25x EFFICIENCY BENEFIT: 1x (2.25x reduced wph) BODY WAFER HANDLING PROCESS OPTIMIZATION BODY WAFER HANDLING PROCESS OPTIMIZATION THROUGHPUT Scaling yields increase of die based processing 32

IMEC WAFER SIZE CONVERSION HISTORY 1984: 4 Pilot-line 1986: 5 Pilot-line 1993: 6 Pilot-line 1999: 8 Pilot-line 2004: 12 Pilot-line 2016: 450 mm Pilot-line 33

ENIAC FP7 Flemish Gov t Industry Imec 450 mm migration KET HORIZON 2020 ENIAC Flemish Gov t Industry 2013 2014 2015 2016 2017 2018 2019 2020 450mm Equipment roadmaps 450mm Pilot 450mm Production phase 1 Selected Module assessment 300/450mm imec Fab1 450 mm ready facility @ imec EEMI450, SOI450, NGC450, EEM450PR, Phase 2 Process & Device development in Full flow facility 300/450mm imec Fab2 gradually 300/450 mm PILOT R&D facility @ imec 34

WAFER SIZE SCALING : 450 mm 450mm Equipment Alpha Hardware Definition of standards G450C EMI450 EMI450PR EMI450EDL 450 mm migration is feasible! Does 450 mm migration result in a significant cost saving? 450 mm migration waiting for industry commitment. 35

LET S WORK TOGETHER THANK YOU! 36